1 /*-
2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 /*
28 * i.MX6 Synchronous Serial Interface (SSI)
29 *
30 * Chapter 61, i.MX 6Dual/6Quad Applications Processor Reference Manual,
31 * Rev. 1, 04/2013
32 */
33
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
36
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/bus.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
42 #include <sys/malloc.h>
43 #include <sys/rman.h>
44 #include <sys/timeet.h>
45 #include <sys/timetc.h>
46
47 #include <dev/sound/pcm/sound.h>
48 #include <dev/sound/chip.h>
49 #include <mixer_if.h>
50
51 #include <dev/ofw/openfirm.h>
52 #include <dev/ofw/ofw_bus.h>
53 #include <dev/ofw/ofw_bus_subr.h>
54
55 #include <machine/bus.h>
56 #include <machine/cpu.h>
57 #include <machine/intr.h>
58
59 #include <arm/freescale/imx/imx6_sdma.h>
60 #include <arm/freescale/imx/imx6_anatopvar.h>
61 #include <arm/freescale/imx/imx_ccmvar.h>
62
63 #define READ4(_sc, _reg) \
64 bus_space_read_4(_sc->bst, _sc->bsh, _reg)
65 #define WRITE4(_sc, _reg, _val) \
66 bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val)
67
68 #define SSI_NCHANNELS 1
69 #define DMAS_TOTAL 8
70
71 /* i.MX6 SSI registers */
72
73 #define SSI_STX0 0x00 /* Transmit Data Register n */
74 #define SSI_STX1 0x04 /* Transmit Data Register n */
75 #define SSI_SRX0 0x08 /* Receive Data Register n */
76 #define SSI_SRX1 0x0C /* Receive Data Register n */
77 #define SSI_SCR 0x10 /* Control Register */
78 #define SCR_I2S_MODE_S 5 /* I2S Mode Select. */
79 #define SCR_I2S_MODE_M 0x3
80 #define SCR_SYN (1 << 4)
81 #define SCR_NET (1 << 3) /* Network mode */
82 #define SCR_RE (1 << 2) /* Receive Enable. */
83 #define SCR_TE (1 << 1) /* Transmit Enable. */
84 #define SCR_SSIEN (1 << 0) /* SSI Enable */
85 #define SSI_SISR 0x14 /* Interrupt Status Register */
86 #define SSI_SIER 0x18 /* Interrupt Enable Register */
87 #define SIER_RDMAE (1 << 22) /* Receive DMA Enable. */
88 #define SIER_RIE (1 << 21) /* Receive Interrupt Enable. */
89 #define SIER_TDMAE (1 << 20) /* Transmit DMA Enable. */
90 #define SIER_TIE (1 << 19) /* Transmit Interrupt Enable. */
91 #define SIER_TDE0IE (1 << 12) /* Transmit Data Register Empty 0. */
92 #define SIER_TUE0IE (1 << 8) /* Transmitter Underrun Error 0. */
93 #define SIER_TFE0IE (1 << 0) /* Transmit FIFO Empty 0 IE. */
94 #define SSI_STCR 0x1C /* Transmit Configuration Register */
95 #define STCR_TXBIT0 (1 << 9) /* Transmit Bit 0 shift MSB/LSB */
96 #define STCR_TFEN1 (1 << 8) /* Transmit FIFO Enable 1. */
97 #define STCR_TFEN0 (1 << 7) /* Transmit FIFO Enable 0. */
98 #define STCR_TFDIR (1 << 6) /* Transmit Frame Direction. */
99 #define STCR_TXDIR (1 << 5) /* Transmit Clock Direction. */
100 #define STCR_TSHFD (1 << 4) /* Transmit Shift Direction. */
101 #define STCR_TSCKP (1 << 3) /* Transmit Clock Polarity. */
102 #define STCR_TFSI (1 << 2) /* Transmit Frame Sync Invert. */
103 #define STCR_TFSL (1 << 1) /* Transmit Frame Sync Length. */
104 #define STCR_TEFS (1 << 0) /* Transmit Early Frame Sync. */
105 #define SSI_SRCR 0x20 /* Receive Configuration Register */
106 #define SSI_STCCR 0x24 /* Transmit Clock Control Register */
107 #define STCCR_DIV2 (1 << 18) /* Divide By 2. */
108 #define STCCR_PSR (1 << 17) /* Divide clock by 8. */
109 #define WL3_WL0_S 13
110 #define WL3_WL0_M 0xf
111 #define DC4_DC0_S 8
112 #define DC4_DC0_M 0x1f
113 #define PM7_PM0_S 0
114 #define PM7_PM0_M 0xff
115 #define SSI_SRCCR 0x28 /* Receive Clock Control Register */
116 #define SSI_SFCSR 0x2C /* FIFO Control/Status Register */
117 #define SFCSR_RFWM1_S 20 /* Receive FIFO Empty WaterMark 1 */
118 #define SFCSR_RFWM1_M 0xf
119 #define SFCSR_TFWM1_S 16 /* Transmit FIFO Empty WaterMark 1 */
120 #define SFCSR_TFWM1_M 0xf
121 #define SFCSR_RFWM0_S 4 /* Receive FIFO Empty WaterMark 0 */
122 #define SFCSR_RFWM0_M 0xf
123 #define SFCSR_TFWM0_S 0 /* Transmit FIFO Empty WaterMark 0 */
124 #define SFCSR_TFWM0_M 0xf
125 #define SSI_SACNT 0x38 /* AC97 Control Register */
126 #define SSI_SACADD 0x3C /* AC97 Command Address Register */
127 #define SSI_SACDAT 0x40 /* AC97 Command Data Register */
128 #define SSI_SATAG 0x44 /* AC97 Tag Register */
129 #define SSI_STMSK 0x48 /* Transmit Time Slot Mask Register */
130 #define SSI_SRMSK 0x4C /* Receive Time Slot Mask Register */
131 #define SSI_SACCST 0x50 /* AC97 Channel Status Register */
132 #define SSI_SACCEN 0x54 /* AC97 Channel Enable Register */
133 #define SSI_SACCDIS 0x58 /* AC97 Channel Disable Register */
134
135 static MALLOC_DEFINE(M_SSI, "ssi", "ssi audio");
136
137 uint32_t ssi_dma_intr(void *arg, int chn);
138
139 struct ssi_rate {
140 uint32_t speed;
141 uint32_t mfi; /* PLL4 Multiplication Factor Integer */
142 uint32_t mfn; /* PLL4 Multiplication Factor Numerator */
143 uint32_t mfd; /* PLL4 Multiplication Factor Denominator */
144 /* More dividers to configure can be added here */
145 };
146
147 static struct ssi_rate rate_map[] = {
148 { 192000, 49, 152, 1000 }, /* PLL4 49.152 Mhz */
149 /* TODO: add more frequences */
150 { 0, 0 },
151 };
152
153 /*
154 * i.MX6 example bit clock formula
155 *
156 * BCLK = 2 channels * 192000 hz * 24 bit = 9216000 hz =
157 * (24000000 * (49 + 152/1000.0) / 4 / 4 / 2 / 2 / 2 / 1 / 1)
158 * ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
159 * | | | | | | | | | | |
160 * Fref ------/ | | | | | | | | | |
161 * PLL4 div select -/ | | | | | | | | |
162 * PLL4 num --------------/ | | | | | | | |
163 * PLL4 denom -------------------/ | | | | | | |
164 * PLL4 post div ---------------------/ | | | | | |
165 * CCM ssi pre div (CCM_CS1CDR) ----------/ | | | | |
166 * CCM ssi post div (CCM_CS1CDR) -------------/ | | | |
167 * SSI PM7_PM0_S ---------------------------------/ | | |
168 * SSI Fixed divider ---------------------------------/ | |
169 * SSI DIV2 ----------------------------------------------/ |
170 * SSI PSR (prescaler /1 or /8) ------------------------------/
171 *
172 * MCLK (Master clock) depends on DAC, usually BCLK * 4
173 */
174
175 struct sc_info {
176 struct resource *res[2];
177 bus_space_tag_t bst;
178 bus_space_handle_t bsh;
179 device_t dev;
180 struct mtx *lock;
181 void *ih;
182 int pos;
183 int dma_size;
184 bus_dma_tag_t dma_tag;
185 bus_dmamap_t dma_map;
186 bus_addr_t buf_base_phys;
187 uint32_t *buf_base;
188 struct sdma_conf *conf;
189 struct ssi_rate *sr;
190 struct sdma_softc *sdma_sc;
191 uint32_t sdma_ev_rx;
192 uint32_t sdma_ev_tx;
193 int sdma_channel;
194 };
195
196 /* Channel registers */
197 struct sc_chinfo {
198 struct snd_dbuf *buffer;
199 struct pcm_channel *channel;
200 struct sc_pcminfo *parent;
201
202 /* Channel information */
203 uint32_t dir;
204 uint32_t format;
205
206 /* Flags */
207 uint32_t run;
208 };
209
210 /* PCM device private data */
211 struct sc_pcminfo {
212 device_t dev;
213 uint32_t (*ih)(struct sc_pcminfo *scp);
214 uint32_t chnum;
215 struct sc_chinfo chan[SSI_NCHANNELS];
216 struct sc_info *sc;
217 };
218
219 static struct resource_spec ssi_spec[] = {
220 { SYS_RES_MEMORY, 0, RF_ACTIVE },
221 { SYS_RES_IRQ, 0, RF_ACTIVE },
222 { -1, 0 }
223 };
224
225 static int setup_dma(struct sc_pcminfo *scp);
226 static void setup_ssi(struct sc_info *);
227 static void ssi_configure_clock(struct sc_info *);
228
229 /*
230 * Mixer interface.
231 */
232
233 static int
234 ssimixer_init(struct snd_mixer *m)
235 {
236 struct sc_pcminfo *scp;
237 struct sc_info *sc;
238 int mask;
239
240 scp = mix_getdevinfo(m);
241 sc = scp->sc;
242
243 if (sc == NULL)
244 return -1;
245
246 mask = SOUND_MASK_PCM;
247 mask |= SOUND_MASK_VOLUME;
248
249 snd_mtxlock(sc->lock);
250 pcm_setflags(scp->dev, pcm_getflags(scp->dev) | SD_F_SOFTPCMVOL);
251 mix_setdevs(m, mask);
252 snd_mtxunlock(sc->lock);
253
254 return (0);
255 }
256
257 static int
258 ssimixer_set(struct snd_mixer *m, unsigned dev,
259 unsigned left, unsigned right)
260 {
261 struct sc_pcminfo *scp;
262
263 scp = mix_getdevinfo(m);
264
265 /* Here we can configure hardware volume on our DAC */
266
267 #if 1
268 device_printf(scp->dev, "ssimixer_set() %d %d\n",
269 left, right);
270 #endif
271
272 return (0);
273 }
274
275 static kobj_method_t ssimixer_methods[] = {
276 KOBJMETHOD(mixer_init, ssimixer_init),
277 KOBJMETHOD(mixer_set, ssimixer_set),
278 KOBJMETHOD_END
279 };
280 MIXER_DECLARE(ssimixer);
281
282 /*
283 * Channel interface.
284 */
285
286 static void *
287 ssichan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b,
288 struct pcm_channel *c, int dir)
289 {
290 struct sc_pcminfo *scp;
291 struct sc_chinfo *ch;
292 struct sc_info *sc;
293
294 scp = (struct sc_pcminfo *)devinfo;
295 sc = scp->sc;
296
297 snd_mtxlock(sc->lock);
298 ch = &scp->chan[0];
299 ch->dir = dir;
300 ch->run = 0;
301 ch->buffer = b;
302 ch->channel = c;
303 ch->parent = scp;
304 snd_mtxunlock(sc->lock);
305
306 if (sndbuf_setup(ch->buffer, sc->buf_base, sc->dma_size) != 0) {
307 device_printf(scp->dev, "Can't setup sndbuf.\n");
308 return NULL;
309 }
310
311 return ch;
312 }
313
314 static int
315 ssichan_free(kobj_t obj, void *data)
316 {
317 struct sc_chinfo *ch = data;
318 struct sc_pcminfo *scp = ch->parent;
319 struct sc_info *sc = scp->sc;
320
321 #if 0
322 device_printf(scp->dev, "ssichan_free()\n");
323 #endif
324
325 snd_mtxlock(sc->lock);
326 /* TODO: free channel buffer */
327 snd_mtxunlock(sc->lock);
328
329 return (0);
330 }
331
332 static int
333 ssichan_setformat(kobj_t obj, void *data, uint32_t format)
334 {
335 struct sc_chinfo *ch = data;
336
337 ch->format = format;
338
339 return (0);
340 }
341
342 static uint32_t
343 ssichan_setspeed(kobj_t obj, void *data, uint32_t speed)
344 {
345 struct sc_pcminfo *scp;
346 struct sc_chinfo *ch;
347 struct ssi_rate *sr;
348 struct sc_info *sc;
349 int threshold;
350 int i;
351
352 ch = data;
353 scp = ch->parent;
354 sc = scp->sc;
355
356 sr = NULL;
357
358 /* First look for equal frequency. */
359 for (i = 0; rate_map[i].speed != 0; i++) {
360 if (rate_map[i].speed == speed)
361 sr = &rate_map[i];
362 }
363
364 /* If no match, just find nearest. */
365 if (sr == NULL) {
366 for (i = 0; rate_map[i].speed != 0; i++) {
367 sr = &rate_map[i];
368 threshold = sr->speed + ((rate_map[i + 1].speed != 0) ?
369 ((rate_map[i + 1].speed - sr->speed) >> 1) : 0);
370 if (speed < threshold)
371 break;
372 }
373 }
374
375 sc->sr = sr;
376
377 ssi_configure_clock(sc);
378
379 return (sr->speed);
380 }
381
382 static void
383 ssi_configure_clock(struct sc_info *sc)
384 {
385 struct ssi_rate *sr;
386
387 sr = sc->sr;
388
389 pll4_configure_output(sr->mfi, sr->mfn, sr->mfd);
390
391 /* Configure other dividers here, if any */
392 }
393
394 static uint32_t
395 ssichan_setblocksize(kobj_t obj, void *data, uint32_t blocksize)
396 {
397 struct sc_chinfo *ch = data;
398 struct sc_pcminfo *scp = ch->parent;
399 struct sc_info *sc = scp->sc;
400
401 sndbuf_resize(ch->buffer, sc->dma_size / blocksize, blocksize);
402
403 setup_dma(scp);
404
405 return (sndbuf_getblksz(ch->buffer));
406 }
407
408 uint32_t
409 ssi_dma_intr(void *arg, int chn)
410 {
411 struct sc_pcminfo *scp;
412 struct sdma_conf *conf;
413 struct sc_chinfo *ch;
414 struct sc_info *sc;
415 int bufsize;
416
417 scp = arg;
418 ch = &scp->chan[0];
419 sc = scp->sc;
420 conf = sc->conf;
421
422 bufsize = sndbuf_getsize(ch->buffer);
423
424 sc->pos += conf->period;
425 if (sc->pos >= bufsize)
426 sc->pos -= bufsize;
427
428 if (ch->run)
429 chn_intr(ch->channel);
430
431 return (0);
432 }
433
434 static int
435 find_sdma_controller(struct sc_info *sc)
436 {
437 struct sdma_softc *sdma_sc;
438 phandle_t node;
439 device_t sdma_dev;
440 pcell_t dts_value[DMAS_TOTAL];
441 int len;
442
443 if ((node = ofw_bus_get_node(sc->dev)) == -1)
444 return (ENXIO);
445
446 if ((len = OF_getproplen(node, "dmas")) <= 0)
447 return (ENXIO);
448
449 if (len != sizeof(dts_value)) {
450 device_printf(sc->dev,
451 "\"dmas\" property length is invalid: %d (expected %d)",
452 len, sizeof(dts_value));
453 return (ENXIO);
454 }
455
456 OF_getencprop(node, "dmas", dts_value, sizeof(dts_value));
457
458 sc->sdma_ev_rx = dts_value[1];
459 sc->sdma_ev_tx = dts_value[5];
460
461 sdma_sc = NULL;
462
463 sdma_dev = devclass_get_device(devclass_find("sdma"), 0);
464 if (sdma_dev)
465 sdma_sc = device_get_softc(sdma_dev);
466
467 if (sdma_sc == NULL) {
468 device_printf(sc->dev, "No sDMA found. Can't operate\n");
469 return (ENXIO);
470 }
471
472 sc->sdma_sc = sdma_sc;
473
474 return (0);
475 };
476
477 static int
478 setup_dma(struct sc_pcminfo *scp)
479 {
480 struct sdma_conf *conf;
481 struct sc_chinfo *ch;
482 struct sc_info *sc;
483 int fmt;
484
485 ch = &scp->chan[0];
486 sc = scp->sc;
487 conf = sc->conf;
488
489 conf->ih = ssi_dma_intr;
490 conf->ih_user = scp;
491 conf->saddr = sc->buf_base_phys;
492 conf->daddr = rman_get_start(sc->res[0]) + SSI_STX0;
493 conf->event = sc->sdma_ev_tx; /* SDMA TX event */
494 conf->period = sndbuf_getblksz(ch->buffer);
495 conf->num_bd = sndbuf_getblkcnt(ch->buffer);
496
497 /*
498 * Word Length
499 * Can be 32, 24, 16 or 8 for sDMA.
500 *
501 * SSI supports 24 at max.
502 */
503
504 fmt = sndbuf_getfmt(ch->buffer);
505
506 if (fmt & AFMT_16BIT) {
507 conf->word_length = 16;
508 conf->command = CMD_2BYTES;
509 } else if (fmt & AFMT_24BIT) {
510 conf->word_length = 24;
511 conf->command = CMD_3BYTES;
512 } else {
513 device_printf(sc->dev, "Unknown format\n");
514 return (-1);
515 }
516
517 return (0);
518 }
519
520 static int
521 ssi_start(struct sc_pcminfo *scp)
522 {
523 struct sc_info *sc;
524 int reg;
525
526 sc = scp->sc;
527
528 if (sdma_configure(sc->sdma_channel, sc->conf) != 0) {
529 device_printf(sc->dev, "Can't configure sDMA\n");
530 return (-1);
531 }
532
533 /* Enable DMA interrupt */
534 reg = (SIER_TDMAE);
535 WRITE4(sc, SSI_SIER, reg);
536
537 sdma_start(sc->sdma_channel);
538
539 return (0);
540 }
541
542 static int
543 ssi_stop(struct sc_pcminfo *scp)
544 {
545 struct sc_info *sc;
546 int reg;
547
548 sc = scp->sc;
549
550 reg = READ4(sc, SSI_SIER);
551 reg &= ~(SIER_TDMAE);
552 WRITE4(sc, SSI_SIER, reg);
553
554 sdma_stop(sc->sdma_channel);
555
556 bzero(sc->buf_base, sc->dma_size);
557
558 return (0);
559 }
560
561 static int
562 ssichan_trigger(kobj_t obj, void *data, int go)
563 {
564 struct sc_pcminfo *scp;
565 struct sc_chinfo *ch;
566 struct sc_info *sc;
567
568 ch = data;
569 scp = ch->parent;
570 sc = scp->sc;
571
572 snd_mtxlock(sc->lock);
573
574 switch (go) {
575 case PCMTRIG_START:
576 #if 0
577 device_printf(scp->dev, "trigger start\n");
578 #endif
579 ch->run = 1;
580
581 ssi_start(scp);
582
583 break;
584
585 case PCMTRIG_STOP:
586 case PCMTRIG_ABORT:
587 #if 0
588 device_printf(scp->dev, "trigger stop or abort\n");
589 #endif
590 ch->run = 0;
591
592 ssi_stop(scp);
593
594 break;
595 }
596
597 snd_mtxunlock(sc->lock);
598
599 return (0);
600 }
601
602 static uint32_t
603 ssichan_getptr(kobj_t obj, void *data)
604 {
605 struct sc_pcminfo *scp;
606 struct sc_chinfo *ch;
607 struct sc_info *sc;
608
609 ch = data;
610 scp = ch->parent;
611 sc = scp->sc;
612
613 return (sc->pos);
614 }
615
616 static uint32_t ssi_pfmt[] = {
617 SND_FORMAT(AFMT_S24_LE, 2, 0),
618 0
619 };
620
621 static struct pcmchan_caps ssi_pcaps = {44100, 192000, ssi_pfmt, 0};
622
623 static struct pcmchan_caps *
624 ssichan_getcaps(kobj_t obj, void *data)
625 {
626
627 return (&ssi_pcaps);
628 }
629
630 static kobj_method_t ssichan_methods[] = {
631 KOBJMETHOD(channel_init, ssichan_init),
632 KOBJMETHOD(channel_free, ssichan_free),
633 KOBJMETHOD(channel_setformat, ssichan_setformat),
634 KOBJMETHOD(channel_setspeed, ssichan_setspeed),
635 KOBJMETHOD(channel_setblocksize, ssichan_setblocksize),
636 KOBJMETHOD(channel_trigger, ssichan_trigger),
637 KOBJMETHOD(channel_getptr, ssichan_getptr),
638 KOBJMETHOD(channel_getcaps, ssichan_getcaps),
639 KOBJMETHOD_END
640 };
641 CHANNEL_DECLARE(ssichan);
642
643 static int
644 ssi_probe(device_t dev)
645 {
646
647 if (!ofw_bus_status_okay(dev))
648 return (ENXIO);
649
650 if (!ofw_bus_is_compatible(dev, "fsl,imx6q-ssi"))
651 return (ENXIO);
652
653 device_set_desc(dev, "i.MX6 Synchronous Serial Interface (SSI)");
654 return (BUS_PROBE_DEFAULT);
655 }
656
657 static void
658 ssi_intr(void *arg)
659 {
660 #if 0
661 struct sc_pcminfo *scp;
662 struct sc_info *sc;
663
664 scp = arg;
665 sc = scp->sc;
666 #endif
667
668 /* We don't use SSI interrupt */
669 #if 0
670 device_printf(scp->sc->dev, "SSI Intr 0x%08x\n",
671 READ4(sc, SSI_SISR));
672 #endif
673 }
674
675 static void
676 setup_ssi(struct sc_info *sc)
677 {
678 int reg;
679
680 reg = READ4(sc, SSI_STCCR);
681 reg &= ~(WL3_WL0_M << WL3_WL0_S);
682 reg |= (0xb << WL3_WL0_S); /* 24 bit */
683 reg &= ~(DC4_DC0_M << DC4_DC0_S);
684 reg |= (1 << DC4_DC0_S); /* 2 words per frame */
685 reg &= ~(STCCR_DIV2); /* Divide by 1 */
686 reg &= ~(STCCR_PSR); /* Divide by 1 */
687 reg &= ~(PM7_PM0_M << PM7_PM0_S);
688 reg |= (1 << PM7_PM0_S); /* Divide by 2 */
689 WRITE4(sc, SSI_STCCR, reg);
690
691 reg = READ4(sc, SSI_SFCSR);
692 reg &= ~(SFCSR_TFWM0_M << SFCSR_TFWM0_S);
693 reg |= (8 << SFCSR_TFWM0_S); /* empty slots */
694 WRITE4(sc, SSI_SFCSR, reg);
695
696 reg = READ4(sc, SSI_STCR);
697 reg |= (STCR_TFEN0);
698 reg &= ~(STCR_TFEN1);
699 reg &= ~(STCR_TSHFD); /* MSB */
700 reg |= (STCR_TXBIT0);
701 reg |= (STCR_TXDIR | STCR_TFDIR);
702 reg |= (STCR_TSCKP); /* falling edge */
703 reg |= (STCR_TFSI);
704 reg &= ~(STCR_TFSI); /* active high frame sync */
705 reg &= ~(STCR_TFSL);
706 reg |= STCR_TEFS;
707 WRITE4(sc, SSI_STCR, reg);
708
709 reg = READ4(sc, SSI_SCR);
710 reg &= ~(SCR_I2S_MODE_M << SCR_I2S_MODE_S); /* Not master */
711 reg |= (SCR_SSIEN | SCR_TE);
712 reg |= (SCR_NET);
713 reg |= (SCR_SYN);
714 WRITE4(sc, SSI_SCR, reg);
715 }
716
717 static void
718 ssi_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
719 {
720 bus_addr_t *addr;
721
722 if (err)
723 return;
724
725 addr = (bus_addr_t*)arg;
726 *addr = segs[0].ds_addr;
727 }
728
729 static int
730 ssi_attach(device_t dev)
731 {
732 char status[SND_STATUSLEN];
733 struct sc_pcminfo *scp;
734 struct sc_info *sc;
735 int err;
736
737 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
738 sc->dev = dev;
739 sc->sr = &rate_map[0];
740 sc->pos = 0;
741 sc->conf = malloc(sizeof(struct sdma_conf), M_DEVBUF, M_WAITOK | M_ZERO);
742
743 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "ssi softc");
744 if (sc->lock == NULL) {
745 device_printf(dev, "Can't create mtx\n");
746 return (ENXIO);
747 }
748
749 if (bus_alloc_resources(dev, ssi_spec, sc->res)) {
750 device_printf(dev, "could not allocate resources\n");
751 return (ENXIO);
752 }
753
754 /* Memory interface */
755 sc->bst = rman_get_bustag(sc->res[0]);
756 sc->bsh = rman_get_bushandle(sc->res[0]);
757
758 /* SDMA */
759 if (find_sdma_controller(sc)) {
760 device_printf(dev, "could not find active SDMA\n");
761 return (ENXIO);
762 }
763
764 /* Setup PCM */
765 scp = malloc(sizeof(struct sc_pcminfo), M_DEVBUF, M_NOWAIT | M_ZERO);
766 scp->sc = sc;
767 scp->dev = dev;
768
769 /*
770 * Maximum possible DMA buffer.
771 * Will be used partially to match 24 bit word.
772 */
773 sc->dma_size = 131072;
774
775 /*
776 * Must use dma_size boundary as modulo feature required.
777 * Modulo feature allows setup circular buffer.
778 */
779
780 err = bus_dma_tag_create(
781 bus_get_dma_tag(sc->dev),
782 4, sc->dma_size, /* alignment, boundary */
783 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
784 BUS_SPACE_MAXADDR, /* highaddr */
785 NULL, NULL, /* filter, filterarg */
786 sc->dma_size, 1, /* maxsize, nsegments */
787 sc->dma_size, 0, /* maxsegsize, flags */
788 NULL, NULL, /* lockfunc, lockarg */
789 &sc->dma_tag);
790
791 err = bus_dmamem_alloc(sc->dma_tag, (void **)&sc->buf_base,
792 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->dma_map);
793 if (err) {
794 device_printf(dev, "cannot allocate framebuffer\n");
795 return (ENXIO);
796 }
797
798 err = bus_dmamap_load(sc->dma_tag, sc->dma_map, sc->buf_base,
799 sc->dma_size, ssi_dmamap_cb, &sc->buf_base_phys, BUS_DMA_NOWAIT);
800 if (err) {
801 device_printf(dev, "cannot load DMA map\n");
802 return (ENXIO);
803 }
804
805 bzero(sc->buf_base, sc->dma_size);
806
807 /* Setup interrupt handler */
808 err = bus_setup_intr(dev, sc->res[1], INTR_MPSAFE | INTR_TYPE_AV,
809 NULL, ssi_intr, scp, &sc->ih);
810 if (err) {
811 device_printf(dev, "Unable to alloc interrupt resource.\n");
812 return (ENXIO);
813 }
814
815 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE);
816
817 err = pcm_register(dev, scp, 1, 0);
818 if (err) {
819 device_printf(dev, "Can't register pcm.\n");
820 return (ENXIO);
821 }
822
823 scp->chnum = 0;
824 pcm_addchan(dev, PCMDIR_PLAY, &ssichan_class, scp);
825 scp->chnum++;
826
827 snprintf(status, SND_STATUSLEN, "at simplebus");
828 pcm_setstatus(dev, status);
829
830 mixer_init(dev, &ssimixer_class, scp);
831 setup_ssi(sc);
832
833 imx_ccm_ssi_configure(dev);
834
835 sc->sdma_channel = sdma_alloc();
836 if (sc->sdma_channel < 0) {
837 device_printf(sc->dev, "Can't get sDMA channel\n");
838 return (1);
839 }
840
841 return (0);
842 }
843
844 static device_method_t ssi_pcm_methods[] = {
845 DEVMETHOD(device_probe, ssi_probe),
846 DEVMETHOD(device_attach, ssi_attach),
847 { 0, 0 }
848 };
849
850 static driver_t ssi_pcm_driver = {
851 "pcm",
852 ssi_pcm_methods,
853 PCM_SOFTC_SIZE,
854 };
855
856 DRIVER_MODULE(ssi, simplebus, ssi_pcm_driver, 0, 0);
857 MODULE_DEPEND(ssi, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
858 MODULE_DEPEND(ssi, sdma, 0, 0, 0);
859 MODULE_VERSION(ssi, 1);
Cache object: 1980ecadd1195d9a2bc1f0c0591240da
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