1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2012, 2013 The FreeBSD Foundation
5 *
6 * This software was developed by Oleksandr Rybalko under sponsorship
7 * from the FreeBSD Foundation.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
33
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/bus.h>
37 #include <sys/kernel.h>
38 #include <sys/module.h>
39 #include <sys/rman.h>
40 #include <sys/timeet.h>
41 #include <sys/timetc.h>
42 #include <machine/bus.h>
43 #include <machine/intr.h>
44 #include <machine/machdep.h> /* For arm_set_delay */
45
46 #include <dev/ofw/openfirm.h>
47 #include <dev/ofw/ofw_bus.h>
48 #include <dev/ofw/ofw_bus_subr.h>
49
50 #include <arm/freescale/imx/imx_ccmvar.h>
51 #include <arm/freescale/imx/imx_gptreg.h>
52
53 #define WRITE4(_sc, _r, _v) \
54 bus_space_write_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r), (_v))
55 #define READ4(_sc, _r) \
56 bus_space_read_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r))
57 #define SET4(_sc, _r, _m) \
58 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m))
59 #define CLEAR4(_sc, _r, _m) \
60 WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m))
61
62 static u_int imx_gpt_get_timecount(struct timecounter *);
63 static int imx_gpt_timer_start(struct eventtimer *, sbintime_t,
64 sbintime_t);
65 static int imx_gpt_timer_stop(struct eventtimer *);
66
67 static void imx_gpt_do_delay(int, void *);
68
69 static int imx_gpt_intr(void *);
70 static int imx_gpt_probe(device_t);
71 static int imx_gpt_attach(device_t);
72
73 static struct timecounter imx_gpt_timecounter = {
74 .tc_name = "iMXGPT",
75 .tc_get_timecount = imx_gpt_get_timecount,
76 .tc_counter_mask = ~0u,
77 .tc_frequency = 0,
78 .tc_quality = 1000,
79 };
80
81 struct imx_gpt_softc {
82 device_t sc_dev;
83 struct resource * res[2];
84 bus_space_tag_t sc_iot;
85 bus_space_handle_t sc_ioh;
86 void * sc_ih; /* interrupt handler */
87 uint32_t sc_period;
88 uint32_t sc_clksrc;
89 uint32_t clkfreq;
90 uint32_t ir_reg;
91 struct eventtimer et;
92 };
93
94 /* Try to divide down an available fast clock to this frequency. */
95 #define TARGET_FREQUENCY 1000000000
96
97 static struct resource_spec imx_gpt_spec[] = {
98 { SYS_RES_MEMORY, 0, RF_ACTIVE },
99 { SYS_RES_IRQ, 0, RF_ACTIVE },
100 { -1, 0 }
101 };
102
103 static struct ofw_compat_data compat_data[] = {
104 {"fsl,imx6dl-gpt", 1},
105 {"fsl,imx6q-gpt", 1},
106 {"fsl,imx6ul-gpt", 1},
107 {"fsl,imx53-gpt", 1},
108 {"fsl,imx51-gpt", 1},
109 {"fsl,imx31-gpt", 1},
110 {"fsl,imx27-gpt", 1},
111 {"fsl,imx25-gpt", 1},
112 {NULL, 0}
113 };
114
115 static int
116 imx_gpt_probe(device_t dev)
117 {
118
119 if (!ofw_bus_status_okay(dev))
120 return (ENXIO);
121
122 /*
123 * We only support a single unit, because the only thing this driver
124 * does with the complex timer hardware is supply the system
125 * timecounter and eventtimer. There is nothing useful we can do with
126 * the additional device instances that exist in some chips.
127 */
128 if (device_get_unit(dev) > 0)
129 return (ENXIO);
130
131 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) {
132 device_set_desc(dev, "Freescale i.MX GPT timer");
133 return (BUS_PROBE_DEFAULT);
134 }
135
136 return (ENXIO);
137 }
138
139 static int
140 imx_gpt_attach(device_t dev)
141 {
142 struct imx_gpt_softc *sc;
143 int ctlreg, err;
144 uint32_t basefreq, prescale, setup_ticks, t1, t2;
145
146 sc = device_get_softc(dev);
147
148 if (bus_alloc_resources(dev, imx_gpt_spec, sc->res)) {
149 device_printf(dev, "could not allocate resources\n");
150 return (ENXIO);
151 }
152
153 sc->sc_dev = dev;
154 sc->sc_iot = rman_get_bustag(sc->res[0]);
155 sc->sc_ioh = rman_get_bushandle(sc->res[0]);
156
157 /*
158 * For now, just automatically choose a good clock for the hardware
159 * we're running on. Eventually we could allow selection from the fdt;
160 * the code in this driver will cope with any clock frequency.
161 */
162 sc->sc_clksrc = GPT_CR_CLKSRC_IPG;
163
164 ctlreg = 0;
165
166 switch (sc->sc_clksrc) {
167 case GPT_CR_CLKSRC_32K:
168 basefreq = 32768;
169 break;
170 case GPT_CR_CLKSRC_IPG:
171 basefreq = imx_ccm_ipg_hz();
172 break;
173 case GPT_CR_CLKSRC_IPG_HIGH:
174 basefreq = imx_ccm_ipg_hz() * 2;
175 break;
176 case GPT_CR_CLKSRC_24M:
177 ctlreg |= GPT_CR_24MEN;
178 basefreq = 24000000;
179 break;
180 case GPT_CR_CLKSRC_NONE:/* Can't run without a clock. */
181 case GPT_CR_CLKSRC_EXT: /* No way to get the freq of an ext clock. */
182 default:
183 device_printf(dev, "Unsupported clock source '%d'\n",
184 sc->sc_clksrc);
185 return (EINVAL);
186 }
187
188 /*
189 * The following setup sequence is from the I.MX6 reference manual,
190 * "Selecting the clock source". First, disable the clock and
191 * interrupts. This also clears input and output mode bits and in
192 * general completes several of the early steps in the procedure.
193 */
194 WRITE4(sc, IMX_GPT_CR, 0);
195 WRITE4(sc, IMX_GPT_IR, 0);
196
197 /* Choose the clock and the power-saving behaviors. */
198 ctlreg |=
199 sc->sc_clksrc | /* Use selected clock */
200 GPT_CR_FRR | /* Just count (FreeRunner mode) */
201 GPT_CR_STOPEN | /* Run in STOP mode */
202 GPT_CR_DOZEEN | /* Run in DOZE mode */
203 GPT_CR_WAITEN | /* Run in WAIT mode */
204 GPT_CR_DBGEN; /* Run in DEBUG mode */
205 WRITE4(sc, IMX_GPT_CR, ctlreg);
206
207 /*
208 * The datasheet says to do the software reset after choosing the clock
209 * source. It says nothing about needing to wait for the reset to
210 * complete, but the register description does document the fact that
211 * the reset isn't complete until the SWR bit reads 0, so let's be safe.
212 * The reset also clears all registers except for a few of the bits in
213 * CR, but we'll rewrite all the CR bits when we start the counter.
214 */
215 WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_SWR);
216 while (READ4(sc, IMX_GPT_CR) & GPT_CR_SWR)
217 continue;
218
219 /* Set a prescaler value that gets us near the target frequency. */
220 if (basefreq < TARGET_FREQUENCY) {
221 prescale = 0;
222 sc->clkfreq = basefreq;
223 } else {
224 prescale = basefreq / TARGET_FREQUENCY;
225 sc->clkfreq = basefreq / prescale;
226 prescale -= 1; /* 1..n range is 0..n-1 in hardware. */
227 }
228 WRITE4(sc, IMX_GPT_PR, prescale);
229
230 /* Clear the status register. */
231 WRITE4(sc, IMX_GPT_SR, GPT_IR_ALL);
232
233 /* Start the counter. */
234 WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_EN);
235
236 if (bootverbose)
237 device_printf(dev, "Running on %dKHz clock, base freq %uHz CR=0x%08x, PR=0x%08x\n",
238 sc->clkfreq / 1000, basefreq, READ4(sc, IMX_GPT_CR), READ4(sc, IMX_GPT_PR));
239
240 /* Setup the timer interrupt. */
241 err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_CLK, imx_gpt_intr,
242 NULL, sc, &sc->sc_ih);
243 if (err != 0) {
244 bus_release_resources(dev, imx_gpt_spec, sc->res);
245 device_printf(dev, "Unable to setup the clock irq handler, "
246 "err = %d\n", err);
247 return (ENXIO);
248 }
249
250 /*
251 * Measure how many clock ticks it takes to setup a one-shot event (it's
252 * longer than you might think, due to wait states in accessing gpt
253 * registers). Scale up the result by a factor of 1.5 to be safe,
254 * and use that to set the minimum eventtimer period we can schedule. In
255 * the real world, the value works out to about 750ns on imx5 hardware.
256 */
257 t1 = READ4(sc, IMX_GPT_CNT);
258 WRITE4(sc, IMX_GPT_OCR3, 0);
259 t2 = READ4(sc, IMX_GPT_CNT);
260 setup_ticks = ((t2 - t1 + 1) * 3) / 2;
261
262 /* Register as an eventtimer. */
263 sc->et.et_name = "iMXGPT";
264 sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERIODIC;
265 sc->et.et_quality = 800;
266 sc->et.et_frequency = sc->clkfreq;
267 sc->et.et_min_period = ((uint64_t)setup_ticks << 32) / sc->clkfreq;
268 sc->et.et_max_period = ((uint64_t)0xfffffffe << 32) / sc->clkfreq;
269 sc->et.et_start = imx_gpt_timer_start;
270 sc->et.et_stop = imx_gpt_timer_stop;
271 sc->et.et_priv = sc;
272 et_register(&sc->et);
273
274 /* Register as a timecounter. */
275 imx_gpt_timecounter.tc_frequency = sc->clkfreq;
276 imx_gpt_timecounter.tc_priv = sc;
277 tc_init(&imx_gpt_timecounter);
278
279 /* If this is the first unit, store the softc for use in DELAY. */
280 if (device_get_unit(dev) == 0) {
281 arm_set_delay(imx_gpt_do_delay, sc);
282 }
283
284 return (0);
285 }
286
287 static int
288 imx_gpt_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
289 {
290 struct imx_gpt_softc *sc;
291 uint32_t ticks;
292
293 sc = (struct imx_gpt_softc *)et->et_priv;
294
295 if (period != 0) {
296 sc->sc_period = ((uint32_t)et->et_frequency * period) >> 32;
297 /* Set expected value */
298 WRITE4(sc, IMX_GPT_OCR2, READ4(sc, IMX_GPT_CNT) + sc->sc_period);
299 /* Enable compare register 2 Interrupt */
300 sc->ir_reg |= GPT_IR_OF2;
301 WRITE4(sc, IMX_GPT_IR, sc->ir_reg);
302 return (0);
303 } else if (first != 0) {
304 /* Enable compare register 3 interrupt if not already on. */
305 if ((sc->ir_reg & GPT_IR_OF3) == 0) {
306 sc->ir_reg |= GPT_IR_OF3;
307 WRITE4(sc, IMX_GPT_IR, sc->ir_reg);
308 }
309 ticks = ((uint32_t)et->et_frequency * first) >> 32;
310 /* Do not disturb, otherwise event will be lost */
311 spinlock_enter();
312 /* Set expected value */
313 WRITE4(sc, IMX_GPT_OCR3, READ4(sc, IMX_GPT_CNT) + ticks);
314 /* Now everybody can relax */
315 spinlock_exit();
316 return (0);
317 }
318
319 return (EINVAL);
320 }
321
322 static int
323 imx_gpt_timer_stop(struct eventtimer *et)
324 {
325 struct imx_gpt_softc *sc;
326
327 sc = (struct imx_gpt_softc *)et->et_priv;
328
329 /* Disable interrupts and clear any pending status. */
330 sc->ir_reg &= ~(GPT_IR_OF2 | GPT_IR_OF3);
331 WRITE4(sc, IMX_GPT_IR, sc->ir_reg);
332 WRITE4(sc, IMX_GPT_SR, GPT_IR_OF2 | GPT_IR_OF3);
333 sc->sc_period = 0;
334
335 return (0);
336 }
337
338 static int
339 imx_gpt_intr(void *arg)
340 {
341 struct imx_gpt_softc *sc;
342 uint32_t status;
343
344 sc = (struct imx_gpt_softc *)arg;
345
346 status = READ4(sc, IMX_GPT_SR);
347
348 /*
349 * Clear interrupt status before invoking event callbacks. The callback
350 * often sets up a new one-shot timer event and if the interval is short
351 * enough it can fire before we get out of this function. If we cleared
352 * at the bottom we'd miss the interrupt and hang until the clock wraps.
353 */
354 WRITE4(sc, IMX_GPT_SR, status);
355
356 /* Handle one-shot timer events. */
357 if (status & GPT_IR_OF3) {
358 if (sc->et.et_active) {
359 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
360 }
361 }
362
363 /* Handle periodic timer events. */
364 if (status & GPT_IR_OF2) {
365 if (sc->et.et_active)
366 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
367 if (sc->sc_period != 0)
368 WRITE4(sc, IMX_GPT_OCR2, READ4(sc, IMX_GPT_CNT) +
369 sc->sc_period);
370 }
371
372 return (FILTER_HANDLED);
373 }
374
375 static u_int
376 imx_gpt_get_timecount(struct timecounter *tc)
377 {
378 struct imx_gpt_softc *sc;
379
380 sc = tc->tc_priv;
381 return (READ4(sc, IMX_GPT_CNT));
382 }
383
384 static device_method_t imx_gpt_methods[] = {
385 DEVMETHOD(device_probe, imx_gpt_probe),
386 DEVMETHOD(device_attach, imx_gpt_attach),
387
388 DEVMETHOD_END
389 };
390
391 static driver_t imx_gpt_driver = {
392 "imx_gpt",
393 imx_gpt_methods,
394 sizeof(struct imx_gpt_softc),
395 };
396
397 EARLY_DRIVER_MODULE(imx_gpt, simplebus, imx_gpt_driver, 0, 0, BUS_PASS_TIMER);
398
399 static void
400 imx_gpt_do_delay(int usec, void *arg)
401 {
402 struct imx_gpt_softc *sc = arg;
403 uint64_t curcnt, endcnt, startcnt, ticks;
404
405 /*
406 * Calculate the tick count with 64-bit values so that it works for any
407 * clock frequency. Loop until the hardware count reaches start+ticks.
408 * If the 32-bit hardware count rolls over while we're looping, just
409 * manually do a carry into the high bits after each read; don't worry
410 * that doing this on each loop iteration is inefficient -- we're trying
411 * to waste time here.
412 */
413 ticks = 1 + ((uint64_t)usec * sc->clkfreq) / 1000000;
414 curcnt = startcnt = READ4(sc, IMX_GPT_CNT);
415 endcnt = startcnt + ticks;
416 while (curcnt < endcnt) {
417 curcnt = READ4(sc, IMX_GPT_CNT);
418 if (curcnt < startcnt)
419 curcnt += 1ULL << 32;
420 }
421 }
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