1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include "opt_platform.h"
30
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
33
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/reboot.h>
37 #include <sys/devmap.h>
38
39 #include <vm/vm.h>
40 #include <vm/pmap.h>
41
42 #include <machine/armreg.h>
43 #include <machine/bus.h>
44 #include <machine/cpu.h>
45 #include <machine/machdep.h>
46
47 #include <arm/freescale/imx/imx_machdep.h>
48 #include <arm/freescale/imx/imx_wdogreg.h>
49
50 SYSCTL_NODE(_hw, OID_AUTO, imx, CTLFLAG_RW | CTLFLAG_MPSAFE, NULL,
51 "i.MX container");
52
53 static int last_reset_status;
54 SYSCTL_UINT(_hw_imx, OID_AUTO, last_reset_status, CTLFLAG_RD,
55 &last_reset_status, 0, "Last reset status register");
56
57 SYSCTL_STRING(_hw_imx, OID_AUTO, last_reset_reason, CTLFLAG_RD,
58 "unknown", 0, "Last reset reason");
59
60 /*
61 * This code which manipulates the watchdog hardware is here to implement
62 * cpu_reset() because the watchdog is the only way for software to reset the
63 * chip. Why here and not in imx_wdog.c? Because there's no requirement that
64 * the watchdog driver be compiled in, but it's nice to be able to reboot even
65 * if it's not.
66 */
67 void
68 imx_wdog_cpu_reset(vm_offset_t wdcr_physaddr)
69 {
70 volatile uint16_t cr, *pcr;
71
72 if ((pcr = devmap_ptov(wdcr_physaddr, sizeof(*pcr))) == NULL) {
73 printf("imx_wdog_cpu_reset(): "
74 "cannot find control register... locking up now.");
75 for (;;)
76 cpu_spinwait();
77 }
78 cr = *pcr;
79
80 /*
81 * If the watchdog hardware has been set up to trigger an external reset
82 * signal on watchdog timeout, then we do software-requested rebooting
83 * the same way, by asserting the external reset signal.
84 *
85 * Asserting external reset is supposed to result in some external
86 * component asserting the POR pin on the SoC, possibly after adjusting
87 * and stabilizing system voltages, or taking other system-wide reset
88 * actions. Just in case there is some kind of misconfiguration, we
89 * hang out and do nothing for a full second, then continue on into
90 * the code to assert a software reset as well.
91 */
92 if (cr & WDOG_CR_WDT) {
93 cr &= ~WDOG_CR_WDA; /* Assert active-low ext reset bit. */
94 *pcr = cr;
95 DELAY(1000000);
96 printf("imx_wdog_cpu_reset(): "
97 "External reset failed, trying internal cpu-reset\n");
98 DELAY(10000); /* Time for printf to appear */
99 }
100
101 /*
102 * Imx6 erratum ERR004346 says the SRS bit has to be cleared twice
103 * within the same cycle of the 32khz clock to reliably trigger the
104 * reset. Writing it 3 times in a row ensures at least 2 of the writes
105 * happen in the same 32k clock cycle.
106 */
107 cr &= ~WDOG_CR_SRS; /* Assert active-low software reset bit. */
108 *pcr = cr;
109 *pcr = cr;
110 *pcr = cr;
111
112 /* Reset happens on the next tick of the 32khz clock, wait for it. */
113 for (;;)
114 cpu_spinwait();
115 }
116
117 void
118 imx_wdog_init_last_reset(vm_offset_t wdsr_phys)
119 {
120 volatile uint16_t * psr;
121
122 if ((psr = devmap_ptov(wdsr_phys, sizeof(*psr))) == NULL)
123 return;
124 last_reset_status = *psr;
125 if (last_reset_status & WDOG_RSR_SFTW) {
126 sysctl___hw_imx_last_reset_reason.oid_arg1 = "SoftwareReset";
127 } else if (last_reset_status & WDOG_RSR_TOUT) {
128 sysctl___hw_imx_last_reset_reason.oid_arg1 = "WatchdogTimeout";
129 } else if (last_reset_status & WDOG_RSR_POR) {
130 sysctl___hw_imx_last_reset_reason.oid_arg1 = "PowerOnReset";
131 }
132 }
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