1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2012, 2013 The FreeBSD Foundation
5 *
6 * This software was developed by Oleksandr Rybalko under sponsorship
7 * from the FreeBSD Foundation.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * $FreeBSD$
31 */
32
33 #define WDOG_CLK_FREQ 32768
34
35 #define WDOG_CR_REG 0x00 /* Control Register */
36 #define WDOG_CR_WT_MASK 0xff00 /* Count; 0.5 sec units */
37 #define WDOG_CR_WT_SHIFT 8
38 #define WDOG_CR_WDW (1u << 7) /* Suspend when in WAIT mode */
39 #define WDOG_CR_WDA (1u << 5) /* Don't assert ext reset */
40 #define WDOG_CR_SRS (1u << 4) /* Don't assert soft reset */
41 #define WDOG_CR_WDT (1u << 3) /* Assert ext reset on timeout */
42 #define WDOG_CR_WDE (1u << 2) /* Watchdog Enable */
43 #define WDOG_CR_WDBG (1u << 1) /* Suspend when DBG mode */
44 #define WDOG_CR_WDZST (1u << 0) /* Suspend when LP mode */
45
46 #define WDOG_SR_REG 0x02 /* Service Register */
47 #define WDOG_SR_STEP1 0x5555
48 #define WDOG_SR_STEP2 0xaaaa
49
50 #define WDOG_RSR_REG 0x04 /* Reset Status Register */
51 #define WDOG_RSR_POR (1u << 4) /* Due to Power-On Reset */
52 #define WDOG_RSR_TOUT (1u << 1) /* Due WDog timeout reset */
53 #define WDOG_RSR_SFTW (1u << 0) /* Due Soft reset */
54
55 #define WDOG_ICR_REG 0x06 /* Interrupt Control Register */
56 #define WDOG_ICR_WIE (1u << 15) /* Enable Interrupt */
57 #define WDOG_ICR_WTIS (1u << 14) /* Interrupt has occurred */
58 #define WDOG_ICR_WTCT_MASK 0x00ff /* Interrupt lead time in 0.5s */
59 #define WDOG_ICR_WTCT_SHIFT 0 /* units before reset occurs */
60
61 #define WDOG_MCR_REG 0x08 /* Miscellaneous Control Register */
62 #define WDOG_MCR_PDE (1u << 0) /* Power-down enable */
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