The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/freescale/imx/tzic.c

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    1 /*-
    2  * Copyright (c) 2012, 2013 The FreeBSD Foundation
    3  * All rights reserved.
    4  *
    5  * This software was developed by Oleksandr Rybalko under sponsorship
    6  * from the FreeBSD Foundation.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1.   Redistributions of source code must retain the above copyright
   12  *      notice, this list of conditions and the following disclaimer.
   13  * 2.   Redistributions in binary form must reproduce the above copyright
   14  *      notice, this list of conditions and the following disclaimer in the
   15  *      documentation and/or other materials provided with the distribution.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   20  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   27  * SUCH DAMAGE.
   28  */
   29 
   30 #include <sys/cdefs.h>
   31 __FBSDID("$FreeBSD: releng/11.0/sys/arm/freescale/imx/tzic.c 261513 2014-02-05 14:44:22Z nwhitehorn $");
   32 
   33 #include <sys/param.h>
   34 #include <sys/systm.h>
   35 #include <sys/bus.h>
   36 #include <sys/kernel.h>
   37 #include <sys/ktr.h>
   38 #include <sys/module.h>
   39 #include <sys/rman.h>
   40 #include <sys/pcpu.h>
   41 #include <sys/proc.h>
   42 #include <sys/cpuset.h>
   43 #include <sys/lock.h>
   44 #include <sys/mutex.h>
   45 #include <machine/bus.h>
   46 #include <machine/intr.h>
   47 
   48 #include <dev/fdt/fdt_common.h>
   49 #include <dev/ofw/openfirm.h>
   50 #include <dev/ofw/ofw_bus.h>
   51 #include <dev/ofw/ofw_bus_subr.h>
   52 
   53 #include <arm/freescale/imx/imx51_tzicreg.h>
   54 
   55 struct tzic_softc {
   56         struct resource *       tzic_res[3];
   57         bus_space_tag_t         tzic_bst;
   58         bus_space_handle_t      tzic_bsh;
   59         uint8_t                 ver;
   60 };
   61 
   62 static struct resource_spec tzic_spec[] = {
   63         { SYS_RES_MEMORY,       0,      RF_ACTIVE },
   64         { -1, 0 }
   65 };
   66 
   67 static struct tzic_softc *tzic_sc = NULL;
   68 
   69 #define tzic_read_4(reg)                \
   70     bus_space_read_4(tzic_sc->tzic_bst, tzic_sc->tzic_bsh, reg)
   71 #define tzic_write_4(reg, val)          \
   72     bus_space_write_4(tzic_sc->tzic_bst, tzic_sc->tzic_bsh, reg, val)
   73 
   74 static void tzic_post_filter(void *);
   75 
   76 static int
   77 tzic_probe(device_t dev)
   78 {
   79 
   80         if (!ofw_bus_status_okay(dev))
   81                 return (ENXIO);
   82 
   83         if (ofw_bus_is_compatible(dev, "fsl,tzic")) {
   84                 device_set_desc(dev, "TrustZone Interrupt Controller");
   85                 return (BUS_PROBE_DEFAULT);
   86         }
   87         return (ENXIO);
   88 }
   89 
   90 static int
   91 tzic_attach(device_t dev)
   92 {
   93         struct          tzic_softc *sc = device_get_softc(dev);
   94         int             i;
   95         uint32_t        reg;
   96 
   97         if (tzic_sc)
   98                 return (ENXIO);
   99 
  100         if (bus_alloc_resources(dev, tzic_spec, sc->tzic_res)) {
  101                 device_printf(dev, "could not allocate resources\n");
  102                 return (ENXIO);
  103         }
  104 
  105         arm_post_filter = tzic_post_filter;
  106 
  107         /* Distributor Interface */
  108         sc->tzic_bst = rman_get_bustag(sc->tzic_res[0]);
  109         sc->tzic_bsh = rman_get_bushandle(sc->tzic_res[0]);
  110 
  111         tzic_sc = sc;
  112 
  113         reg = tzic_read_4(TZIC_INTCNTL);
  114         tzic_write_4(TZIC_INTCNTL, INTCNTL_NSEN_MASK|INTCNTL_NSEN|INTCNTL_EN);
  115         reg = tzic_read_4(TZIC_INTCNTL);
  116         tzic_write_4(TZIC_PRIOMASK, 0x1f);
  117         reg = tzic_read_4(TZIC_PRIOMASK);
  118 
  119         tzic_write_4(TZIC_SYNCCTRL, 0x02);
  120         reg = tzic_read_4(TZIC_SYNCCTRL);
  121 
  122         /* route all interrupts to IRQ.  secure interrupts are for FIQ */
  123         for (i = 0; i < 4; i++)
  124                 tzic_write_4(TZIC_INTSEC(i), 0xffffffff);
  125 
  126         /* disable all interrupts */
  127         for (i = 0; i < 4; i++)
  128                 tzic_write_4(TZIC_ENCLEAR(i), 0xffffffff);
  129 
  130         return (0);
  131 }
  132 
  133 static device_method_t tzic_methods[] = {
  134         DEVMETHOD(device_probe,         tzic_probe),
  135         DEVMETHOD(device_attach,        tzic_attach),
  136         { 0, 0 }
  137 };
  138 
  139 static driver_t tzic_driver = {
  140         "tzic",
  141         tzic_methods,
  142         sizeof(struct tzic_softc),
  143 };
  144 
  145 static devclass_t tzic_devclass;
  146 
  147 /*
  148  * Memory space of controller located outside of device range, so let him to
  149  * attach not only to simplebus, but ofwbus also.
  150  */
  151 EARLY_DRIVER_MODULE(tzic, ofwbus, tzic_driver, tzic_devclass, 0, 0,
  152     BUS_PASS_INTERRUPT);
  153 EARLY_DRIVER_MODULE(tzic, simplebus, tzic_driver, tzic_devclass, 0, 0,
  154     BUS_PASS_INTERRUPT);
  155 
  156 static void
  157 tzic_post_filter(void *arg)
  158 {
  159 
  160 }
  161 
  162 int
  163 arm_get_next_irq(int last_irq)
  164 {
  165         uint32_t pending;
  166         int i, b;
  167 
  168         for (i = 0; i < 4; i++) {
  169                 pending = tzic_read_4(TZIC_PND(i));
  170                 for (b = 0; pending != 0 && b < 32; b++)
  171                         if (pending & (1 << b)) {
  172                                 return (i * 32 + b);
  173                         }
  174         }
  175 
  176         return (-1);
  177 }
  178 
  179 void
  180 arm_mask_irq(uintptr_t nb)
  181 {
  182 
  183         tzic_write_4(TZIC_ENCLEAR(nb / 32), (1UL <<(nb % 32)));
  184 }
  185 
  186 void
  187 arm_unmask_irq(uintptr_t nb)
  188 {
  189 
  190         tzic_write_4(TZIC_ENSET(nb / 32), (1UL <<(nb % 32)));
  191 }

Cache object: 21eacfe6e534b400d2e9c492fbac4b8f


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