The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/freescale/vybrid/vf_anadig.c

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (c) 2013-2014 Ruslan Bukin <br@bsdpad.com>
    5  * All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  *
   16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   26  * SUCH DAMAGE.
   27  */
   28 
   29 /*
   30  * Vybrid Family Analog components control digital interface (ANADIG)
   31  * Chapter 11, Vybrid Reference Manual, Rev. 5, 07/2013
   32  */
   33 
   34 #include <sys/cdefs.h>
   35 __FBSDID("$FreeBSD: head/sys/arm/freescale/vybrid/vf_anadig.c 326258 2017-11-27 15:04:10Z pfg $");
   36 
   37 #include <sys/param.h>
   38 #include <sys/systm.h>
   39 #include <sys/bus.h>
   40 #include <sys/kernel.h>
   41 #include <sys/module.h>
   42 #include <sys/malloc.h>
   43 #include <sys/rman.h>
   44 #include <sys/timeet.h>
   45 #include <sys/timetc.h>
   46 #include <sys/watchdog.h>
   47 
   48 #include <dev/ofw/openfirm.h>
   49 #include <dev/ofw/ofw_bus.h>
   50 #include <dev/ofw/ofw_bus_subr.h>
   51 
   52 #include <machine/bus.h>
   53 #include <machine/cpu.h>
   54 #include <machine/intr.h>
   55 
   56 #include <arm/freescale/vybrid/vf_common.h>
   57 
   58 #define ANADIG_PLL3_CTRL        0x010   /* PLL3 Control */
   59 #define ANADIG_PLL7_CTRL        0x020   /* PLL7 Control */
   60 #define ANADIG_PLL2_CTRL        0x030   /* PLL2 Control */
   61 #define ANADIG_PLL2_SS          0x040   /* PLL2 Spread Spectrum */
   62 #define ANADIG_PLL2_NUM         0x050   /* PLL2 Numerator */
   63 #define ANADIG_PLL2_DENOM       0x060   /* PLL2 Denominator */
   64 #define ANADIG_PLL4_CTRL        0x070   /* PLL4 Control */
   65 #define ANADIG_PLL4_NUM         0x080   /* PLL4 Numerator */
   66 #define ANADIG_PLL4_DENOM       0x090   /* PLL4 Denominator */
   67 #define ANADIG_PLL6_CTRL        0x0A0   /* PLL6 Control */
   68 #define ANADIG_PLL6_NUM         0x0B0   /* PLL6 Numerator */
   69 #define ANADIG_PLL6_DENOM       0x0C0   /* PLL6 Denominator */
   70 #define ANADIG_PLL5_CTRL        0x0E0   /* PLL5 Control */
   71 #define ANADIG_PLL3_PFD         0x0F0   /* PLL3 PFD */
   72 #define ANADIG_PLL2_PFD         0x100   /* PLL2 PFD */
   73 #define ANADIG_REG_1P1          0x110   /* Regulator 1P1 */
   74 #define ANADIG_REG_3P0          0x120   /* Regulator 3P0 */
   75 #define ANADIG_REG_2P5          0x130   /* Regulator 2P5 */
   76 #define ANADIG_ANA_MISC0        0x150   /* Analog Miscellaneous */
   77 #define ANADIG_ANA_MISC1        0x160   /* Analog Miscellaneous */
   78 #define ANADIG_ANADIG_DIGPROG   0x260   /* Digital Program */
   79 #define ANADIG_PLL1_CTRL        0x270   /* PLL1 Control */
   80 #define ANADIG_PLL1_SS          0x280   /* PLL1 Spread Spectrum */
   81 #define ANADIG_PLL1_NUM         0x290   /* PLL1 Numerator */
   82 #define ANADIG_PLL1_DENOM       0x2A0   /* PLL1 Denominator */
   83 #define ANADIG_PLL1_PFD         0x2B0   /* PLL1_PFD */
   84 #define ANADIG_PLL_LOCK         0x2C0   /* PLL Lock */
   85 
   86 #define USB_VBUS_DETECT(n)              (0x1A0 + 0x60 * n)
   87 #define USB_CHRG_DETECT(n)              (0x1B0 + 0x60 * n)
   88 #define USB_VBUS_DETECT_STATUS(n)       (0x1C0 + 0x60 * n)
   89 #define USB_CHRG_DETECT_STATUS(n)       (0x1D0 + 0x60 * n)
   90 #define USB_LOOPBACK(n)                 (0x1E0 + 0x60 * n)
   91 #define USB_MISC(n)                     (0x1F0 + 0x60 * n)
   92 
   93 #define ANADIG_PLL_LOCKED       (1U << 31)
   94 #define ENABLE_LINREG           (1 << 0)
   95 #define EN_CLK_TO_UTMI          (1 << 30)
   96 
   97 #define CTRL_BYPASS             (1 << 16)
   98 #define CTRL_PWR                (1 << 12)
   99 #define CTRL_PLL_EN             (1 << 13)
  100 #define EN_USB_CLKS             (1 << 6)
  101 
  102 #define PLL4_CTRL_DIV_SEL_S     0
  103 #define PLL4_CTRL_DIV_SEL_M     0x7f
  104 
  105 struct anadig_softc {
  106         struct resource         *res[1];
  107         bus_space_tag_t         bst;
  108         bus_space_handle_t      bsh;
  109 };
  110 
  111 struct anadig_softc *anadig_sc;
  112 
  113 static struct resource_spec anadig_spec[] = {
  114         { SYS_RES_MEMORY,       0,      RF_ACTIVE },
  115         { -1, 0 }
  116 };
  117 
  118 static int
  119 anadig_probe(device_t dev)
  120 {
  121 
  122         if (!ofw_bus_status_okay(dev))
  123                 return (ENXIO);
  124 
  125         if (!ofw_bus_is_compatible(dev, "fsl,mvf600-anadig"))
  126                 return (ENXIO);
  127 
  128         device_set_desc(dev, "Vybrid Family ANADIG Unit");
  129         return (BUS_PROBE_DEFAULT);
  130 }
  131 
  132 static int
  133 enable_pll(struct anadig_softc *sc, int pll_ctrl)
  134 {
  135         int reg;
  136 
  137         reg = READ4(sc, pll_ctrl);
  138         reg &= ~(CTRL_BYPASS | CTRL_PWR);
  139         if (pll_ctrl == ANADIG_PLL3_CTRL || pll_ctrl == ANADIG_PLL7_CTRL) {
  140                 /* It is USB PLL. Power bit logic is reversed */
  141                 reg |= (CTRL_PWR | EN_USB_CLKS);
  142         }
  143         WRITE4(sc, pll_ctrl, reg);
  144 
  145         /* Wait for PLL lock */
  146         while (!(READ4(sc, pll_ctrl) & ANADIG_PLL_LOCKED))
  147                 ;
  148 
  149         reg = READ4(sc, pll_ctrl);
  150         reg |= (CTRL_PLL_EN);
  151         WRITE4(sc, pll_ctrl, reg);
  152 
  153         return (0);
  154 }
  155 
  156 uint32_t
  157 pll4_configure_output(uint32_t mfi, uint32_t mfn, uint32_t mfd)
  158 {
  159         struct anadig_softc *sc;
  160         int reg;
  161 
  162         sc = anadig_sc;
  163 
  164         /*
  165          * PLLout = Fsys * (MFI+(MFN/MFD))
  166          */
  167 
  168         reg = READ4(sc, ANADIG_PLL4_CTRL);
  169         reg &= ~(PLL4_CTRL_DIV_SEL_M << PLL4_CTRL_DIV_SEL_S);
  170         reg |= (mfi << PLL4_CTRL_DIV_SEL_S);
  171         WRITE4(sc, ANADIG_PLL4_CTRL, reg);
  172         WRITE4(sc, ANADIG_PLL4_NUM, mfn);
  173         WRITE4(sc, ANADIG_PLL4_DENOM, mfd);
  174 
  175         return (0);
  176 }
  177 
  178 static int
  179 anadig_attach(device_t dev)
  180 {
  181         struct anadig_softc *sc;
  182         int reg;
  183 
  184         sc = device_get_softc(dev);
  185 
  186         if (bus_alloc_resources(dev, anadig_spec, sc->res)) {
  187                 device_printf(dev, "could not allocate resources\n");
  188                 return (ENXIO);
  189         }
  190 
  191         /* Memory interface */
  192         sc->bst = rman_get_bustag(sc->res[0]);
  193         sc->bsh = rman_get_bushandle(sc->res[0]);
  194 
  195         anadig_sc = sc;
  196 
  197         /* Enable USB PLLs */
  198         enable_pll(sc, ANADIG_PLL3_CTRL);
  199         enable_pll(sc, ANADIG_PLL7_CTRL);
  200 
  201         /* Enable other PLLs */
  202         enable_pll(sc, ANADIG_PLL1_CTRL);
  203         enable_pll(sc, ANADIG_PLL2_CTRL);
  204         enable_pll(sc, ANADIG_PLL4_CTRL);
  205         enable_pll(sc, ANADIG_PLL5_CTRL);
  206         enable_pll(sc, ANADIG_PLL6_CTRL);
  207 
  208         /* Enable USB voltage regulator */
  209         reg = READ4(sc, ANADIG_REG_3P0);
  210         reg |= (ENABLE_LINREG);
  211         WRITE4(sc, ANADIG_REG_3P0, reg);
  212 
  213         /* Give clocks to USB */
  214         reg = READ4(sc, USB_MISC(0));
  215         reg |= (EN_CLK_TO_UTMI);
  216         WRITE4(sc, USB_MISC(0), reg);
  217 
  218         reg = READ4(sc, USB_MISC(1));
  219         reg |= (EN_CLK_TO_UTMI);
  220         WRITE4(sc, USB_MISC(1), reg);
  221 
  222 #if 0
  223         printf("USB_ANALOG_USB_MISC(0) == 0x%08x\n",
  224             READ4(sc, USB_ANALOG_USB_MISC(0)));
  225         printf("USB_ANALOG_USB_MISC(1) == 0x%08x\n",
  226             READ4(sc, USB_ANALOG_USB_MISC(1)));
  227 #endif
  228 
  229         return (0);
  230 }
  231 
  232 static device_method_t anadig_methods[] = {
  233         DEVMETHOD(device_probe,         anadig_probe),
  234         DEVMETHOD(device_attach,        anadig_attach),
  235         { 0, 0 }
  236 };
  237 
  238 static driver_t anadig_driver = {
  239         "anadig",
  240         anadig_methods,
  241         sizeof(struct anadig_softc),
  242 };
  243 
  244 static devclass_t anadig_devclass;
  245 
  246 DRIVER_MODULE(anadig, simplebus, anadig_driver, anadig_devclass, 0, 0);

Cache object: 48244253828e6134820f83cb9152a4be


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