Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/arm/freescale/vybrid/vf_dcu4.c
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1 /*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * Vybrid Family Display Control Unit (DCU4) 29 * Chapter 55, Vybrid Reference Manual, Rev. 5, 07/2013 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD: releng/10.2/sys/arm/freescale/vybrid/vf_dcu4.c 266274 2014-05-16 23:27:18Z ian $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/kernel.h> 39 #include <sys/module.h> 40 #include <sys/malloc.h> 41 #include <sys/rman.h> 42 #include <sys/timeet.h> 43 #include <sys/timetc.h> 44 #include <sys/watchdog.h> 45 #include <sys/fbio.h> 46 #include <sys/consio.h> 47 #include <sys/eventhandler.h> 48 #include <sys/gpio.h> 49 50 #include <dev/fdt/fdt_common.h> 51 #include <dev/ofw/openfirm.h> 52 #include <dev/ofw/ofw_bus.h> 53 #include <dev/ofw/ofw_bus_subr.h> 54 55 #include <dev/vt/vt.h> 56 #include <dev/vt/colors/vt_termcolors.h> 57 58 #include "gpio_if.h" 59 60 #include <machine/bus.h> 61 #include <machine/fdt.h> 62 #include <machine/cpu.h> 63 #include <machine/intr.h> 64 65 #include "fb_if.h" 66 67 #include <arm/freescale/vybrid/vf_common.h> 68 69 #define DCU_CTRLDESCCURSOR1 0x000 /* Control Descriptor Cursor 1 */ 70 #define DCU_CTRLDESCCURSOR2 0x004 /* Control Descriptor Cursor 2 */ 71 #define DCU_CTRLDESCCURSOR3 0x008 /* Control Descriptor Cursor 3 */ 72 #define DCU_CTRLDESCCURSOR4 0x00C /* Control Descriptor Cursor 4 */ 73 #define DCU_DCU_MODE 0x010 /* DCU4 Mode */ 74 #define DCU_MODE_M 0x3 75 #define DCU_MODE_S 0 76 #define DCU_MODE_NORMAL 0x1 77 #define DCU_MODE_TEST 0x2 78 #define DCU_MODE_COLBAR 0x3 79 #define RASTER_EN (1 << 14) /* Raster scan of pixel data */ 80 #define PDI_EN (1 << 13) 81 #define PDI_DE_MODE (1 << 11) 82 #define PDI_MODE_M 2 83 #define DCU_BGND 0x014 /* Background */ 84 #define DCU_DISP_SIZE 0x018 /* Display Size */ 85 #define DELTA_M 0x7ff 86 #define DELTA_Y_S 16 87 #define DELTA_X_S 0 88 #define DCU_HSYN_PARA 0x01C /* Horizontal Sync Parameter */ 89 #define BP_H_SHIFT 22 90 #define PW_H_SHIFT 11 91 #define FP_H_SHIFT 0 92 #define DCU_VSYN_PARA 0x020 /* Vertical Sync Parameter */ 93 #define BP_V_SHIFT 22 94 #define PW_V_SHIFT 11 95 #define FP_V_SHIFT 0 96 #define DCU_SYNPOL 0x024 /* Synchronize Polarity */ 97 #define INV_HS (1 << 0) 98 #define INV_VS (1 << 1) 99 #define INV_PDI_VS (1 << 8) /* Polarity of PDI input VSYNC. */ 100 #define INV_PDI_HS (1 << 9) /* Polarity of PDI input HSYNC. */ 101 #define INV_PDI_DE (1 << 10) /* Polarity of PDI input DE. */ 102 #define DCU_THRESHOLD 0x028 /* Threshold */ 103 #define LS_BF_VS_SHIFT 16 104 #define OUT_BUF_HIGH_SHIFT 8 105 #define OUT_BUF_LOW_SHIFT 0 106 #define DCU_INT_STATUS 0x02C /* Interrupt Status */ 107 #define DCU_INT_MASK 0x030 /* Interrupt Mask */ 108 #define DCU_COLBAR_1 0x034 /* COLBAR_1 */ 109 #define DCU_COLBAR_2 0x038 /* COLBAR_2 */ 110 #define DCU_COLBAR_3 0x03C /* COLBAR_3 */ 111 #define DCU_COLBAR_4 0x040 /* COLBAR_4 */ 112 #define DCU_COLBAR_5 0x044 /* COLBAR_5 */ 113 #define DCU_COLBAR_6 0x048 /* COLBAR_6 */ 114 #define DCU_COLBAR_7 0x04C /* COLBAR_7 */ 115 #define DCU_COLBAR_8 0x050 /* COLBAR_8 */ 116 #define DCU_DIV_RATIO 0x054 /* Divide Ratio */ 117 #define DCU_SIGN_CALC_1 0x058 /* Sign Calculation 1 */ 118 #define DCU_SIGN_CALC_2 0x05C /* Sign Calculation 2 */ 119 #define DCU_CRC_VAL 0x060 /* CRC Value */ 120 #define DCU_PDI_STATUS 0x064 /* PDI Status */ 121 #define DCU_PDI_STA_MSK 0x068 /* PDI Status Mask */ 122 #define DCU_PARR_ERR_STATUS1 0x06C /* Parameter Error Status 1 */ 123 #define DCU_PARR_ERR_STATUS2 0x070 /* Parameter Error Status 2 */ 124 #define DCU_PARR_ERR_STATUS3 0x07C /* Parameter Error Status 3 */ 125 #define DCU_MASK_PARR_ERR_ST1 0x080 /* Mask Parameter Error Status 1 */ 126 #define DCU_MASK_PARR_ERR_ST2 0x084 /* Mask Parameter Error Status 2 */ 127 #define DCU_MASK_PARR_ERR_ST3 0x090 /* Mask Parameter Error Status 3 */ 128 #define DCU_THRESHOLD_INP_BUF_1 0x094 /* Threshold Input 1 */ 129 #define DCU_THRESHOLD_INP_BUF_2 0x098 /* Threshold Input 2 */ 130 #define DCU_THRESHOLD_INP_BUF_3 0x09C /* Threshold Input 3 */ 131 #define DCU_LUMA_COMP 0x0A0 /* LUMA Component */ 132 #define DCU_CHROMA_RED 0x0A4 /* Red Chroma Components */ 133 #define DCU_CHROMA_GREEN 0x0A8 /* Green Chroma Components */ 134 #define DCU_CHROMA_BLUE 0x0AC /* Blue Chroma Components */ 135 #define DCU_CRC_POS 0x0B0 /* CRC Position */ 136 #define DCU_LYR_INTPOL_EN 0x0B4 /* Layer Interpolation Enable */ 137 #define DCU_LYR_LUMA_COMP 0x0B8 /* Layer Luminance Component */ 138 #define DCU_LYR_CHRM_RED 0x0BC /* Layer Chroma Red */ 139 #define DCU_LYR_CHRM_GRN 0x0C0 /* Layer Chroma Green */ 140 #define DCU_LYR_CHRM_BLUE 0x0C4 /* Layer Chroma Blue */ 141 #define DCU_COMP_IMSIZE 0x0C8 /* Compression Image Size */ 142 #define DCU_UPDATE_MODE 0x0CC /* Update Mode */ 143 #define READREG (1 << 30) 144 #define MODE (1 << 31) 145 #define DCU_UNDERRUN 0x0D0 /* Underrun */ 146 #define DCU_GLBL_PROTECT 0x100 /* Global Protection */ 147 #define DCU_SFT_LCK_BIT_L0 0x104 /* Soft Lock Bit Layer 0 */ 148 #define DCU_SFT_LCK_BIT_L1 0x108 /* Soft Lock Bit Layer 1 */ 149 #define DCU_SFT_LCK_DISP_SIZE 0x10C /* Soft Lock Display Size */ 150 #define DCU_SFT_LCK_HS_VS_PARA 0x110 /* Soft Lock Hsync/Vsync Parameter */ 151 #define DCU_SFT_LCK_POL 0x114 /* Soft Lock POL */ 152 #define DCU_SFT_LCK_L0_TRANSP 0x118 /* Soft Lock L0 Transparency */ 153 #define DCU_SFT_LCK_L1_TRANSP 0x11C /* Soft Lock L1 Transparency */ 154 155 /* Control Descriptor */ 156 #define DCU_CTRLDESCL(n, m) 0x200 + (0x40 * n) + 0x4 * (m - 1) 157 #define DCU_CTRLDESCLn_1(n) DCU_CTRLDESCL(n, 1) 158 #define DCU_CTRLDESCLn_2(n) DCU_CTRLDESCL(n, 2) 159 #define DCU_CTRLDESCLn_3(n) DCU_CTRLDESCL(n, 3) 160 #define TRANS_SHIFT 20 161 #define DCU_CTRLDESCLn_4(n) DCU_CTRLDESCL(n, 4) 162 #define BPP_MASK 0xf /* Bit per pixel Mask */ 163 #define BPP_SHIFT 16 /* Bit per pixel Shift */ 164 #define BPP24 0x5 165 #define EN_LAYER (1 << 31) /* Enable the layer */ 166 #define DCU_CTRLDESCLn_5(n) DCU_CTRLDESCL(n, 5) 167 #define DCU_CTRLDESCLn_6(n) DCU_CTRLDESCL(n, 6) 168 #define DCU_CTRLDESCLn_7(n) DCU_CTRLDESCL(n, 7) 169 #define DCU_CTRLDESCLn_8(n) DCU_CTRLDESCL(n, 8) 170 #define DCU_CTRLDESCLn_9(n) DCU_CTRLDESCL(n, 9) 171 172 #define NUM_LAYERS 64 173 174 struct panel_info { 175 uint32_t width; 176 uint32_t height; 177 uint32_t h_back_porch; 178 uint32_t h_pulse_width; 179 uint32_t h_front_porch; 180 uint32_t v_back_porch; 181 uint32_t v_pulse_width; 182 uint32_t v_front_porch; 183 uint32_t clk_div; 184 uint32_t backlight_pin; 185 }; 186 187 struct dcu_softc { 188 struct resource *res[2]; 189 bus_space_tag_t bst; 190 bus_space_handle_t bsh; 191 void *ih; 192 device_t dev; 193 device_t sc_fbd; /* fbd child */ 194 struct fb_info sc_info; 195 struct panel_info *panel; 196 }; 197 198 static struct resource_spec dcu_spec[] = { 199 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 200 { SYS_RES_IRQ, 0, RF_ACTIVE }, 201 { -1, 0 } 202 }; 203 204 static int 205 dcu_probe(device_t dev) 206 { 207 208 if (!ofw_bus_status_okay(dev)) 209 return (ENXIO); 210 211 if (!ofw_bus_is_compatible(dev, "fsl,mvf600-dcu4")) 212 return (ENXIO); 213 214 device_set_desc(dev, "Vybrid Family Display Control Unit (DCU4)"); 215 return (BUS_PROBE_DEFAULT); 216 } 217 218 static void 219 dcu_intr(void *arg) 220 { 221 struct dcu_softc *sc; 222 int reg; 223 224 sc = arg; 225 226 /* Ack interrupts */ 227 reg = READ4(sc, DCU_INT_STATUS); 228 WRITE4(sc, DCU_INT_STATUS, reg); 229 230 /* TODO interrupt handler */ 231 } 232 233 static int 234 get_panel_info(struct dcu_softc *sc, struct panel_info *panel) 235 { 236 phandle_t node; 237 pcell_t dts_value[3]; 238 int len; 239 240 if ((node = ofw_bus_get_node(sc->dev)) == -1) 241 return (ENXIO); 242 243 /* panel size */ 244 if ((len = OF_getproplen(node, "panel-size")) <= 0) 245 return (ENXIO); 246 OF_getprop(node, "panel-size", &dts_value, len); 247 panel->width = fdt32_to_cpu(dts_value[0]); 248 panel->height = fdt32_to_cpu(dts_value[1]); 249 250 /* hsync */ 251 if ((len = OF_getproplen(node, "panel-hsync")) <= 0) 252 return (ENXIO); 253 OF_getprop(node, "panel-hsync", &dts_value, len); 254 panel->h_back_porch = fdt32_to_cpu(dts_value[0]); 255 panel->h_pulse_width = fdt32_to_cpu(dts_value[1]); 256 panel->h_front_porch = fdt32_to_cpu(dts_value[2]); 257 258 /* vsync */ 259 if ((len = OF_getproplen(node, "panel-vsync")) <= 0) 260 return (ENXIO); 261 OF_getprop(node, "panel-vsync", &dts_value, len); 262 panel->v_back_porch = fdt32_to_cpu(dts_value[0]); 263 panel->v_pulse_width = fdt32_to_cpu(dts_value[1]); 264 panel->v_front_porch = fdt32_to_cpu(dts_value[2]); 265 266 /* clk divider */ 267 if ((len = OF_getproplen(node, "panel-clk-div")) <= 0) 268 return (ENXIO); 269 OF_getprop(node, "panel-clk-div", &dts_value, len); 270 panel->clk_div = fdt32_to_cpu(dts_value[0]); 271 272 /* backlight pin */ 273 if ((len = OF_getproplen(node, "panel-backlight-pin")) <= 0) 274 return (ENXIO); 275 OF_getprop(node, "panel-backlight-pin", &dts_value, len); 276 panel->backlight_pin = fdt32_to_cpu(dts_value[0]); 277 278 return (0); 279 } 280 281 static int 282 dcu_init(struct dcu_softc *sc) 283 { 284 struct panel_info *panel; 285 int reg; 286 int i; 287 288 panel = sc->panel; 289 290 /* Configure DCU */ 291 reg = ((sc->sc_info.fb_height) << DELTA_Y_S); 292 reg |= (sc->sc_info.fb_width / 16); 293 WRITE4(sc, DCU_DISP_SIZE, reg); 294 295 reg = (panel->h_back_porch << BP_H_SHIFT); 296 reg |= (panel->h_pulse_width << PW_H_SHIFT); 297 reg |= (panel->h_front_porch << FP_H_SHIFT); 298 WRITE4(sc, DCU_HSYN_PARA, reg); 299 300 reg = (panel->v_back_porch << BP_V_SHIFT); 301 reg |= (panel->v_pulse_width << PW_V_SHIFT); 302 reg |= (panel->v_front_porch << FP_V_SHIFT); 303 WRITE4(sc, DCU_VSYN_PARA, reg); 304 305 WRITE4(sc, DCU_BGND, 0); 306 WRITE4(sc, DCU_DIV_RATIO, panel->clk_div); 307 308 reg = (INV_VS | INV_HS); 309 WRITE4(sc, DCU_SYNPOL, reg); 310 311 /* TODO: export to panel info */ 312 reg = (0x3 << LS_BF_VS_SHIFT); 313 reg |= (0x78 << OUT_BUF_HIGH_SHIFT); 314 reg |= (0 << OUT_BUF_LOW_SHIFT); 315 WRITE4(sc, DCU_THRESHOLD, reg); 316 317 /* Mask all the interrupts */ 318 WRITE4(sc, DCU_INT_MASK, 0xffffffff); 319 320 /* Reset all layers */ 321 for (i = 0; i < NUM_LAYERS; i++) { 322 WRITE4(sc, DCU_CTRLDESCLn_1(i), 0x0); 323 WRITE4(sc, DCU_CTRLDESCLn_2(i), 0x0); 324 WRITE4(sc, DCU_CTRLDESCLn_3(i), 0x0); 325 WRITE4(sc, DCU_CTRLDESCLn_4(i), 0x0); 326 WRITE4(sc, DCU_CTRLDESCLn_5(i), 0x0); 327 WRITE4(sc, DCU_CTRLDESCLn_6(i), 0x0); 328 WRITE4(sc, DCU_CTRLDESCLn_7(i), 0x0); 329 WRITE4(sc, DCU_CTRLDESCLn_8(i), 0x0); 330 WRITE4(sc, DCU_CTRLDESCLn_9(i), 0x0); 331 } 332 333 /* Setup first layer */ 334 reg = (sc->sc_info.fb_width | (sc->sc_info.fb_height << 16)); 335 WRITE4(sc, DCU_CTRLDESCLn_1(0), reg); 336 WRITE4(sc, DCU_CTRLDESCLn_2(0), 0x0); 337 WRITE4(sc, DCU_CTRLDESCLn_3(0), sc->sc_info.fb_pbase); 338 reg = (BPP24 << BPP_SHIFT); 339 reg |= EN_LAYER; 340 reg |= (0xFF << TRANS_SHIFT); /* completely opaque */ 341 WRITE4(sc, DCU_CTRLDESCLn_4(0), reg); 342 WRITE4(sc, DCU_CTRLDESCLn_5(0), 0xffffff); 343 WRITE4(sc, DCU_CTRLDESCLn_6(0), 0x0); 344 WRITE4(sc, DCU_CTRLDESCLn_7(0), 0x0); 345 WRITE4(sc, DCU_CTRLDESCLn_8(0), 0x0); 346 WRITE4(sc, DCU_CTRLDESCLn_9(0), 0x0); 347 348 /* Enable DCU in normal mode */ 349 reg = READ4(sc, DCU_DCU_MODE); 350 reg &= ~(DCU_MODE_M << DCU_MODE_S); 351 reg |= (DCU_MODE_NORMAL << DCU_MODE_S); 352 reg |= (RASTER_EN); 353 WRITE4(sc, DCU_DCU_MODE, reg); 354 WRITE4(sc, DCU_UPDATE_MODE, READREG); 355 356 return (0); 357 } 358 359 static int 360 dcu_attach(device_t dev) 361 { 362 struct panel_info panel; 363 struct dcu_softc *sc; 364 device_t gpio_dev; 365 int err; 366 367 sc = device_get_softc(dev); 368 sc->dev = dev; 369 370 if (bus_alloc_resources(dev, dcu_spec, sc->res)) { 371 device_printf(dev, "could not allocate resources\n"); 372 return (ENXIO); 373 } 374 375 /* Memory interface */ 376 sc->bst = rman_get_bustag(sc->res[0]); 377 sc->bsh = rman_get_bushandle(sc->res[0]); 378 379 /* Setup interrupt handler */ 380 err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_BIO | INTR_MPSAFE, 381 NULL, dcu_intr, sc, &sc->ih); 382 if (err) { 383 device_printf(dev, "Unable to alloc interrupt resource.\n"); 384 return (ENXIO); 385 } 386 387 if (get_panel_info(sc, &panel)) { 388 device_printf(dev, "Can't get panel info\n"); 389 return (ENXIO); 390 } 391 392 sc->panel = &panel; 393 394 /* Bypass timing control (used for raw lcd panels) */ 395 tcon_bypass(); 396 397 /* Get the GPIO device, we need this to give power to USB */ 398 gpio_dev = devclass_get_device(devclass_find("gpio"), 0); 399 if (gpio_dev == NULL) { 400 device_printf(sc->dev, "Error: failed to get the GPIO dev\n"); 401 return (1); 402 } 403 404 /* Turn on backlight */ 405 /* TODO: Use FlexTimer/PWM */ 406 GPIO_PIN_SETFLAGS(gpio_dev, panel.backlight_pin, GPIO_PIN_OUTPUT); 407 GPIO_PIN_SET(gpio_dev, panel.backlight_pin, GPIO_PIN_HIGH); 408 409 sc->sc_info.fb_width = panel.width; 410 sc->sc_info.fb_height = panel.height; 411 sc->sc_info.fb_stride = sc->sc_info.fb_width * 3; 412 sc->sc_info.fb_bpp = sc->sc_info.fb_depth = 24; 413 sc->sc_info.fb_size = sc->sc_info.fb_height * sc->sc_info.fb_stride; 414 sc->sc_info.fb_vbase = (intptr_t)contigmalloc(sc->sc_info.fb_size, 415 M_DEVBUF, M_ZERO, 0, ~0, PAGE_SIZE, 0); 416 sc->sc_info.fb_pbase = (intptr_t)vtophys(sc->sc_info.fb_vbase); 417 418 #if 0 419 printf("%dx%d [%d]\n", sc->sc_info.fb_width, sc->sc_info.fb_height, 420 sc->sc_info.fb_stride); 421 printf("pbase == 0x%08x\n", sc->sc_info.fb_pbase); 422 #endif 423 424 memset((int8_t *)sc->sc_info.fb_vbase, 0x0, sc->sc_info.fb_size); 425 426 dcu_init(sc); 427 428 sc->sc_info.fb_name = device_get_nameunit(dev); 429 430 /* Ask newbus to attach framebuffer device to me. */ 431 sc->sc_fbd = device_add_child(dev, "fbd", device_get_unit(dev)); 432 if (sc->sc_fbd == NULL) 433 device_printf(dev, "Can't attach fbd device\n"); 434 435 if (device_probe_and_attach(sc->sc_fbd) != 0) { 436 device_printf(sc->dev, "Failed to attach fbd device\n"); 437 } 438 439 return (0); 440 } 441 442 static struct fb_info * 443 dcu4_fb_getinfo(device_t dev) 444 { 445 struct dcu_softc *sc = device_get_softc(dev); 446 447 return (&sc->sc_info); 448 } 449 450 static device_method_t dcu_methods[] = { 451 DEVMETHOD(device_probe, dcu_probe), 452 DEVMETHOD(device_attach, dcu_attach), 453 454 /* Framebuffer service methods */ 455 DEVMETHOD(fb_getinfo, dcu4_fb_getinfo), 456 { 0, 0 } 457 }; 458 459 static driver_t dcu_driver = { 460 "fb", 461 dcu_methods, 462 sizeof(struct dcu_softc), 463 }; 464 465 static devclass_t dcu_devclass; 466 467 DRIVER_MODULE(fb, simplebus, dcu_driver, dcu_devclass, 0, 0);
Cache object: 3110ca4a39059d9cc3b2d42cfa6c3e8a
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