The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/freescale/vybrid/vf_dcu4.c

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    1 /*-
    2  * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  */
   26 
   27 /*
   28  * Vybrid Family Display Control Unit (DCU4)
   29  * Chapter 55, Vybrid Reference Manual, Rev. 5, 07/2013
   30  */
   31 
   32 #include <sys/cdefs.h>
   33 __FBSDID("$FreeBSD: releng/11.1/sys/arm/freescale/vybrid/vf_dcu4.c 314503 2017-03-01 18:53:05Z ian $");
   34 
   35 #include <sys/param.h>
   36 #include <sys/systm.h>
   37 #include <sys/bus.h>
   38 #include <sys/kernel.h>
   39 #include <sys/module.h>
   40 #include <sys/malloc.h>
   41 #include <sys/rman.h>
   42 #include <sys/timeet.h>
   43 #include <sys/timetc.h>
   44 #include <sys/watchdog.h>
   45 #include <sys/fbio.h>
   46 #include <sys/consio.h>
   47 #include <sys/eventhandler.h>
   48 #include <sys/gpio.h>
   49 
   50 #include <vm/vm.h>
   51 #include <vm/pmap.h>
   52 
   53 #include <dev/ofw/openfirm.h>
   54 #include <dev/ofw/ofw_bus.h>
   55 #include <dev/ofw/ofw_bus_subr.h>
   56 
   57 #include <dev/vt/vt.h>
   58 #include <dev/vt/colors/vt_termcolors.h>
   59 
   60 #include "gpio_if.h"
   61 
   62 #include <machine/bus.h>
   63 #include <machine/fdt.h>
   64 #include <machine/cpu.h>
   65 #include <machine/intr.h>
   66 
   67 #include "fb_if.h"
   68 
   69 #include <arm/freescale/vybrid/vf_common.h>
   70 
   71 #define DCU_CTRLDESCCURSOR1     0x000   /* Control Descriptor Cursor 1 */
   72 #define DCU_CTRLDESCCURSOR2     0x004   /* Control Descriptor Cursor 2 */
   73 #define DCU_CTRLDESCCURSOR3     0x008   /* Control Descriptor Cursor 3 */
   74 #define DCU_CTRLDESCCURSOR4     0x00C   /* Control Descriptor Cursor 4 */
   75 #define DCU_DCU_MODE            0x010   /* DCU4 Mode */
   76 #define  DCU_MODE_M             0x3
   77 #define  DCU_MODE_S             0
   78 #define  DCU_MODE_NORMAL        0x1
   79 #define  DCU_MODE_TEST          0x2
   80 #define  DCU_MODE_COLBAR        0x3
   81 #define  RASTER_EN              (1 << 14)       /* Raster scan of pixel data */
   82 #define  PDI_EN                 (1 << 13)
   83 #define  PDI_DE_MODE            (1 << 11)
   84 #define  PDI_MODE_M             2
   85 #define DCU_BGND                0x014   /* Background */
   86 #define DCU_DISP_SIZE           0x018   /* Display Size */
   87 #define  DELTA_M                0x7ff
   88 #define  DELTA_Y_S              16
   89 #define  DELTA_X_S              0
   90 #define DCU_HSYN_PARA           0x01C   /* Horizontal Sync Parameter */
   91 #define  BP_H_SHIFT             22
   92 #define  PW_H_SHIFT             11
   93 #define  FP_H_SHIFT             0
   94 #define DCU_VSYN_PARA           0x020   /* Vertical Sync Parameter */
   95 #define  BP_V_SHIFT             22
   96 #define  PW_V_SHIFT             11
   97 #define  FP_V_SHIFT             0
   98 #define DCU_SYNPOL              0x024   /* Synchronize Polarity */
   99 #define  INV_HS                 (1 << 0)
  100 #define  INV_VS                 (1 << 1)
  101 #define  INV_PDI_VS             (1 << 8) /* Polarity of PDI input VSYNC. */
  102 #define  INV_PDI_HS             (1 << 9) /* Polarity of PDI input HSYNC. */
  103 #define  INV_PDI_DE             (1 << 10) /* Polarity of PDI input DE. */
  104 #define DCU_THRESHOLD           0x028   /* Threshold */
  105 #define  LS_BF_VS_SHIFT         16
  106 #define  OUT_BUF_HIGH_SHIFT     8
  107 #define  OUT_BUF_LOW_SHIFT      0
  108 #define DCU_INT_STATUS          0x02C   /* Interrupt Status */
  109 #define DCU_INT_MASK            0x030   /* Interrupt Mask */
  110 #define DCU_COLBAR_1            0x034   /* COLBAR_1 */
  111 #define DCU_COLBAR_2            0x038   /* COLBAR_2 */
  112 #define DCU_COLBAR_3            0x03C   /* COLBAR_3 */
  113 #define DCU_COLBAR_4            0x040   /* COLBAR_4 */
  114 #define DCU_COLBAR_5            0x044   /* COLBAR_5 */
  115 #define DCU_COLBAR_6            0x048   /* COLBAR_6 */
  116 #define DCU_COLBAR_7            0x04C   /* COLBAR_7 */
  117 #define DCU_COLBAR_8            0x050   /* COLBAR_8 */
  118 #define DCU_DIV_RATIO           0x054   /* Divide Ratio */
  119 #define DCU_SIGN_CALC_1         0x058   /* Sign Calculation 1 */
  120 #define DCU_SIGN_CALC_2         0x05C   /* Sign Calculation 2 */
  121 #define DCU_CRC_VAL             0x060   /* CRC Value */
  122 #define DCU_PDI_STATUS          0x064   /* PDI Status */
  123 #define DCU_PDI_STA_MSK         0x068   /* PDI Status Mask */
  124 #define DCU_PARR_ERR_STATUS1    0x06C   /* Parameter Error Status 1 */
  125 #define DCU_PARR_ERR_STATUS2    0x070   /* Parameter Error Status 2 */
  126 #define DCU_PARR_ERR_STATUS3    0x07C   /* Parameter Error Status 3 */
  127 #define DCU_MASK_PARR_ERR_ST1   0x080   /* Mask Parameter Error Status 1 */
  128 #define DCU_MASK_PARR_ERR_ST2   0x084   /* Mask Parameter Error Status 2 */
  129 #define DCU_MASK_PARR_ERR_ST3   0x090   /* Mask Parameter Error Status 3 */
  130 #define DCU_THRESHOLD_INP_BUF_1 0x094   /* Threshold Input 1 */
  131 #define DCU_THRESHOLD_INP_BUF_2 0x098   /* Threshold Input 2 */
  132 #define DCU_THRESHOLD_INP_BUF_3 0x09C   /* Threshold Input 3 */
  133 #define DCU_LUMA_COMP           0x0A0   /* LUMA Component */
  134 #define DCU_CHROMA_RED          0x0A4   /* Red Chroma Components */
  135 #define DCU_CHROMA_GREEN        0x0A8   /* Green Chroma Components */
  136 #define DCU_CHROMA_BLUE         0x0AC   /* Blue Chroma Components */
  137 #define DCU_CRC_POS             0x0B0   /* CRC Position */
  138 #define DCU_LYR_INTPOL_EN       0x0B4   /* Layer Interpolation Enable */
  139 #define DCU_LYR_LUMA_COMP       0x0B8   /* Layer Luminance Component */
  140 #define DCU_LYR_CHRM_RED        0x0BC   /* Layer Chroma Red */
  141 #define DCU_LYR_CHRM_GRN        0x0C0   /* Layer Chroma Green */
  142 #define DCU_LYR_CHRM_BLUE       0x0C4   /* Layer Chroma Blue */
  143 #define DCU_COMP_IMSIZE         0x0C8   /* Compression Image Size */
  144 #define DCU_UPDATE_MODE         0x0CC   /* Update Mode */
  145 #define  READREG                (1 << 30)
  146 #define  MODE                   (1 << 31)
  147 #define DCU_UNDERRUN            0x0D0   /* Underrun */
  148 #define DCU_GLBL_PROTECT        0x100   /* Global Protection */
  149 #define DCU_SFT_LCK_BIT_L0      0x104   /* Soft Lock Bit Layer 0 */
  150 #define DCU_SFT_LCK_BIT_L1      0x108   /* Soft Lock Bit Layer 1 */
  151 #define DCU_SFT_LCK_DISP_SIZE   0x10C   /* Soft Lock Display Size */
  152 #define DCU_SFT_LCK_HS_VS_PARA  0x110   /* Soft Lock Hsync/Vsync Parameter */
  153 #define DCU_SFT_LCK_POL         0x114   /* Soft Lock POL */
  154 #define DCU_SFT_LCK_L0_TRANSP   0x118   /* Soft Lock L0 Transparency */
  155 #define DCU_SFT_LCK_L1_TRANSP   0x11C   /* Soft Lock L1 Transparency */
  156 
  157 /* Control Descriptor */
  158 #define DCU_CTRLDESCL(n, m)     0x200 + (0x40 * n) + 0x4 * (m - 1)
  159 #define DCU_CTRLDESCLn_1(n)     DCU_CTRLDESCL(n, 1)
  160 #define DCU_CTRLDESCLn_2(n)     DCU_CTRLDESCL(n, 2)
  161 #define DCU_CTRLDESCLn_3(n)     DCU_CTRLDESCL(n, 3)
  162 #define  TRANS_SHIFT            20
  163 #define DCU_CTRLDESCLn_4(n)     DCU_CTRLDESCL(n, 4)
  164 #define  BPP_MASK               0xf             /* Bit per pixel Mask */
  165 #define  BPP_SHIFT              16              /* Bit per pixel Shift */
  166 #define  BPP24                  0x5
  167 #define  EN_LAYER               (1 << 31)       /* Enable the layer */
  168 #define DCU_CTRLDESCLn_5(n)     DCU_CTRLDESCL(n, 5)
  169 #define DCU_CTRLDESCLn_6(n)     DCU_CTRLDESCL(n, 6)
  170 #define DCU_CTRLDESCLn_7(n)     DCU_CTRLDESCL(n, 7)
  171 #define DCU_CTRLDESCLn_8(n)     DCU_CTRLDESCL(n, 8)
  172 #define DCU_CTRLDESCLn_9(n)     DCU_CTRLDESCL(n, 9)
  173 
  174 #define NUM_LAYERS      64
  175 
  176 struct panel_info {
  177         uint32_t        width;
  178         uint32_t        height;
  179         uint32_t        h_back_porch;
  180         uint32_t        h_pulse_width;
  181         uint32_t        h_front_porch;
  182         uint32_t        v_back_porch;
  183         uint32_t        v_pulse_width;
  184         uint32_t        v_front_porch;
  185         uint32_t        clk_div;
  186         uint32_t        backlight_pin;
  187 };
  188 
  189 struct dcu_softc {
  190         struct resource         *res[2];
  191         bus_space_tag_t         bst;
  192         bus_space_handle_t      bsh;
  193         void                    *ih;
  194         device_t                dev;
  195         device_t                sc_fbd;         /* fbd child */
  196         struct fb_info          sc_info;
  197         struct panel_info       *panel;
  198 };
  199 
  200 static struct resource_spec dcu_spec[] = {
  201         { SYS_RES_MEMORY,       0,      RF_ACTIVE },
  202         { SYS_RES_IRQ,          0,      RF_ACTIVE },
  203         { -1, 0 }
  204 };
  205 
  206 static int
  207 dcu_probe(device_t dev)
  208 {
  209 
  210         if (!ofw_bus_status_okay(dev))
  211                 return (ENXIO);
  212 
  213         if (!ofw_bus_is_compatible(dev, "fsl,mvf600-dcu4"))
  214                 return (ENXIO);
  215 
  216         device_set_desc(dev, "Vybrid Family Display Control Unit (DCU4)");
  217         return (BUS_PROBE_DEFAULT);
  218 }
  219 
  220 static void
  221 dcu_intr(void *arg)
  222 {
  223         struct dcu_softc *sc;
  224         int reg;
  225 
  226         sc = arg;
  227 
  228         /* Ack interrupts */
  229         reg = READ4(sc, DCU_INT_STATUS);
  230         WRITE4(sc, DCU_INT_STATUS, reg);
  231 
  232         /* TODO interrupt handler */
  233 }
  234 
  235 static int
  236 get_panel_info(struct dcu_softc *sc, struct panel_info *panel)
  237 {
  238         phandle_t node;
  239         pcell_t dts_value[3];
  240         int len;
  241 
  242         if ((node = ofw_bus_get_node(sc->dev)) == -1)
  243                 return (ENXIO);
  244 
  245         /* panel size */
  246         if ((len = OF_getproplen(node, "panel-size")) <= 0)
  247                 return (ENXIO);
  248         OF_getencprop(node, "panel-size", dts_value, len);
  249         panel->width = dts_value[0];
  250         panel->height = dts_value[1];
  251 
  252         /* hsync */
  253         if ((len = OF_getproplen(node, "panel-hsync")) <= 0)
  254                 return (ENXIO);
  255         OF_getencprop(node, "panel-hsync", dts_value, len);
  256         panel->h_back_porch = dts_value[0];
  257         panel->h_pulse_width = dts_value[1];
  258         panel->h_front_porch = dts_value[2];
  259 
  260         /* vsync */
  261         if ((len = OF_getproplen(node, "panel-vsync")) <= 0)
  262                 return (ENXIO);
  263         OF_getencprop(node, "panel-vsync", dts_value, len);
  264         panel->v_back_porch = dts_value[0];
  265         panel->v_pulse_width = dts_value[1];
  266         panel->v_front_porch = dts_value[2];
  267 
  268         /* clk divider */
  269         if ((len = OF_getproplen(node, "panel-clk-div")) <= 0)
  270                 return (ENXIO);
  271         OF_getencprop(node, "panel-clk-div", dts_value, len);
  272         panel->clk_div = dts_value[0];
  273 
  274         /* backlight pin */
  275         if ((len = OF_getproplen(node, "panel-backlight-pin")) <= 0)
  276                 return (ENXIO);
  277         OF_getencprop(node, "panel-backlight-pin", dts_value, len);
  278         panel->backlight_pin = dts_value[0];
  279 
  280         return (0);
  281 }
  282 
  283 static int
  284 dcu_init(struct dcu_softc *sc)
  285 {
  286         struct panel_info *panel;
  287         int reg;
  288         int i;
  289 
  290         panel = sc->panel;
  291 
  292         /* Configure DCU */
  293         reg = ((sc->sc_info.fb_height) << DELTA_Y_S);
  294         reg |= (sc->sc_info.fb_width / 16);
  295         WRITE4(sc, DCU_DISP_SIZE, reg);
  296 
  297         reg = (panel->h_back_porch << BP_H_SHIFT);
  298         reg |= (panel->h_pulse_width << PW_H_SHIFT);
  299         reg |= (panel->h_front_porch << FP_H_SHIFT);
  300         WRITE4(sc, DCU_HSYN_PARA, reg);
  301 
  302         reg = (panel->v_back_porch << BP_V_SHIFT);
  303         reg |= (panel->v_pulse_width << PW_V_SHIFT);
  304         reg |= (panel->v_front_porch << FP_V_SHIFT);
  305         WRITE4(sc, DCU_VSYN_PARA, reg);
  306 
  307         WRITE4(sc, DCU_BGND, 0);
  308         WRITE4(sc, DCU_DIV_RATIO, panel->clk_div);
  309 
  310         reg = (INV_VS | INV_HS);
  311         WRITE4(sc, DCU_SYNPOL, reg);
  312 
  313         /* TODO: export to panel info */
  314         reg = (0x3 << LS_BF_VS_SHIFT);
  315         reg |= (0x78 << OUT_BUF_HIGH_SHIFT);
  316         reg |= (0 << OUT_BUF_LOW_SHIFT);
  317         WRITE4(sc, DCU_THRESHOLD, reg);
  318 
  319         /* Mask all the interrupts */
  320         WRITE4(sc, DCU_INT_MASK, 0xffffffff);
  321 
  322         /* Reset all layers */
  323         for (i = 0; i < NUM_LAYERS; i++) {
  324                 WRITE4(sc, DCU_CTRLDESCLn_1(i), 0x0);
  325                 WRITE4(sc, DCU_CTRLDESCLn_2(i), 0x0);
  326                 WRITE4(sc, DCU_CTRLDESCLn_3(i), 0x0);
  327                 WRITE4(sc, DCU_CTRLDESCLn_4(i), 0x0);
  328                 WRITE4(sc, DCU_CTRLDESCLn_5(i), 0x0);
  329                 WRITE4(sc, DCU_CTRLDESCLn_6(i), 0x0);
  330                 WRITE4(sc, DCU_CTRLDESCLn_7(i), 0x0);
  331                 WRITE4(sc, DCU_CTRLDESCLn_8(i), 0x0);
  332                 WRITE4(sc, DCU_CTRLDESCLn_9(i), 0x0);
  333         }
  334 
  335         /* Setup first layer */
  336         reg = (sc->sc_info.fb_width | (sc->sc_info.fb_height << 16));
  337         WRITE4(sc, DCU_CTRLDESCLn_1(0), reg);
  338         WRITE4(sc, DCU_CTRLDESCLn_2(0), 0x0);
  339         WRITE4(sc, DCU_CTRLDESCLn_3(0), sc->sc_info.fb_pbase);
  340         reg = (BPP24 << BPP_SHIFT);
  341         reg |= EN_LAYER;
  342         reg |= (0xFF << TRANS_SHIFT); /* completely opaque */
  343         WRITE4(sc, DCU_CTRLDESCLn_4(0), reg);
  344         WRITE4(sc, DCU_CTRLDESCLn_5(0), 0xffffff);
  345         WRITE4(sc, DCU_CTRLDESCLn_6(0), 0x0);
  346         WRITE4(sc, DCU_CTRLDESCLn_7(0), 0x0);
  347         WRITE4(sc, DCU_CTRLDESCLn_8(0), 0x0);
  348         WRITE4(sc, DCU_CTRLDESCLn_9(0), 0x0);
  349 
  350         /* Enable DCU in normal mode */
  351         reg = READ4(sc, DCU_DCU_MODE);
  352         reg &= ~(DCU_MODE_M << DCU_MODE_S);
  353         reg |= (DCU_MODE_NORMAL << DCU_MODE_S);
  354         reg |= (RASTER_EN);
  355         WRITE4(sc, DCU_DCU_MODE, reg);
  356         WRITE4(sc, DCU_UPDATE_MODE, READREG);
  357 
  358         return (0);
  359 }
  360 
  361 static int
  362 dcu_attach(device_t dev)
  363 {
  364         struct panel_info panel;
  365         struct dcu_softc *sc;
  366         device_t gpio_dev;
  367         int err;
  368 
  369         sc = device_get_softc(dev);
  370         sc->dev = dev;
  371 
  372         if (bus_alloc_resources(dev, dcu_spec, sc->res)) {
  373                 device_printf(dev, "could not allocate resources\n");
  374                 return (ENXIO);
  375         }
  376 
  377         /* Memory interface */
  378         sc->bst = rman_get_bustag(sc->res[0]);
  379         sc->bsh = rman_get_bushandle(sc->res[0]);
  380 
  381         /* Setup interrupt handler */
  382         err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_BIO | INTR_MPSAFE,
  383             NULL, dcu_intr, sc, &sc->ih);
  384         if (err) {
  385                 device_printf(dev, "Unable to alloc interrupt resource.\n");
  386                 return (ENXIO);
  387         }
  388 
  389         if (get_panel_info(sc, &panel)) {
  390                 device_printf(dev, "Can't get panel info\n");
  391                 return (ENXIO);
  392         }
  393 
  394         sc->panel = &panel;
  395 
  396         /* Bypass timing control (used for raw lcd panels) */
  397         tcon_bypass();
  398 
  399         /* Get the GPIO device, we need this to give power to USB */
  400         gpio_dev = devclass_get_device(devclass_find("gpio"), 0);
  401         if (gpio_dev == NULL) {
  402                 device_printf(sc->dev, "Error: failed to get the GPIO dev\n");
  403                 return (1);
  404         }
  405 
  406         /* Turn on backlight */
  407         /* TODO: Use FlexTimer/PWM */
  408         GPIO_PIN_SETFLAGS(gpio_dev, panel.backlight_pin, GPIO_PIN_OUTPUT);
  409         GPIO_PIN_SET(gpio_dev, panel.backlight_pin, GPIO_PIN_HIGH);
  410 
  411         sc->sc_info.fb_width = panel.width;
  412         sc->sc_info.fb_height = panel.height;
  413         sc->sc_info.fb_stride = sc->sc_info.fb_width * 3;
  414         sc->sc_info.fb_bpp = sc->sc_info.fb_depth = 24;
  415         sc->sc_info.fb_size = sc->sc_info.fb_height * sc->sc_info.fb_stride;
  416         sc->sc_info.fb_vbase = (intptr_t)contigmalloc(sc->sc_info.fb_size,
  417             M_DEVBUF, M_ZERO, 0, ~0, PAGE_SIZE, 0);
  418         sc->sc_info.fb_pbase = (intptr_t)vtophys(sc->sc_info.fb_vbase);
  419 
  420 #if 0
  421         printf("%dx%d [%d]\n", sc->sc_info.fb_width, sc->sc_info.fb_height,
  422             sc->sc_info.fb_stride);
  423         printf("pbase == 0x%08x\n", sc->sc_info.fb_pbase);
  424 #endif
  425 
  426         memset((int8_t *)sc->sc_info.fb_vbase, 0x0, sc->sc_info.fb_size);
  427 
  428         dcu_init(sc);
  429 
  430         sc->sc_info.fb_name = device_get_nameunit(dev);
  431 
  432         /* Ask newbus to attach framebuffer device to me. */
  433         sc->sc_fbd = device_add_child(dev, "fbd", device_get_unit(dev));
  434         if (sc->sc_fbd == NULL)
  435                 device_printf(dev, "Can't attach fbd device\n");
  436 
  437         if (device_probe_and_attach(sc->sc_fbd) != 0) {
  438                 device_printf(sc->dev, "Failed to attach fbd device\n");
  439         }
  440 
  441         return (0);
  442 }
  443 
  444 static struct fb_info *
  445 dcu4_fb_getinfo(device_t dev)
  446 {
  447         struct dcu_softc *sc = device_get_softc(dev);
  448 
  449         return (&sc->sc_info);
  450 }
  451 
  452 static device_method_t dcu_methods[] = {
  453         DEVMETHOD(device_probe,         dcu_probe),
  454         DEVMETHOD(device_attach,        dcu_attach),
  455 
  456         /* Framebuffer service methods */
  457         DEVMETHOD(fb_getinfo,           dcu4_fb_getinfo),
  458         { 0, 0 }
  459 };
  460 
  461 static driver_t dcu_driver = {
  462         "fb",
  463         dcu_methods,
  464         sizeof(struct dcu_softc),
  465 };
  466 
  467 static devclass_t dcu_devclass;
  468 
  469 DRIVER_MODULE(fb, simplebus, dcu_driver, dcu_devclass, 0, 0);

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