Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/arm/freescale/vybrid/vf_nfc.c
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1 /*- 2 * Copyright (c) 2013 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * Vybrid Family NAND Flash Controller (NFC) 29 * Chapter 31, Vybrid Reference Manual, Rev. 5, 07/2013 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD: releng/11.0/sys/arm/freescale/vybrid/vf_nfc.c 281085 2015-04-04 21:34:26Z andrew $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/proc.h> 38 #include <sys/bus.h> 39 #include <sys/conf.h> 40 #include <sys/kernel.h> 41 #include <sys/module.h> 42 #include <sys/malloc.h> 43 #include <sys/rman.h> 44 #include <sys/lock.h> 45 #include <sys/mutex.h> 46 #include <sys/time.h> 47 48 #include <dev/ofw/ofw_bus.h> 49 #include <dev/ofw/ofw_bus_subr.h> 50 #include <dev/nand/nand.h> 51 #include <dev/nand/nandbus.h> 52 53 #include <machine/bus.h> 54 55 #include "nfc_if.h" 56 57 #include <arm/freescale/vybrid/vf_common.h> 58 59 enum addr_type { 60 ADDR_NONE, 61 ADDR_ID, 62 ADDR_ROW, 63 ADDR_ROWCOL 64 }; 65 66 struct fsl_nfc_fcm { 67 uint32_t addr_bits; 68 enum addr_type addr_type; 69 uint32_t col_addr_bits; 70 uint32_t row_addr_bits; 71 u_int read_ptr; 72 u_int addr_ptr; 73 u_int command; 74 u_int code; 75 }; 76 77 struct vf_nand_softc { 78 struct nand_softc nand_dev; 79 bus_space_handle_t bsh; 80 bus_space_tag_t bst; 81 struct resource *res[2]; 82 struct fsl_nfc_fcm fcm; 83 }; 84 85 static struct resource_spec nfc_spec[] = { 86 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 87 { SYS_RES_IRQ, 0, RF_ACTIVE }, 88 { -1, 0 } 89 }; 90 91 static int vf_nand_attach(device_t); 92 static int vf_nand_probe(device_t); 93 static int vf_nand_send_command(device_t, uint8_t); 94 static int vf_nand_send_address(device_t, uint8_t); 95 static int vf_nand_start_command(device_t); 96 static uint8_t vf_nand_read_byte(device_t); 97 static void vf_nand_read_buf(device_t, void *, uint32_t); 98 static void vf_nand_write_buf(device_t, void *, uint32_t); 99 static int vf_nand_select_cs(device_t, uint8_t); 100 static int vf_nand_read_rnb(device_t); 101 102 #define CMD_READ_PAGE 0x7EE0 103 #define CMD_PROG_PAGE 0x7FC0 104 #define CMD_PROG_PAGE_DMA 0xFFC8 105 #define CMD_ERASE 0x4EC0 106 #define CMD_READ_ID 0x4804 107 #define CMD_READ_STATUS 0x4068 108 #define CMD_RESET 0x4040 109 #define CMD_RANDOM_IN 0x7140 110 #define CMD_RANDOM_OUT 0x70E0 111 112 #define CMD_BYTE2_PROG_PAGE 0x10 113 #define CMD_BYTE2_PAGE_READ 0x30 114 #define CMD_BYTE2_ERASE 0xD0 115 116 #define NFC_CMD1 0x3F00 /* Flash command 1 */ 117 #define NFC_CMD2 0x3F04 /* Flash command 2 */ 118 #define NFC_CAR 0x3F08 /* Column address */ 119 #define NFC_RAR 0x3F0C /* Row address */ 120 #define NFC_RPT 0x3F10 /* Flash command repeat */ 121 #define NFC_RAI 0x3F14 /* Row address increment */ 122 #define NFC_SR1 0x3F18 /* Flash status 1 */ 123 #define NFC_SR2 0x3F1C /* Flash status 2 */ 124 #define NFC_DMA_CH1 0x3F20 /* DMA channel 1 address */ 125 #define NFC_DMACFG 0x3F24 /* DMA configuration */ 126 #define NFC_SWAP 0x3F28 /* Cach swap */ 127 #define NFC_SECSZ 0x3F2C /* Sector size */ 128 #define NFC_CFG 0x3F30 /* Flash configuration */ 129 #define NFC_DMA_CH2 0x3F34 /* DMA channel 2 address */ 130 #define NFC_ISR 0x3F38 /* Interrupt status */ 131 132 #define ECCMODE_SHIFT 17 133 #define AIAD_SHIFT 5 134 #define AIBN_SHIFT 4 135 #define PAGECOUNT_SHIFT 0 136 #define BITWIDTH_SHIFT 7 137 #define BITWIDTH8 0 138 #define BITWIDTH16 1 139 #define PAGECOUNT_MASK 0xf 140 141 #define CMD2_BYTE1_SHIFT 24 142 #define CMD2_CODE_SHIFT 8 143 #define CMD2_BUFNO_SHIFT 1 144 #define CMD2_START_SHIFT 0 145 146 static device_method_t vf_nand_methods[] = { 147 DEVMETHOD(device_probe, vf_nand_probe), 148 DEVMETHOD(device_attach, vf_nand_attach), 149 DEVMETHOD(nfc_start_command, vf_nand_start_command), 150 DEVMETHOD(nfc_send_command, vf_nand_send_command), 151 DEVMETHOD(nfc_send_address, vf_nand_send_address), 152 DEVMETHOD(nfc_read_byte, vf_nand_read_byte), 153 DEVMETHOD(nfc_read_buf, vf_nand_read_buf), 154 DEVMETHOD(nfc_write_buf, vf_nand_write_buf), 155 DEVMETHOD(nfc_select_cs, vf_nand_select_cs), 156 DEVMETHOD(nfc_read_rnb, vf_nand_read_rnb), 157 { 0, 0 }, 158 }; 159 160 static driver_t vf_nand_driver = { 161 "nand", 162 vf_nand_methods, 163 sizeof(struct vf_nand_softc), 164 }; 165 166 static devclass_t vf_nand_devclass; 167 DRIVER_MODULE(vf_nand, simplebus, vf_nand_driver, vf_nand_devclass, 0, 0); 168 169 static int 170 vf_nand_probe(device_t dev) 171 { 172 173 if (!ofw_bus_status_okay(dev)) 174 return (ENXIO); 175 176 if (!ofw_bus_is_compatible(dev, "fsl,mvf600-nand")) 177 return (ENXIO); 178 179 device_set_desc(dev, "Vybrid Family NAND controller"); 180 return (BUS_PROBE_DEFAULT); 181 } 182 183 static int 184 vf_nand_attach(device_t dev) 185 { 186 struct vf_nand_softc *sc; 187 int err; 188 int reg; 189 190 sc = device_get_softc(dev); 191 if (bus_alloc_resources(dev, nfc_spec, sc->res)) { 192 device_printf(dev, "could not allocate resources!\n"); 193 return (ENXIO); 194 } 195 196 sc->bst = rman_get_bustag(sc->res[0]); 197 sc->bsh = rman_get_bushandle(sc->res[0]); 198 199 /* Size in bytes of one elementary transfer unit */ 200 WRITE4(sc, NFC_SECSZ, 2048); 201 202 /* Flash mode width */ 203 reg = READ4(sc, NFC_CFG); 204 reg |= (BITWIDTH16 << BITWIDTH_SHIFT); 205 206 /* No correction, ECC bypass */ 207 reg &= ~(0x7 << ECCMODE_SHIFT); 208 209 /* Disable Auto-incrementing of flash row address */ 210 reg &= ~(0x1 << AIAD_SHIFT); 211 212 /* Disable Auto-incrementing of buffer numbers */ 213 reg &= ~(0x1 << AIBN_SHIFT); 214 215 /* 216 * Number of virtual pages (in one physical flash page) 217 * to be programmed or read, etc. 218 */ 219 reg &= ~(PAGECOUNT_MASK); 220 reg |= (1 << PAGECOUNT_SHIFT); 221 WRITE4(sc, NFC_CFG, reg); 222 223 nand_init(&sc->nand_dev, dev, NAND_ECC_NONE, 0, 0, NULL, NULL); 224 err = nandbus_create(dev); 225 return (err); 226 } 227 228 static int 229 vf_nand_start_command(device_t dev) 230 { 231 struct vf_nand_softc *sc; 232 struct fsl_nfc_fcm *fcm; 233 int reg; 234 235 sc = device_get_softc(dev); 236 fcm = &sc->fcm; 237 238 nand_debug(NDBG_DRV,"vf_nand: start command %x", fcm->command); 239 240 /* CMD2 */ 241 reg = READ4(sc, NFC_CMD2); 242 reg &= ~(0xff << CMD2_BYTE1_SHIFT); 243 reg |= (fcm->command << CMD2_BYTE1_SHIFT); 244 WRITE4(sc, NFC_CMD2, reg); 245 246 /* CMD1 */ 247 if ((fcm->command == NAND_CMD_READ) || 248 (fcm->command == NAND_CMD_PROG) || 249 (fcm->command == NAND_CMD_ERASE)) { 250 reg = READ4(sc, NFC_CMD1); 251 reg &= ~(0xff << 24); 252 253 if (fcm->command == NAND_CMD_READ) 254 reg |= (CMD_BYTE2_PAGE_READ << 24); 255 else if (fcm->command == NAND_CMD_PROG) 256 reg |= (CMD_BYTE2_PROG_PAGE << 24); 257 else if (fcm->command == NAND_CMD_ERASE) 258 reg |= (CMD_BYTE2_ERASE << 24); 259 260 WRITE4(sc, NFC_CMD1, reg); 261 } 262 263 /* We work with 1st buffer */ 264 reg = READ4(sc, NFC_CMD2); 265 reg &= ~(0xf << CMD2_BUFNO_SHIFT); 266 reg |= (0 << CMD2_BUFNO_SHIFT); 267 WRITE4(sc, NFC_CMD2, reg); 268 269 /* Cmd CODE */ 270 reg = READ4(sc, NFC_CMD2); 271 reg &= ~(0xffff << CMD2_CODE_SHIFT); 272 reg |= (fcm->code << CMD2_CODE_SHIFT); 273 WRITE4(sc, NFC_CMD2, reg); 274 275 /* Col */ 276 if (fcm->addr_type == ADDR_ROWCOL) { 277 reg = READ4(sc, NFC_CAR); 278 reg &= ~(0xffff); 279 reg |= fcm->col_addr_bits; 280 nand_debug(NDBG_DRV,"setting CAR to 0x%08x\n", reg); 281 WRITE4(sc, NFC_CAR, reg); 282 } 283 284 /* Row */ 285 reg = READ4(sc, NFC_RAR); 286 reg &= ~(0xffffff); 287 if (fcm->addr_type == ADDR_ID) 288 reg |= fcm->addr_bits; 289 else 290 reg |= fcm->row_addr_bits; 291 WRITE4(sc, NFC_RAR, reg); 292 293 /* Start */ 294 reg = READ4(sc, NFC_CMD2); 295 reg |= (1 << CMD2_START_SHIFT); 296 WRITE4(sc, NFC_CMD2, reg); 297 298 /* Wait command completion */ 299 while (READ4(sc, NFC_CMD2) & (1 << CMD2_START_SHIFT)) 300 ; 301 302 return (0); 303 } 304 305 static int 306 vf_nand_send_command(device_t dev, uint8_t command) 307 { 308 struct vf_nand_softc *sc; 309 struct fsl_nfc_fcm *fcm; 310 311 nand_debug(NDBG_DRV,"vf_nand: send command %x", command); 312 313 sc = device_get_softc(dev); 314 fcm = &sc->fcm; 315 316 if ((command == NAND_CMD_READ_END) || 317 (command == NAND_CMD_PROG_END) || 318 (command == NAND_CMD_ERASE_END)) { 319 return (0); 320 } 321 322 fcm->command = command; 323 324 fcm->code = 0; 325 fcm->read_ptr = 0; 326 fcm->addr_type = 0; 327 fcm->addr_bits = 0; 328 329 fcm->addr_ptr = 0; 330 fcm->col_addr_bits = 0; 331 fcm->row_addr_bits = 0; 332 333 switch (command) { 334 case NAND_CMD_READ: 335 fcm->code = CMD_READ_PAGE; 336 fcm->addr_type = ADDR_ROWCOL; 337 break; 338 case NAND_CMD_PROG: 339 fcm->code = CMD_PROG_PAGE; 340 fcm->addr_type = ADDR_ROWCOL; 341 break; 342 case NAND_CMD_PROG_END: 343 break; 344 case NAND_CMD_ERASE_END: 345 break; 346 case NAND_CMD_RESET: 347 fcm->code = CMD_RESET; 348 break; 349 case NAND_CMD_READ_ID: 350 fcm->code = CMD_READ_ID; 351 fcm->addr_type = ADDR_ID; 352 break; 353 case NAND_CMD_READ_PARAMETER: 354 fcm->code = CMD_READ_PAGE; 355 fcm->addr_type = ADDR_ID; 356 break; 357 case NAND_CMD_STATUS: 358 fcm->code = CMD_READ_STATUS; 359 break; 360 case NAND_CMD_ERASE: 361 fcm->code = CMD_ERASE; 362 fcm->addr_type = ADDR_ROW; 363 break; 364 default: 365 nand_debug(NDBG_DRV, "unknown command %d\n", command); 366 return (1); 367 } 368 369 return (0); 370 } 371 372 static int 373 vf_nand_send_address(device_t dev, uint8_t addr) 374 { 375 struct vf_nand_softc *sc; 376 struct fsl_nfc_fcm *fcm; 377 378 nand_debug(NDBG_DRV,"vf_nand: send address %x", addr); 379 sc = device_get_softc(dev); 380 fcm = &sc->fcm; 381 382 nand_debug(NDBG_DRV, "setting addr #%d to 0x%02x\n", fcm->addr_ptr, addr); 383 384 if (fcm->addr_type == ADDR_ID) { 385 fcm->addr_bits = addr; 386 } else if (fcm->addr_type == ADDR_ROWCOL) { 387 388 if (fcm->addr_ptr < 2) 389 fcm->col_addr_bits |= (addr << (fcm->addr_ptr * 8)); 390 else 391 fcm->row_addr_bits |= (addr << ((fcm->addr_ptr - 2) * 8)); 392 393 } else if (fcm->addr_type == ADDR_ROW) 394 fcm->row_addr_bits |= (addr << (fcm->addr_ptr * 8)); 395 396 fcm->addr_ptr += 1; 397 398 return (0); 399 } 400 401 static uint8_t 402 vf_nand_read_byte(device_t dev) 403 { 404 struct vf_nand_softc *sc; 405 struct fsl_nfc_fcm *fcm; 406 uint8_t data; 407 int sr1, sr2; 408 int b; 409 410 sc = device_get_softc(dev); 411 fcm = &sc->fcm; 412 413 sr1 = READ4(sc, NFC_SR1); 414 sr2 = READ4(sc, NFC_SR2); 415 416 data = 0; 417 if (fcm->addr_type == ADDR_ID) { 418 b = 32 - ((fcm->read_ptr + 1) * 8); 419 data = (sr1 >> b) & 0xff; 420 fcm->read_ptr++; 421 } else if (fcm->command == NAND_CMD_STATUS) { 422 data = sr2 & 0xff; 423 } 424 425 nand_debug(NDBG_DRV,"vf_nand: read %x", data); 426 return (data); 427 } 428 429 static void 430 vf_nand_read_buf(device_t dev, void* buf, uint32_t len) 431 { 432 struct vf_nand_softc *sc; 433 struct fsl_nfc_fcm *fcm; 434 uint16_t *tmp; 435 uint8_t *b; 436 int i; 437 438 b = (uint8_t*)buf; 439 sc = device_get_softc(dev); 440 fcm = &sc->fcm; 441 442 nand_debug(NDBG_DRV, "vf_nand: read_buf len %d", len); 443 444 if (fcm->command == NAND_CMD_READ_PARAMETER) { 445 tmp = malloc(len, M_DEVBUF, M_NOWAIT); 446 bus_read_region_2(sc->res[0], 0x0, tmp, len); 447 448 for (i = 0; i < len; i += 2) { 449 b[i] = tmp[i+1]; 450 b[i+1] = tmp[i]; 451 } 452 453 free(tmp, M_DEVBUF); 454 455 #ifdef NAND_DEBUG 456 for (i = 0; i < len; i++) { 457 if (!(i % 16)) 458 printf("%s", i == 0 ? "vf_nand:\n" : "\n"); 459 printf(" %x", b[i]); 460 if (i == len - 1) 461 printf("\n"); 462 } 463 #endif 464 465 } else { 466 467 for (i = 0; i < len; i++) { 468 b[i] = READ1(sc, i); 469 470 #ifdef NAND_DEBUG 471 if (!(i % 16)) 472 printf("%s", i == 0 ? "vf_nand:\n" : "\n"); 473 printf(" %x", b[i]); 474 if (i == len - 1) 475 printf("\n"); 476 #endif 477 } 478 479 } 480 } 481 482 static void 483 vf_nand_write_buf(device_t dev, void* buf, uint32_t len) 484 { 485 struct vf_nand_softc *sc; 486 struct fsl_nfc_fcm *fcm; 487 uint8_t *b; 488 int i; 489 490 b = (uint8_t*)buf; 491 sc = device_get_softc(dev); 492 fcm = &sc->fcm; 493 494 nand_debug(NDBG_DRV,"vf_nand: write_buf len %d", len); 495 496 for (i = 0; i < len; i++) { 497 WRITE1(sc, i, b[i]); 498 499 #ifdef NAND_DEBUG 500 if (!(i % 16)) 501 printf("%s", i == 0 ? "vf_nand:\n" : "\n"); 502 printf(" %x", b[i]); 503 if (i == len - 1) 504 printf("\n"); 505 #endif 506 507 } 508 } 509 510 static int 511 vf_nand_select_cs(device_t dev, uint8_t cs) 512 { 513 514 if (cs > 0) 515 return (ENODEV); 516 517 return (0); 518 } 519 520 static int 521 vf_nand_read_rnb(device_t dev) 522 { 523 524 /* no-op */ 525 return (0); /* ready */ 526 }
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