The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/freescale/vybrid/vf_spi.c

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    1 /*-
    2  * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  */
   26 
   27 /*
   28  * Vybrid Family Serial Peripheral Interface (SPI)
   29  * Chapter 47, Vybrid Reference Manual, Rev. 5, 07/2013
   30  */
   31 
   32 #include <sys/cdefs.h>
   33 __FBSDID("$FreeBSD: head/sys/arm/freescale/vybrid/vf_spi.c 310229 2016-12-18 14:54:20Z manu $");
   34 
   35 #include <sys/param.h>
   36 #include <sys/systm.h>
   37 #include <sys/bus.h>
   38 #include <sys/kernel.h>
   39 #include <sys/module.h>
   40 #include <sys/malloc.h>
   41 #include <sys/rman.h>
   42 #include <sys/timeet.h>
   43 #include <sys/timetc.h>
   44 #include <sys/watchdog.h>
   45 
   46 #include <dev/spibus/spi.h>
   47 #include <dev/spibus/spibusvar.h>
   48 
   49 #include "spibus_if.h"
   50 
   51 #include <dev/ofw/openfirm.h>
   52 #include <dev/ofw/ofw_bus.h>
   53 #include <dev/ofw/ofw_bus_subr.h>
   54 
   55 #include <machine/bus.h>
   56 #include <machine/cpu.h>
   57 #include <machine/intr.h>
   58 
   59 #include <arm/freescale/vybrid/vf_common.h>
   60 
   61 #define SPI_FIFO_SIZE   4
   62 
   63 #define SPI_MCR         0x00            /* Module Configuration */
   64 #define  MCR_MSTR       (1 << 31)       /* Master/Slave Mode Select */
   65 #define  MCR_CONT_SCKE  (1 << 30)       /* Continuous SCK Enable */
   66 #define  MCR_FRZ        (1 << 27)       /* Freeze */
   67 #define  MCR_PCSIS_S    16              /* Peripheral Chip Select */
   68 #define  MCR_PCSIS_M    0x3f
   69 #define  MCR_MDIS       (1 << 14)       /* Module Disable */
   70 #define  MCR_CLR_TXF    (1 << 11)       /* Clear TX FIFO */
   71 #define  MCR_CLR_RXF    (1 << 10)       /* Clear RX FIFO */
   72 #define  MCR_HALT       (1 << 0)        /* Starts and stops SPI transfers */
   73 #define SPI_TCR         0x08            /* Transfer Count */
   74 #define SPI_CTAR0       0x0C            /* Clock and Transfer Attributes */
   75 #define SPI_CTAR0_SLAVE 0x0C            /* Clock and Transfer Attributes */
   76 #define SPI_CTAR1       0x10            /* Clock and Transfer Attributes */
   77 #define SPI_CTAR2       0x14            /* Clock and Transfer Attributes */
   78 #define SPI_CTAR3       0x18            /* Clock and Transfer Attributes */
   79 #define  CTAR_FMSZ_M    0xf
   80 #define  CTAR_FMSZ_S    27              /* Frame Size */
   81 #define  CTAR_FMSZ_8    0x7             /* 8 bits */
   82 #define  CTAR_CPOL      (1 << 26)       /* Clock Polarity */
   83 #define  CTAR_CPHA      (1 << 25)       /* Clock Phase */
   84 #define  CTAR_LSBFE     (1 << 24)       /* Less significant bit first */
   85 #define  CTAR_PCSSCK_M  0x3
   86 #define  CTAR_PCSSCK_S  22              /* PCS to SCK Delay Prescaler */
   87 #define  CTAR_PBR_M     0x3
   88 #define  CTAR_PBR_S     16              /* Baud Rate Prescaler */
   89 #define  CTAR_PBR_7     0x3             /* Divide by 7 */
   90 #define  CTAR_CSSCK_M   0xf
   91 #define  CTAR_CSSCK_S   12              /* PCS to SCK Delay Scaler */
   92 #define  CTAR_BR_M      0xf
   93 #define  CTAR_BR_S      0               /* Baud Rate Scaler */
   94 #define SPI_SR          0x2C            /* Status Register */
   95 #define  SR_TCF         (1 << 31)       /* Transfer Complete Flag */
   96 #define  SR_EOQF        (1 << 28)       /* End of Queue Flag */
   97 #define  SR_TFFF        (1 << 25)       /* Transmit FIFO Fill Flag */
   98 #define  SR_RFDF        (1 << 17)       /* Receive FIFO Drain Flag */
   99 #define SPI_RSER        0x30            /* DMA/Interrupt Select */
  100 #define  RSER_EOQF_RE   (1 << 28)       /* Finished Request Enable */
  101 #define SPI_PUSHR       0x34            /* PUSH TX FIFO In Master Mode */
  102 #define  PUSHR_CONT     (1 << 31)       /* Continuous Peripheral CS */
  103 #define  PUSHR_EOQ      (1 << 27)       /* End Of Queue */
  104 #define  PUSHR_CTCNT    (1 << 26)       /* Clear Transfer Counter */
  105 #define  PUSHR_PCS_M    0x3f
  106 #define  PUSHR_PCS_S    16              /* Select PCS signals */
  107 
  108 #define SPI_PUSHR_SLAVE 0x34    /* PUSH TX FIFO Register In Slave Mode */
  109 #define SPI_POPR        0x38    /* POP RX FIFO Register */
  110 #define SPI_TXFR0       0x3C    /* Transmit FIFO Registers */
  111 #define SPI_TXFR1       0x40
  112 #define SPI_TXFR2       0x44
  113 #define SPI_TXFR3       0x48
  114 #define SPI_RXFR0       0x7C    /* Receive FIFO Registers */
  115 #define SPI_RXFR1       0x80
  116 #define SPI_RXFR2       0x84
  117 #define SPI_RXFR3       0x88
  118 
  119 struct spi_softc {
  120         struct resource         *res[2];
  121         bus_space_tag_t         bst;
  122         bus_space_handle_t      bsh;
  123         void                    *ih;
  124 };
  125 
  126 static struct resource_spec spi_spec[] = {
  127         { SYS_RES_MEMORY,       0,      RF_ACTIVE },
  128         { SYS_RES_IRQ,          0,      RF_ACTIVE },
  129         { -1, 0 }
  130 };
  131 
  132 static int
  133 spi_probe(device_t dev)
  134 {
  135 
  136         if (!ofw_bus_status_okay(dev))
  137                 return (ENXIO);
  138 
  139         if (!ofw_bus_is_compatible(dev, "fsl,mvf600-spi"))
  140                 return (ENXIO);
  141 
  142         device_set_desc(dev, "Vybrid Family Serial Peripheral Interface");
  143         return (BUS_PROBE_DEFAULT);
  144 }
  145 
  146 static int
  147 spi_attach(device_t dev)
  148 {
  149         struct spi_softc *sc;
  150         uint32_t reg;
  151 
  152         sc = device_get_softc(dev);
  153 
  154         if (bus_alloc_resources(dev, spi_spec, sc->res)) {
  155                 device_printf(dev, "could not allocate resources\n");
  156                 return (ENXIO);
  157         }
  158 
  159         /* Memory interface */
  160         sc->bst = rman_get_bustag(sc->res[0]);
  161         sc->bsh = rman_get_bushandle(sc->res[0]);
  162 
  163         reg = READ4(sc, SPI_MCR);
  164         reg |= MCR_MSTR;
  165         reg &= ~(MCR_CONT_SCKE | MCR_MDIS | MCR_FRZ);
  166         reg &= ~(MCR_PCSIS_M << MCR_PCSIS_S);
  167         reg |= (MCR_PCSIS_M << MCR_PCSIS_S);    /* PCS Active low */
  168         reg |= (MCR_CLR_TXF | MCR_CLR_RXF);
  169         WRITE4(sc, SPI_MCR, reg);
  170 
  171         reg = READ4(sc, SPI_RSER);
  172         reg |= RSER_EOQF_RE;
  173         WRITE4(sc, SPI_RSER, reg);
  174 
  175         reg = READ4(sc, SPI_MCR);
  176         reg &= ~MCR_HALT;
  177         WRITE4(sc, SPI_MCR, reg);
  178 
  179         reg = READ4(sc, SPI_CTAR0);
  180         reg &= ~(CTAR_FMSZ_M << CTAR_FMSZ_S);
  181         reg |= (CTAR_FMSZ_8 << CTAR_FMSZ_S);
  182         /*
  183          * TODO: calculate BR
  184          * SCK baud rate = ( fsys / PBR ) * (1 + DBR) / BR
  185          *
  186          * reg &= ~(CTAR_BR_M << CTAR_BR_S);
  187          */
  188         reg &= ~CTAR_CPOL; /* Polarity */
  189         reg |= CTAR_CPHA;
  190         /*
  191          * Set LSB (Less significant bit first)
  192          * must be used for some applications, e.g. some LCDs
  193          */
  194         reg |= CTAR_LSBFE;
  195         WRITE4(sc, SPI_CTAR0, reg);
  196 
  197         reg = READ4(sc, SPI_CTAR0);
  198         reg &= ~(CTAR_PBR_M << CTAR_PBR_S);
  199         reg |= (CTAR_PBR_7 << CTAR_PBR_S);
  200         WRITE4(sc, SPI_CTAR0, reg);
  201 
  202         device_add_child(dev, "spibus", 0);
  203         return (bus_generic_attach(dev));
  204 }
  205 
  206 static int
  207 spi_txrx(struct spi_softc *sc, uint8_t *out_buf,
  208     uint8_t *in_buf, int bufsz, int cs)
  209 {
  210         uint32_t reg, wreg;
  211         uint32_t txcnt;
  212         uint32_t i;
  213 
  214         txcnt = 0;
  215 
  216         for (i = 0; i < bufsz; i++) {
  217                 txcnt++;
  218                 wreg = out_buf[i];
  219                 wreg |= PUSHR_CONT;
  220                 wreg |= (cs << PUSHR_PCS_S);
  221                 if (i == 0)
  222                         wreg |= PUSHR_CTCNT;
  223                 if (i == (bufsz - 1) || txcnt == SPI_FIFO_SIZE)
  224                         wreg |= PUSHR_EOQ;
  225                 WRITE4(sc, SPI_PUSHR, wreg);
  226 
  227                 if (i == (bufsz - 1) || txcnt == SPI_FIFO_SIZE) {
  228                         txcnt = 0;
  229 
  230                         /* Wait last entry in a queue to be transmitted */
  231                         while((READ4(sc, SPI_SR) & SR_EOQF) == 0)
  232                                 continue;
  233 
  234                         reg = READ4(sc, SPI_SR);
  235                         reg |= (SR_TCF | SR_EOQF);
  236                         WRITE4(sc, SPI_SR, reg);
  237                 }
  238 
  239                 /* Wait until RX FIFO is empty */
  240                 while((READ4(sc, SPI_SR) & SR_RFDF) == 0)
  241                         continue;
  242 
  243                 in_buf[i] = READ1(sc, SPI_POPR);
  244         }
  245 
  246         return (0);
  247 }
  248 
  249 static int
  250 spi_transfer(device_t dev, device_t child, struct spi_command *cmd)
  251 {
  252         struct spi_softc *sc;
  253         uint32_t cs;
  254 
  255         sc = device_get_softc(dev);
  256 
  257         KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz,
  258             ("%s: TX/RX command sizes should be equal", __func__));
  259         KASSERT(cmd->tx_data_sz == cmd->rx_data_sz,
  260             ("%s: TX/RX data sizes should be equal", __func__));
  261 
  262         /* get the proper chip select */
  263         spibus_get_cs(child, &cs);
  264 
  265         cs &= ~SPIBUS_CS_HIGH;
  266 
  267         /* Command */
  268         spi_txrx(sc, cmd->tx_cmd, cmd->rx_cmd, cmd->tx_cmd_sz, cs);
  269 
  270         /* Data */
  271         spi_txrx(sc, cmd->tx_data, cmd->rx_data, cmd->tx_data_sz, cs);
  272 
  273         return (0);
  274 }
  275 
  276 static device_method_t spi_methods[] = {
  277         /* Device interface */
  278         DEVMETHOD(device_probe,         spi_probe),
  279         DEVMETHOD(device_attach,        spi_attach),
  280         /* SPI interface */
  281         DEVMETHOD(spibus_transfer,      spi_transfer),
  282         { 0, 0 }
  283 };
  284 
  285 static driver_t spi_driver = {
  286         "spi",
  287         spi_methods,
  288         sizeof(struct spi_softc),
  289 };
  290 
  291 static devclass_t spi_devclass;
  292 
  293 DRIVER_MODULE(spi, simplebus, spi_driver, spi_devclass, 0, 0);

Cache object: b3095685a5d5207fb0a7a028ca0165cd


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