The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

FreeBSD/Linux Kernel Cross Reference
sys/arm/include/armreg.h

Version: -  FREEBSD  -  FREEBSD-13-STABLE  -  FREEBSD-13-0  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  l41  -  OPENBSD  -  linux-2.6  -  MK84  -  PLAN9  -  xnu-8792 
SearchContext: -  none  -  3  -  10 

    1 /*      $NetBSD: armreg.h,v 1.28 2003/10/31 16:30:15 scw Exp $  */
    2 
    3 /*-
    4  * Copyright (c) 1998, 2001 Ben Harris
    5  * Copyright (c) 1994-1996 Mark Brinicombe.
    6  * Copyright (c) 1994 Brini.
    7  * All rights reserved.
    8  *
    9  * This code is derived from software written for Brini by Mark Brinicombe
   10  *
   11  * Redistribution and use in source and binary forms, with or without
   12  * modification, are permitted provided that the following conditions
   13  * are met:
   14  * 1. Redistributions of source code must retain the above copyright
   15  *    notice, this list of conditions and the following disclaimer.
   16  * 2. Redistributions in binary form must reproduce the above copyright
   17  *    notice, this list of conditions and the following disclaimer in the
   18  *    documentation and/or other materials provided with the distribution.
   19  * 3. All advertising materials mentioning features or use of this software
   20  *    must display the following acknowledgement:
   21  *      This product includes software developed by Brini.
   22  * 4. The name of the company nor the name of the author may be used to
   23  *    endorse or promote products derived from this software without specific
   24  *    prior written permission.
   25  *
   26  * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
   27  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
   28  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   29  * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
   30  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
   31  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
   32  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   36  * SUCH DAMAGE.
   37  *
   38  * $FreeBSD: releng/6.1/sys/arm/include/armreg.h 139735 2005-01-05 21:58:49Z imp $
   39  */
   40 
   41 #ifndef MACHINE_ARMREG_H
   42 #define MACHINE_ARMREG_H
   43 #define INSN_SIZE       4
   44 #define INSN_COND_MASK  0xf0000000      /* Condition mask */
   45 #define PSR_MODE        0x0000001f      /* mode mask */
   46 #define PSR_USR26_MODE  0x00000000
   47 #define PSR_FIQ26_MODE  0x00000001
   48 #define PSR_IRQ26_MODE  0x00000002
   49 #define PSR_SVC26_MODE  0x00000003
   50 #define PSR_USR32_MODE  0x00000010
   51 #define PSR_FIQ32_MODE  0x00000011
   52 #define PSR_IRQ32_MODE  0x00000012
   53 #define PSR_SVC32_MODE  0x00000013
   54 #define PSR_ABT32_MODE  0x00000017
   55 #define PSR_UND32_MODE  0x0000001b
   56 #define PSR_SYS32_MODE  0x0000001f
   57 #define PSR_32_MODE     0x00000010
   58 #define PSR_FLAGS       0xf0000000    /* flags */
   59 
   60 #define PSR_C_bit (1 << 29)       /* carry */
   61 
   62 /* The high-order byte is always the implementor */
   63 #define CPU_ID_IMPLEMENTOR_MASK 0xff000000
   64 #define CPU_ID_ARM_LTD          0x41000000 /* 'A' */
   65 #define CPU_ID_DEC              0x44000000 /* 'D' */
   66 #define CPU_ID_INTEL            0x69000000 /* 'i' */
   67 #define CPU_ID_TI               0x54000000 /* 'T' */
   68 
   69 /* How to decide what format the CPUID is in. */
   70 #define CPU_ID_ISOLD(x)         (((x) & 0x0000f000) == 0x00000000)
   71 #define CPU_ID_IS7(x)           (((x) & 0x0000f000) == 0x00007000)
   72 #define CPU_ID_ISNEW(x)         (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x))
   73 
   74 /* On ARM3 and ARM6, this byte holds the foundry ID. */
   75 #define CPU_ID_FOUNDRY_MASK     0x00ff0000
   76 #define CPU_ID_FOUNDRY_VLSI     0x00560000
   77 
   78 /* On ARM7 it holds the architecture and variant (sub-model) */
   79 #define CPU_ID_7ARCH_MASK       0x00800000
   80 #define CPU_ID_7ARCH_V3         0x00000000
   81 #define CPU_ID_7ARCH_V4T        0x00800000
   82 #define CPU_ID_7VARIANT_MASK    0x007f0000
   83 
   84 /* On more recent ARMs, it does the same, but in a different format */
   85 #define CPU_ID_ARCH_MASK        0x000f0000
   86 #define CPU_ID_ARCH_V3          0x00000000
   87 #define CPU_ID_ARCH_V4          0x00010000
   88 #define CPU_ID_ARCH_V4T         0x00020000
   89 #define CPU_ID_ARCH_V5          0x00030000
   90 #define CPU_ID_ARCH_V5T         0x00040000
   91 #define CPU_ID_ARCH_V5TE        0x00050000
   92 #define CPU_ID_VARIANT_MASK     0x00f00000
   93 
   94 /* Next three nybbles are part number */
   95 #define CPU_ID_PARTNO_MASK      0x0000fff0
   96 
   97 /* Intel XScale has sub fields in part number */
   98 #define CPU_ID_XSCALE_COREGEN_MASK      0x0000e000 /* core generation */
   99 #define CPU_ID_XSCALE_COREREV_MASK      0x00001c00 /* core revision */
  100 #define CPU_ID_XSCALE_PRODUCT_MASK      0x000003f0 /* product number */
  101 
  102 /* And finally, the revision number. */
  103 #define CPU_ID_REVISION_MASK    0x0000000f
  104 
  105 /* Individual CPUs are probably best IDed by everything but the revision. */
  106 #define CPU_ID_CPU_MASK         0xfffffff0
  107 
  108 /* Fake CPU IDs for ARMs without CP15 */
  109 #define CPU_ID_ARM2             0x41560200
  110 #define CPU_ID_ARM250           0x41560250
  111 
  112 /* Pre-ARM7 CPUs -- [15:12] == 0 */
  113 #define CPU_ID_ARM3             0x41560300
  114 #define CPU_ID_ARM600           0x41560600
  115 #define CPU_ID_ARM610           0x41560610
  116 #define CPU_ID_ARM620           0x41560620
  117 
  118 /* ARM7 CPUs -- [15:12] == 7 */
  119 #define CPU_ID_ARM700           0x41007000 /* XXX This is a guess. */
  120 #define CPU_ID_ARM710           0x41007100
  121 #define CPU_ID_ARM7500          0x41027100 /* XXX This is a guess. */
  122 #define CPU_ID_ARM710A          0x41047100 /* inc ARM7100 */
  123 #define CPU_ID_ARM7500FE        0x41077100
  124 #define CPU_ID_ARM710T          0x41807100
  125 #define CPU_ID_ARM720T          0x41807200
  126 #define CPU_ID_ARM740T8K        0x41807400 /* XXX no MMU, 8KB cache */
  127 #define CPU_ID_ARM740T4K        0x41817400 /* XXX no MMU, 4KB cache */
  128 
  129 /* Post-ARM7 CPUs */
  130 #define CPU_ID_ARM810           0x41018100
  131 #define CPU_ID_ARM920T          0x41129200
  132 #define CPU_ID_ARM922T          0x41029220
  133 #define CPU_ID_ARM940T          0x41029400 /* XXX no MMU */
  134 #define CPU_ID_ARM946ES         0x41049460 /* XXX no MMU */
  135 #define CPU_ID_ARM966ES         0x41049660 /* XXX no MMU */
  136 #define CPU_ID_ARM966ESR1       0x41059660 /* XXX no MMU */
  137 #define CPU_ID_ARM1020E         0x4115a200 /* (AKA arm10 rev 1) */
  138 #define CPU_ID_ARM1022ES        0x4105a220
  139 #define CPU_ID_SA110            0x4401a100
  140 #define CPU_ID_SA1100           0x4401a110
  141 #define CPU_ID_TI925T           0x54029250
  142 #define CPU_ID_SA1110           0x6901b110
  143 #define CPU_ID_IXP1200          0x6901c120
  144 #define CPU_ID_80200            0x69052000
  145 #define CPU_ID_PXA250           0x69052100 /* sans core revision */
  146 #define CPU_ID_PXA210           0x69052120
  147 #define CPU_ID_PXA250A          0x69052100 /* 1st version Core */
  148 #define CPU_ID_PXA210A          0x69052120 /* 1st version Core */
  149 #define CPU_ID_PXA250B          0x69052900 /* 3rd version Core */
  150 #define CPU_ID_PXA210B          0x69052920 /* 3rd version Core */
  151 #define CPU_ID_PXA250C          0x69052d00 /* 4th version Core */
  152 #define CPU_ID_PXA210C          0x69052d20 /* 4th version Core */
  153 #define CPU_ID_80321_400        0x69052420
  154 #define CPU_ID_80321_600        0x69052430
  155 #define CPU_ID_80321_400_B0     0x69052c20
  156 #define CPU_ID_80321_600_B0     0x69052c30
  157 #define CPU_ID_IXP425_533       0x690541c0
  158 #define CPU_ID_IXP425_400       0x690541d0
  159 #define CPU_ID_IXP425_266       0x690541f0
  160 
  161 /* ARM3-specific coprocessor 15 registers */
  162 #define ARM3_CP15_FLUSH         1
  163 #define ARM3_CP15_CONTROL       2
  164 #define ARM3_CP15_CACHEABLE     3
  165 #define ARM3_CP15_UPDATEABLE    4
  166 #define ARM3_CP15_DISRUPTIVE    5       
  167 
  168 /* ARM3 Control register bits */
  169 #define ARM3_CTL_CACHE_ON       0x00000001
  170 #define ARM3_CTL_SHARED         0x00000002
  171 #define ARM3_CTL_MONITOR        0x00000004
  172 
  173 /*
  174  * Post-ARM3 CP15 registers:
  175  *
  176  *      1       Control register
  177  *
  178  *      2       Translation Table Base
  179  *
  180  *      3       Domain Access Control
  181  *
  182  *      4       Reserved
  183  *
  184  *      5       Fault Status
  185  *
  186  *      6       Fault Address
  187  *
  188  *      7       Cache/write-buffer Control
  189  *
  190  *      8       TLB Control
  191  *
  192  *      9       Cache Lockdown
  193  *
  194  *      10      TLB Lockdown
  195  *
  196  *      11      Reserved
  197  *
  198  *      12      Reserved
  199  *
  200  *      13      Process ID (for FCSE)
  201  *
  202  *      14      Reserved
  203  *
  204  *      15      Implementation Dependent
  205  */
  206 
  207 /* Some of the definitions below need cleaning up for V3/V4 architectures */
  208 
  209 /* CPU control register (CP15 register 1) */
  210 #define CPU_CONTROL_MMU_ENABLE  0x00000001 /* M: MMU/Protection unit enable */
  211 #define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */
  212 #define CPU_CONTROL_DC_ENABLE   0x00000004 /* C: IDC/DC enable */
  213 #define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */
  214 #define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */
  215 #define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */
  216 #define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */
  217 #define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */
  218 #define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */
  219 #define CPU_CONTROL_ROM_ENABLE  0x00000200 /* R: ROM protection bit */
  220 #define CPU_CONTROL_CPCLK       0x00000400 /* F: Implementation defined */
  221 #define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */
  222 #define CPU_CONTROL_IC_ENABLE   0x00001000 /* I: IC enable */
  223 #define CPU_CONTROL_VECRELOC    0x00002000 /* V: Vector relocation */
  224 #define CPU_CONTROL_ROUNDROBIN  0x00004000 /* RR: Predictable replacement */
  225 #define CPU_CONTROL_V4COMPAT    0x00008000 /* L4: ARMv4 compat LDR R15 etc */
  226 
  227 #define CPU_CONTROL_IDC_ENABLE  CPU_CONTROL_DC_ENABLE
  228 
  229 /* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */
  230 #define XSCALE_AUXCTL_K         0x00000001 /* dis. write buffer coalescing */
  231 #define XSCALE_AUXCTL_P         0x00000002 /* ECC protect page table access */
  232 #define XSCALE_AUXCTL_MD_WB_RA  0x00000000 /* mini-D$ wb, read-allocate */
  233 #define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */
  234 #define XSCALE_AUXCTL_MD_WT     0x00000020 /* mini-D$ wt, read-allocate */
  235 #define XSCALE_AUXCTL_MD_MASK   0x00000030
  236 
  237 /* Cache type register definitions */
  238 #define CPU_CT_ISIZE(x)         ((x) & 0xfff)           /* I$ info */
  239 #define CPU_CT_DSIZE(x)         (((x) >> 12) & 0xfff)   /* D$ info */
  240 #define CPU_CT_S                (1U << 24)              /* split cache */
  241 #define CPU_CT_CTYPE(x)         (((x) >> 25) & 0xf)     /* cache type */
  242 
  243 #define CPU_CT_CTYPE_WT         0       /* write-through */
  244 #define CPU_CT_CTYPE_WB1        1       /* write-back, clean w/ read */
  245 #define CPU_CT_CTYPE_WB2        2       /* w/b, clean w/ cp15,7 */
  246 #define CPU_CT_CTYPE_WB6        6       /* w/b, cp15,7, lockdown fmt A */
  247 #define CPU_CT_CTYPE_WB7        7       /* w/b, cp15,7, lockdown fmt B */
  248 
  249 #define CPU_CT_xSIZE_LEN(x)     ((x) & 0x3)             /* line size */
  250 #define CPU_CT_xSIZE_M          (1U << 2)               /* multiplier */
  251 #define CPU_CT_xSIZE_ASSOC(x)   (((x) >> 3) & 0x7)      /* associativity */
  252 #define CPU_CT_xSIZE_SIZE(x)    (((x) >> 6) & 0x7)      /* size */
  253 
  254 /* Fault status register definitions */
  255 
  256 #define FAULT_TYPE_MASK 0x0f
  257 #define FAULT_USER      0x10
  258 
  259 #define FAULT_WRTBUF_0  0x00 /* Vector Exception */
  260 #define FAULT_WRTBUF_1  0x02 /* Terminal Exception */
  261 #define FAULT_BUSERR_0  0x04 /* External Abort on Linefetch -- Section */
  262 #define FAULT_BUSERR_1  0x06 /* External Abort on Linefetch -- Page */
  263 #define FAULT_BUSERR_2  0x08 /* External Abort on Non-linefetch -- Section */
  264 #define FAULT_BUSERR_3  0x0a /* External Abort on Non-linefetch -- Page */
  265 #define FAULT_BUSTRNL1  0x0c /* External abort on Translation -- Level 1 */
  266 #define FAULT_BUSTRNL2  0x0e /* External abort on Translation -- Level 2 */
  267 #define FAULT_ALIGN_0   0x01 /* Alignment */
  268 #define FAULT_ALIGN_1   0x03 /* Alignment */
  269 #define FAULT_TRANS_S   0x05 /* Translation -- Section */
  270 #define FAULT_TRANS_P   0x07 /* Translation -- Page */
  271 #define FAULT_DOMAIN_S  0x09 /* Domain -- Section */
  272 #define FAULT_DOMAIN_P  0x0b /* Domain -- Page */
  273 #define FAULT_PERM_S    0x0d /* Permission -- Section */
  274 #define FAULT_PERM_P    0x0f /* Permission -- Page */
  275 
  276 #define FAULT_IMPRECISE 0x400   /* Imprecise exception (XSCALE) */
  277 
  278 /*
  279  * Address of the vector page, low and high versions.
  280  */
  281 #define ARM_VECTORS_LOW         0x00000000U
  282 #define ARM_VECTORS_HIGH        0xffff0000U
  283 
  284 /*
  285  * ARM Instructions
  286  *
  287  *       3 3 2 2 2                              
  288  *       1 0 9 8 7                                                     0
  289  *      +-------+-------------------------------------------------------+
  290  *      | cond  |              instruction dependant                    |
  291  *      |c c c c|                                                       |
  292  *      +-------+-------------------------------------------------------+
  293  */
  294 
  295 #define INSN_SIZE               4               /* Always 4 bytes */
  296 #define INSN_COND_MASK          0xf0000000      /* Condition mask */
  297 #define INSN_COND_AL            0xe0000000      /* Always condition */
  298 
  299 #endif /* !MACHINE_ARMREG_H */

Cache object: cf220f4d240125ef3b9cb7831bce4c12


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]


This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.