Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/arm/include/asmacros.h
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1 /* $NetBSD: frame.h,v 1.6 2003/10/05 19:44:58 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 1994-1997 Mark Brinicombe. 5 * Copyright (c) 1994 Brini. 6 * All rights reserved. 7 * 8 * This code is derived from software written for Brini by Mark Brinicombe 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Brini. 21 * 4. The name of the company nor the name of the author may be used to 22 * endorse or promote products derived from this software without specific 23 * prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * $FreeBSD$ 38 */ 39 40 #ifndef _MACHINE_ASMACROS_H_ 41 #define _MACHINE_ASMACROS_H_ 42 43 #ifdef _KERNEL 44 45 #ifdef LOCORE 46 47 /* 48 * ASM macros for pushing and pulling trapframes from the stack 49 * 50 * These macros are used to handle the irqframe and trapframe structures 51 * defined above. 52 */ 53 54 /* 55 * PUSHFRAME - macro to push a trap frame on the stack in the current mode 56 * Since the current mode is used, the SVC lr field is not defined. 57 * 58 * NOTE: r13 and r14 are stored separately as a work around for the 59 * SA110 rev 2 STM^ bug 60 */ 61 62 #define PUSHFRAME \ 63 str lr, [sp, #-4]!; /* Push the return address */ \ 64 sub sp, sp, #(4*17); /* Adjust the stack pointer */ \ 65 stmia sp, {r0-r12}; /* Push the user mode registers */ \ 66 add r0, sp, #(4*13); /* Adjust the stack pointer */ \ 67 stmia r0, {r13-r14}^; /* Push the user mode registers */ \ 68 mov r0, r0; /* NOP for previous instruction */ \ 69 mrs r0, spsr_all; /* Put the SPSR on the stack */ \ 70 str r0, [sp, #-4]!; \ 71 ldr r0, =ARM_RAS_START; \ 72 mov r1, #0; \ 73 str r1, [r0]; \ 74 mov r1, #0xffffffff; \ 75 str r1, [r0, #4]; 76 77 /* 78 * PULLFRAME - macro to pull a trap frame from the stack in the current mode 79 * Since the current mode is used, the SVC lr field is ignored. 80 */ 81 82 #define PULLFRAME \ 83 ldr r0, [sp], #0x0004; /* Get the SPSR from stack */ \ 84 msr spsr_all, r0; \ 85 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 86 mov r0, r0; /* NOP for previous instruction */ \ 87 add sp, sp, #(4*17); /* Adjust the stack pointer */ \ 88 ldr lr, [sp], #0x0004; /* Pull the return address */ 89 90 /* 91 * PUSHFRAMEINSVC - macro to push a trap frame on the stack in SVC32 mode 92 * This should only be used if the processor is not currently in SVC32 93 * mode. The processor mode is switched to SVC mode and the trap frame is 94 * stored. The SVC lr field is used to store the previous value of 95 * lr in SVC mode. 96 * 97 * NOTE: r13 and r14 are stored separately as a work around for the 98 * SA110 rev 2 STM^ bug 99 */ 100 101 #define PUSHFRAMEINSVC \ 102 stmdb sp, {r0-r3}; /* Save 4 registers */ \ 103 mov r0, lr; /* Save xxx32 r14 */ \ 104 mov r1, sp; /* Save xxx32 sp */ \ 105 mrs r3, spsr; /* Save xxx32 spsr */ \ 106 mrs r2, cpsr; /* Get the CPSR */ \ 107 bic r2, r2, #(PSR_MODE); /* Fix for SVC mode */ \ 108 orr r2, r2, #(PSR_SVC32_MODE); \ 109 msr cpsr_c, r2; /* Punch into SVC mode */ \ 110 mov r2, sp; /* Save SVC sp */ \ 111 str r0, [sp, #-4]!; /* Push return address */ \ 112 str lr, [sp, #-4]!; /* Push SVC lr */ \ 113 str r2, [sp, #-4]!; /* Push SVC sp */ \ 114 msr spsr_all, r3; /* Restore correct spsr */ \ 115 ldmdb r1, {r0-r3}; /* Restore 4 regs from xxx mode */ \ 116 sub sp, sp, #(4*15); /* Adjust the stack pointer */ \ 117 stmia sp, {r0-r12}; /* Push the user mode registers */ \ 118 add r0, sp, #(4*13); /* Adjust the stack pointer */ \ 119 stmia r0, {r13-r14}^; /* Push the user mode registers */ \ 120 mov r0, r0; /* NOP for previous instruction */ \ 121 ldr r5, =ARM_RAS_START; /* Check if there's any RAS */ \ 122 ldr r4, [r5, #4]; /* reset it to point at the */ \ 123 cmp r4, #0xffffffff; /* end of memory if necessary; */ \ 124 movne r1, #0xffffffff; /* leave value in r4 for later */ \ 125 strne r1, [r5, #4]; /* comparision against PC. */ \ 126 ldr r3, [r5]; /* Retrieve global RAS_START */ \ 127 cmp r3, #0; /* and reset it if non-zero. */ \ 128 movne r1, #0; /* If non-zero RAS_START and */ \ 129 strne r1, [r5]; /* PC was lower than RAS_END, */ \ 130 ldrne r1, [r0, #16]; /* adjust the saved PC so that */ \ 131 cmpne r4, r1; /* execution later resumes at */ \ 132 strhi r3, [r0, #16]; /* the RAS_START location. */ \ 133 mrs r0, spsr_all; \ 134 str r0, [sp, #-4]! 135 136 /* 137 * PULLFRAMEFROMSVCANDEXIT - macro to pull a trap frame from the stack 138 * in SVC32 mode and restore the saved processor mode and PC. 139 * This should be used when the SVC lr register needs to be restored on 140 * exit. 141 */ 142 143 #define PULLFRAMEFROMSVCANDEXIT \ 144 ldr r0, [sp], #0x0004; /* Get the SPSR from stack */ \ 145 msr spsr_all, r0; /* restore SPSR */ \ 146 ldmia sp, {r0-r14}^; /* Restore registers (usr mode) */ \ 147 mov r0, r0; /* NOP for previous instruction */ \ 148 add sp, sp, #(4*15); /* Adjust the stack pointer */ \ 149 ldmia sp, {sp, lr, pc}^ /* Restore lr and exit */ 150 151 #define DATA(name) \ 152 .data ; \ 153 _ALIGN_DATA ; \ 154 .globl name ; \ 155 .type name, %object ; \ 156 name: 157 158 #define EMPTY 159 160 161 #define DO_AST \ 162 ldr r0, [sp] /* Get the SPSR from stack */ ;\ 163 mrs r4, cpsr /* save CPSR */ ;\ 164 orr r1, r4, #(I32_bit|F32_bit) ;\ 165 msr cpsr_c, r1 /* Disable interrupts */ ;\ 166 and r0, r0, #(PSR_MODE) /* Returning to USR mode? */ ;\ 167 teq r0, #(PSR_USR32_MODE) ;\ 168 bne 2f /* Nope, get out now */ ;\ 169 bic r4, r4, #(I32_bit|F32_bit) ;\ 170 1: ldr r5, .Lcurthread ;\ 171 ldr r5, [r5] ;\ 172 ldr r1, [r5, #(TD_FLAGS)] ;\ 173 and r1, r1, #(TDF_ASTPENDING|TDF_NEEDRESCHED) ;\ 174 teq r1, #0x00000000 ;\ 175 beq 2f /* Nope. Just bail */ ;\ 176 msr cpsr_c, r4 /* Restore interrupts */ ;\ 177 mov r0, sp ;\ 178 bl _C_LABEL(ast) /* ast(frame) */ ;\ 179 orr r0, r4, #(I32_bit|F32_bit) ;\ 180 msr cpsr_c, r0 ;\ 181 b 1b ;\ 182 2: 183 184 185 #define AST_LOCALS ;\ 186 .Lcurthread: ;\ 187 .word _C_LABEL(__pcpu) + PC_CURTHREAD 188 189 #endif /* LOCORE */ 190 191 #endif /* _KERNEL */ 192 193 #endif /* !_MACHINE_ASMACROS_H_ */
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