atomic-v4.h

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    1 /* $NetBSD: atomic.h,v 1.1 2002/10/19 12:22:34 bsh Exp $ */
    2 
    3 /*-
    4  * Copyright (C) 2003-2004 Olivier Houchard
    5  * Copyright (C) 1994-1997 Mark Brinicombe
    6  * Copyright (C) 1994 Brini
    7  * All rights reserved.
    8  *
    9  * This code is derived from software written for Brini by Mark Brinicombe
   10  *
   11  * Redistribution and use in source and binary forms, with or without
   12  * modification, are permitted provided that the following conditions
   13  * are met:
   14  * 1. Redistributions of source code must retain the above copyright
   15  *    notice, this list of conditions and the following disclaimer.
   16  * 2. Redistributions in binary form must reproduce the above copyright
   17  *    notice, this list of conditions and the following disclaimer in the
   18  *    documentation and/or other materials provided with the distribution.
   19  * 3. All advertising materials mentioning features or use of this software
   20  *    must display the following acknowledgement:
   21  *      This product includes software developed by Brini.
   22  * 4. The name of Brini may not be used to endorse or promote products
   23  *    derived from this software without specific prior written permission.
   24  *
   25  * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR
   26  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   27  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   28  * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
   29  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
   30  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
   31  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
   32  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
   33  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
   34  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   35  *
   36  * $FreeBSD$
   37  */
   38 
   39 #ifndef _MACHINE_ATOMIC_V4_H_
   40 #define _MACHINE_ATOMIC_V4_H_
   41 
   42 #ifndef _MACHINE_ATOMIC_H_
   43 #error Do not include this file directly, use <machine/atomic.h>
   44 #endif
   45 
   46 #if __ARM_ARCH <= 5
   47 #define isb()  __asm __volatile("mcr p15, 0, %0, c7, c5, 4" : : "r" (0) : "memory")
   48 #define dsb()  __asm __volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0) : "memory")
   49 #define dmb()  dsb()
   50 #else
   51 #error Only use this file with ARMv5 and earlier
   52 #endif
   53 
   54 #define mb()   dmb()
   55 #define wmb()  dmb()
   56 #define rmb()  dmb()
   57 
   58 #if defined(__clang_major__) && __clang_major__ >= 12
   59 #pragma clang diagnostic push
   60 #pragma clang diagnostic ignored "-Wcompound-token-split-by-macro"
   61 #endif
   62 
   63 #define __with_interrupts_disabled(expr) \
   64         do {                                            \
   65                 u_int cpsr_save, tmp;                   \
   66                                                         \
   67                 __asm __volatile(                       \
   68                         "mrs  %0, cpsr;"                \
   69                         "orr  %1, %0, %2;"              \
   70                         "msr  cpsr_fsxc, %1;"           \
   71                         : "=r" (cpsr_save), "=r" (tmp)  \
   72                         : "I" (PSR_I | PSR_F)           \
   73                         : "cc" );               \
   74                 (expr);                         \
   75                  __asm __volatile(              \
   76                         "msr  cpsr_fsxc, %0"    \
   77                         : /* no output */       \
   78                         : "r" (cpsr_save)       \
   79                         : "cc" );               \
   80         } while(0)
   81 
   82 static __inline uint32_t
   83 __swp(uint32_t val, volatile uint32_t *ptr)
   84 {
   85         __asm __volatile("swp   %0, %2, [%3]"
   86             : "=&r" (val), "=m" (*ptr)
   87             : "r" (val), "r" (ptr), "m" (*ptr)
   88             : "memory");
   89         return (val);
   90 }
   91 
   92 
   93 #ifdef _KERNEL
   94 #define ARM_HAVE_ATOMIC64
   95 
   96 static __inline void
   97 atomic_add_32(volatile u_int32_t *p, u_int32_t val)
   98 {
   99         __with_interrupts_disabled(*p += val);
  100 }
  101 
  102 static __inline void
  103 atomic_add_64(volatile u_int64_t *p, u_int64_t val)
  104 {
  105         __with_interrupts_disabled(*p += val);
  106 }
  107 
  108 static __inline void
  109 atomic_clear_32(volatile uint32_t *address, uint32_t clearmask)
  110 {
  111         __with_interrupts_disabled(*address &= ~clearmask);
  112 }
  113 
  114 static __inline void
  115 atomic_clear_64(volatile uint64_t *address, uint64_t clearmask)
  116 {
  117         __with_interrupts_disabled(*address &= ~clearmask);
  118 }
  119 
  120 static __inline int
  121 atomic_fcmpset_8(volatile uint8_t *p, volatile uint8_t *cmpval, volatile uint8_t newval)
  122 {
  123         int ret;
  124 
  125         __with_interrupts_disabled(
  126          {
  127                 ret = *p;
  128                 if (*p == *cmpval) {
  129                         *p = newval;
  130                         ret = 1;
  131                 } else {
  132                         *cmpval = *p;
  133                         ret = 0;
  134                 }
  135         });
  136         return (ret);
  137 }
  138 static __inline int
  139 atomic_fcmpset_16(volatile uint16_t *p, volatile uint16_t *cmpval, volatile uint16_t newval)
  140 {
  141         int ret;
  142 
  143         __with_interrupts_disabled(
  144          {
  145                 ret = *p;
  146                 if (*p == *cmpval) {
  147                         *p = newval;
  148                         ret = 1;
  149                 } else {
  150                         *cmpval = *p;
  151                         ret = 0;
  152                 }
  153         });
  154         return (ret);
  155 }
  156 
  157 static __inline int
  158 atomic_fcmpset_32(volatile u_int32_t *p, volatile u_int32_t *cmpval, volatile u_int32_t newval)
  159 {
  160         int ret;
  161 
  162         __with_interrupts_disabled(
  163          {
  164                 ret = *p;
  165                 if (*p == *cmpval) {
  166                         *p = newval;
  167                         ret = 1;
  168                 } else {
  169                         *cmpval = *p;
  170                         ret = 0;
  171                 }
  172         });
  173         return (ret);
  174 }
  175 
  176 static __inline int
  177 atomic_fcmpset_64(volatile u_int64_t *p, volatile u_int64_t *cmpval, volatile u_int64_t newval)
  178 {
  179         int ret;
  180 
  181         __with_interrupts_disabled(
  182          {
  183                 if (*p == *cmpval) {
  184                         *p = newval;
  185                         ret = 1;
  186                 } else {
  187                         *cmpval = *p;
  188                         ret = 0;
  189                 }
  190         });
  191         return (ret);
  192 }
  193 
  194 static __inline int
  195 atomic_cmpset_8(volatile uint8_t *p, volatile uint8_t cmpval, volatile uint8_t newval)
  196 {
  197         int ret;
  198 
  199         __with_interrupts_disabled(
  200          {
  201                 if (*p == cmpval) {
  202                         *p = newval;
  203                         ret = 1;
  204                 } else {
  205                         ret = 0;
  206                 }
  207         });
  208         return (ret);
  209 }
  210 
  211 static __inline int
  212 atomic_cmpset_16(volatile uint16_t *p, volatile uint16_t cmpval, volatile uint16_t newval)
  213 {
  214         int ret;
  215 
  216         __with_interrupts_disabled(
  217          {
  218                 if (*p == cmpval) {
  219                         *p = newval;
  220                         ret = 1;
  221                 } else {
  222                         ret = 0;
  223                 }
  224         });
  225         return (ret);
  226 }
  227 
  228 static __inline int
  229 atomic_cmpset_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval)
  230 {
  231         int ret;
  232 
  233         __with_interrupts_disabled(
  234          {
  235                 if (*p == cmpval) {
  236                         *p = newval;
  237                         ret = 1;
  238                 } else {
  239                         ret = 0;
  240                 }
  241         });
  242         return (ret);
  243 }
  244 
  245 static __inline int
  246 atomic_cmpset_64(volatile u_int64_t *p, volatile u_int64_t cmpval, volatile u_int64_t newval)
  247 {
  248         int ret;
  249 
  250         __with_interrupts_disabled(
  251          {
  252                 if (*p == cmpval) {
  253                         *p = newval;
  254                         ret = 1;
  255                 } else {
  256                         ret = 0;
  257                 }
  258         });
  259         return (ret);
  260 }
  261 
  262 
  263 static __inline uint32_t
  264 atomic_fetchadd_32(volatile uint32_t *p, uint32_t v)
  265 {
  266         uint32_t value;
  267 
  268         __with_interrupts_disabled(
  269         {
  270                 value = *p;
  271                 *p += v;
  272         });
  273         return (value);
  274 }
  275 
  276 static __inline uint64_t
  277 atomic_fetchadd_64(volatile uint64_t *p, uint64_t v)
  278 {
  279         uint64_t value;
  280 
  281         __with_interrupts_disabled(
  282         {
  283                 value = *p;
  284                 *p += v;
  285         });
  286         return (value);
  287 }
  288 
  289 static __inline uint64_t
  290 atomic_load_64(volatile uint64_t *p)
  291 {
  292         uint64_t value;
  293 
  294         __with_interrupts_disabled(value = *p);
  295         return (value);
  296 }
  297 
  298 static __inline void
  299 atomic_set_32(volatile uint32_t *address, uint32_t setmask)
  300 {
  301         __with_interrupts_disabled(*address |= setmask);
  302 }
  303 
  304 static __inline void
  305 atomic_set_64(volatile uint64_t *address, uint64_t setmask)
  306 {
  307         __with_interrupts_disabled(*address |= setmask);
  308 }
  309 
  310 static __inline void
  311 atomic_store_64(volatile uint64_t *p, uint64_t value)
  312 {
  313         __with_interrupts_disabled(*p = value);
  314 }
  315 
  316 static __inline void
  317 atomic_subtract_32(volatile u_int32_t *p, u_int32_t val)
  318 {
  319         __with_interrupts_disabled(*p -= val);
  320 }
  321 
  322 static __inline void
  323 atomic_subtract_64(volatile u_int64_t *p, u_int64_t val)
  324 {
  325         __with_interrupts_disabled(*p -= val);
  326 }
  327 
  328 static __inline uint64_t
  329 atomic_swap_64(volatile uint64_t *p, uint64_t v)
  330 {
  331         uint64_t value;
  332 
  333         __with_interrupts_disabled(
  334         {
  335                 value = *p;
  336                 *p = v;
  337         });
  338         return (value);
  339 }
  340 
  341 #else /* !_KERNEL */
  342 
  343 static __inline void
  344 atomic_add_32(volatile u_int32_t *p, u_int32_t val)
  345 {
  346         int start, ras_start = ARM_RAS_START;
  347 
  348         __asm __volatile("1:\n"
  349             "adr        %1, 1b\n"
  350             "str        %1, [%0]\n"
  351             "adr        %1, 2f\n"
  352             "str        %1, [%0, #4]\n"
  353             "ldr        %1, [%2]\n"
  354             "add        %1, %1, %3\n"
  355             "str        %1, [%2]\n"
  356             "2:\n"
  357             "mov        %1, #0\n"
  358             "str        %1, [%0]\n"
  359             "mov        %1, #0xffffffff\n"
  360             "str        %1, [%0, #4]\n"
  361             : "+r" (ras_start), "=r" (start), "+r" (p), "+r" (val)
  362             : : "memory");
  363 }
  364 
  365 static __inline void
  366 atomic_clear_32(volatile uint32_t *address, uint32_t clearmask)
  367 {
  368         int start, ras_start = ARM_RAS_START;
  369 
  370         __asm __volatile("1:\n"
  371             "adr        %1, 1b\n"
  372             "str        %1, [%0]\n"
  373             "adr        %1, 2f\n"
  374             "str        %1, [%0, #4]\n"
  375             "ldr        %1, [%2]\n"
  376             "bic        %1, %1, %3\n"
  377             "str        %1, [%2]\n"
  378             "2:\n"
  379             "mov        %1, #0\n"
  380             "str        %1, [%0]\n"
  381             "mov        %1, #0xffffffff\n"
  382             "str        %1, [%0, #4]\n"
  383             : "+r" (ras_start), "=r" (start), "+r" (address), "+r" (clearmask)
  384             : : "memory");
  385 
  386 }
  387 
  388 static __inline int
  389 atomic_cmpset_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval)
  390 {
  391         int done, ras_start = ARM_RAS_START;
  392 
  393         __asm __volatile("1:\n"
  394             "adr        %1, 1b\n"
  395             "str        %1, [%0]\n"
  396             "adr        %1, 2f\n"
  397             "str        %1, [%0, #4]\n"
  398             "ldr        %1, [%2]\n"
  399             "cmp        %1, %3\n"
  400             "streq      %4, [%2]\n"
  401             "2:\n"
  402             "mov        %1, #0\n"
  403             "str        %1, [%0]\n"
  404             "mov        %1, #0xffffffff\n"
  405             "str        %1, [%0, #4]\n"
  406             "moveq      %1, #1\n"
  407             "movne      %1, #0\n"
  408             : "+r" (ras_start), "=r" (done)
  409             ,"+r" (p), "+r" (cmpval), "+r" (newval) : : "cc", "memory");
  410         return (done);
  411 }
  412 
  413 static __inline int
  414 atomic_fcmpset_32(volatile u_int32_t *p, volatile u_int32_t *cmpval, volatile u_int32_t newval)
  415 {
  416         int done, oldval, ras_start = ARM_RAS_START;
  417 
  418         __asm __volatile("1:\n"
  419             "adr        %1, 1b\n"
  420             "str        %1, [%0]\n"
  421             "adr        %1, 2f\n"
  422             "str        %1, [%0, #4]\n"
  423             "ldr        %1, [%2]\n"
  424             "ldr        %5, [%3]\n"
  425             "cmp        %1, %5\n"
  426             "streq      %4, [%2]\n"
  427             "2:\n"
  428             "mov        %5, #0\n"
  429             "str        %5, [%0]\n"
  430             "mov        %5, #0xffffffff\n"
  431             "str        %5, [%0, #4]\n"
  432             "strne      %1, [%3]\n"
  433             "moveq      %1, #1\n"
  434             "movne      %1, #0\n"
  435             : "+r" (ras_start), "=r" (done) ,"+r" (p)
  436             , "+r" (cmpval), "+r" (newval), "+r" (oldval) : : "cc", "memory");
  437         return (done);
  438 }
  439 
  440 static __inline uint32_t
  441 atomic_fetchadd_32(volatile uint32_t *p, uint32_t v)
  442 {
  443         uint32_t start, tmp, ras_start = ARM_RAS_START;
  444 
  445         __asm __volatile("1:\n"
  446             "adr        %1, 1b\n"
  447             "str        %1, [%0]\n"
  448             "adr        %1, 2f\n"
  449             "str        %1, [%0, #4]\n"
  450             "ldr        %1, [%3]\n"
  451             "mov        %2, %1\n"
  452             "add        %2, %2, %4\n"
  453             "str        %2, [%3]\n"
  454             "2:\n"
  455             "mov        %2, #0\n"
  456             "str        %2, [%0]\n"
  457             "mov        %2, #0xffffffff\n"
  458             "str        %2, [%0, #4]\n"
  459             : "+r" (ras_start), "=r" (start), "=r" (tmp), "+r" (p), "+r" (v)
  460             : : "memory");
  461         return (start);
  462 }
  463 
  464 static __inline void
  465 atomic_set_32(volatile uint32_t *address, uint32_t setmask)
  466 {
  467         int start, ras_start = ARM_RAS_START;
  468 
  469         __asm __volatile("1:\n"
  470             "adr        %1, 1b\n"
  471             "str        %1, [%0]\n"
  472             "adr        %1, 2f\n"
  473             "str        %1, [%0, #4]\n"
  474             "ldr        %1, [%2]\n"
  475             "orr        %1, %1, %3\n"
  476             "str        %1, [%2]\n"
  477             "2:\n"
  478             "mov        %1, #0\n"
  479             "str        %1, [%0]\n"
  480             "mov        %1, #0xffffffff\n"
  481             "str        %1, [%0, #4]\n"
  482 
  483             : "+r" (ras_start), "=r" (start), "+r" (address), "+r" (setmask)
  484             : : "memory");
  485 }
  486 
  487 static __inline void
  488 atomic_subtract_32(volatile u_int32_t *p, u_int32_t val)
  489 {
  490         int start, ras_start = ARM_RAS_START;
  491 
  492         __asm __volatile("1:\n"
  493             "adr        %1, 1b\n"
  494             "str        %1, [%0]\n"
  495             "adr        %1, 2f\n"
  496             "str        %1, [%0, #4]\n"
  497             "ldr        %1, [%2]\n"
  498             "sub        %1, %1, %3\n"
  499             "str        %1, [%2]\n"
  500             "2:\n"
  501             "mov        %1, #0\n"
  502             "str        %1, [%0]\n"
  503             "mov        %1, #0xffffffff\n"
  504             "str        %1, [%0, #4]\n"
  505 
  506             : "+r" (ras_start), "=r" (start), "+r" (p), "+r" (val)
  507             : : "memory");
  508 }
  509 
  510 #endif /* _KERNEL */
  511 
  512 static __inline uint32_t
  513 atomic_readandclear_32(volatile u_int32_t *p)
  514 {
  515 
  516         return (__swp(0, p));
  517 }
  518 
  519 static __inline uint32_t
  520 atomic_swap_32(volatile u_int32_t *p, u_int32_t v)
  521 {
  522 
  523         return (__swp(v, p));
  524 }
  525 
  526 #define atomic_fcmpset_rel_32   atomic_fcmpset_32
  527 #define atomic_fcmpset_acq_32   atomic_fcmpset_32
  528 #ifdef _KERNEL
  529 #define atomic_fcmpset_rel_8    atomic_fcmpset_8
  530 #define atomic_fcmpset_acq_8    atomic_fcmpset_8
  531 #define atomic_fcmpset_rel_16   atomic_fcmpset_16
  532 #define atomic_fcmpset_acq_16   atomic_fcmpset_16
  533 #define atomic_fcmpset_rel_64   atomic_fcmpset_64
  534 #define atomic_fcmpset_acq_64   atomic_fcmpset_64
  535 #endif
  536 #define atomic_fcmpset_acq_long atomic_fcmpset_long
  537 #define atomic_fcmpset_rel_long atomic_fcmpset_long
  538 #define atomic_cmpset_rel_32    atomic_cmpset_32
  539 #define atomic_cmpset_acq_32    atomic_cmpset_32
  540 #ifdef _KERNEL
  541 #define atomic_cmpset_rel_8     atomic_cmpset_8
  542 #define atomic_cmpset_acq_8     atomic_cmpset_8
  543 #define atomic_cmpset_rel_16    atomic_cmpset_16
  544 #define atomic_cmpset_acq_16    atomic_cmpset_16
  545 #define atomic_cmpset_rel_64    atomic_cmpset_64
  546 #define atomic_cmpset_acq_64    atomic_cmpset_64
  547 #endif
  548 #define atomic_set_rel_32       atomic_set_32
  549 #define atomic_set_acq_32       atomic_set_32
  550 #define atomic_clear_rel_32     atomic_clear_32
  551 #define atomic_clear_acq_32     atomic_clear_32
  552 #define atomic_add_rel_32       atomic_add_32
  553 #define atomic_add_acq_32       atomic_add_32
  554 #define atomic_subtract_rel_32  atomic_subtract_32
  555 #define atomic_subtract_acq_32  atomic_subtract_32
  556 #define atomic_store_rel_32     atomic_store_32
  557 #define atomic_store_rel_long   atomic_store_long
  558 #define atomic_store_rel_64     atomic_store_64
  559 #define atomic_load_acq_32      atomic_load_32
  560 #define atomic_load_acq_long    atomic_load_long
  561 #define atomic_add_acq_long             atomic_add_long
  562 #define atomic_add_rel_long             atomic_add_long
  563 #define atomic_subtract_acq_long        atomic_subtract_long
  564 #define atomic_subtract_rel_long        atomic_subtract_long
  565 #define atomic_clear_acq_long           atomic_clear_long
  566 #define atomic_clear_rel_long           atomic_clear_long
  567 #define atomic_set_acq_long             atomic_set_long
  568 #define atomic_set_rel_long             atomic_set_long
  569 #define atomic_cmpset_acq_long          atomic_cmpset_long
  570 #define atomic_cmpset_rel_long          atomic_cmpset_long
  571 #define atomic_load_acq_long            atomic_load_long
  572 #undef __with_interrupts_disabled
  573 
  574 #if defined(__clang_major__) && __clang_major__ >= 12
  575 #pragma clang diagnostic pop
  576 #endif
  577 
  578 static __inline void
  579 atomic_add_long(volatile u_long *p, u_long v)
  580 {
  581 
  582         atomic_add_32((volatile uint32_t *)p, v);
  583 }
  584 
  585 static __inline void
  586 atomic_clear_long(volatile u_long *p, u_long v)
  587 {
  588 
  589         atomic_clear_32((volatile uint32_t *)p, v);
  590 }
  591 
  592 static __inline int
  593 atomic_cmpset_long(volatile u_long *dst, u_long old, u_long newe)
  594 {
  595 
  596         return (atomic_cmpset_32((volatile uint32_t *)dst, old, newe));
  597 }
  598 
  599 static __inline u_long
  600 atomic_fcmpset_long(volatile u_long *dst, u_long *old, u_long newe)
  601 {
  602 
  603         return (atomic_fcmpset_32((volatile uint32_t *)dst,
  604             (uint32_t *)old, newe));
  605 }
  606 
  607 static __inline u_long
  608 atomic_fetchadd_long(volatile u_long *p, u_long v)
  609 {
  610 
  611         return (atomic_fetchadd_32((volatile uint32_t *)p, v));
  612 }
  613 
  614 static __inline void
  615 atomic_readandclear_long(volatile u_long *p)
  616 {
  617 
  618         atomic_readandclear_32((volatile uint32_t *)p);
  619 }
  620 
  621 static __inline void
  622 atomic_set_long(volatile u_long *p, u_long v)
  623 {
  624 
  625         atomic_set_32((volatile uint32_t *)p, v);
  626 }
  627 
  628 static __inline void
  629 atomic_subtract_long(volatile u_long *p, u_long v)
  630 {
  631 
  632         atomic_subtract_32((volatile uint32_t *)p, v);
  633 }
  634 
  635 /*
  636  * ARMv5 does not support SMP.  For both kernel and user modes, only a
  637  * compiler barrier is needed for fences, since CPU is always
  638  * self-consistent.
  639  */
  640 static __inline void
  641 atomic_thread_fence_acq(void)
  642 {
  643 
  644         __compiler_membar();
  645 }
  646 
  647 static __inline void
  648 atomic_thread_fence_rel(void)
  649 {
  650 
  651         __compiler_membar();
  652 }
  653 
  654 static __inline void
  655 atomic_thread_fence_acq_rel(void)
  656 {
  657 
  658         __compiler_membar();
  659 }
  660 
  661 static __inline void
  662 atomic_thread_fence_seq_cst(void)
  663 {
  664 
  665         __compiler_membar();
  666 }
  667 
  668 #endif /* _MACHINE_ATOMIC_H_ */
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FreeBSD/Linux Kernel Cross Reference sys/arm/include/atomic-v4.h

FreeBSD/Linux Kernel Cross Reference
sys/arm/include/atomic-v4.h
