1 /* $NetBSD: atomic.h,v 1.1 2002/10/19 12:22:34 bsh Exp $ */
2
3 /*-
4 * Copyright (C) 2003-2004 Olivier Houchard
5 * Copyright (C) 1994-1997 Mark Brinicombe
6 * Copyright (C) 1994 Brini
7 * All rights reserved.
8 *
9 * This code is derived from software written for Brini by Mark Brinicombe
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by Brini.
22 * 4. The name of Brini may not be used to endorse or promote products
23 * derived from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR
26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
31 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
33 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
34 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *
36 * $FreeBSD: releng/6.0/sys/arm/include/atomic.h 151008 2005-10-06 18:12:06Z jhb $
37 */
38
39 #ifndef _MACHINE_ATOMIC_H_
40 #define _MACHINE_ATOMIC_H_
41
42
43
44 #ifndef _LOCORE
45
46 #include <sys/types.h>
47
48 #ifndef I32_bit
49 #define I32_bit (1 << 7) /* IRQ disable */
50 #endif
51 #ifndef F32_bit
52 #define F32_bit (1 << 6) /* FIQ disable */
53 #endif
54
55 #define __with_interrupts_disabled(expr) \
56 do { \
57 u_int cpsr_save, tmp; \
58 \
59 __asm __volatile( \
60 "mrs %0, cpsr;" \
61 "orr %1, %0, %2;" \
62 "msr cpsr_all, %1;" \
63 : "=r" (cpsr_save), "=r" (tmp) \
64 : "I" (I32_bit) \
65 : "cc" ); \
66 (expr); \
67 __asm __volatile( \
68 "msr cpsr_all, %0" \
69 : /* no output */ \
70 : "r" (cpsr_save) \
71 : "cc" ); \
72 } while(0)
73
74 #define ARM_RAS_START 0xe0000004
75 #define ARM_RAS_END 0xe0000008
76
77 static __inline uint32_t
78 __swp(uint32_t val, volatile uint32_t *ptr)
79 {
80 __asm __volatile("swp %0, %2, [%3]"
81 : "=&r" (val), "=m" (*ptr)
82 : "r" (val) , "r" (ptr), "m" (*ptr)
83 : "memory");
84 return (val);
85 }
86
87
88 #ifdef _KERNEL
89 static __inline void
90 atomic_set_32(volatile uint32_t *address, uint32_t setmask)
91 {
92 __with_interrupts_disabled(*address |= setmask);
93 }
94
95 static __inline void
96 atomic_clear_32(volatile uint32_t *address, uint32_t clearmask)
97 {
98 __with_interrupts_disabled(*address &= ~clearmask);
99 }
100
101 static __inline u_int32_t
102 atomic_cmpset_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval)
103 {
104 int ret;
105
106 __with_interrupts_disabled(
107 {
108 if (*p == cmpval) {
109 *p = newval;
110 ret = 1;
111 } else {
112 ret = 0;
113 }
114 });
115 return (ret);
116 }
117
118 static __inline void
119 atomic_add_32(volatile u_int32_t *p, u_int32_t val)
120 {
121 __with_interrupts_disabled(*p += val);
122 }
123
124 static __inline void
125 atomic_subtract_32(volatile u_int32_t *p, u_int32_t val)
126 {
127 __with_interrupts_disabled(*p -= val);
128 }
129
130 static __inline uint32_t
131 atomic_fetchadd_32(volatile uint32_t *p, uint32_t v)
132 {
133 uint32_t value;
134
135 __with_interrupts_disabled(
136 {
137 value = *p;
138 *p += v;
139 });
140 return (value);
141 }
142
143 #else /* !_KERNEL */
144
145 static __inline u_int32_t
146 atomic_cmpset_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval)
147 {
148 register int done, ras_start;
149
150 __asm __volatile("1:\n"
151 "mov %0, #0xe0000008\n"
152 "adr %1, 2f\n"
153 "str %1, [%0]\n"
154 "adr %1, 1b\n"
155 "mov %0, #0xe0000004\n"
156 "str %1, [%0]\n"
157 "ldr %1, [%2]\n"
158 "cmp %1, %3\n"
159 "streq %4, [%2]\n"
160 "2:\n"
161 "mov %1, #0\n"
162 "str %1, [%0]\n"
163 "moveq %1, #1\n"
164 "movne %1, #0\n"
165 : "=r" (ras_start), "=r" (done)
166 ,"+r" (p), "+r" (cmpval), "+r" (newval));
167 return (done);
168 }
169
170 static __inline void
171 atomic_add_32(volatile u_int32_t *p, u_int32_t val)
172 {
173 int ras_start, start;
174
175 __asm __volatile("1:\n"
176 "mov %0, #0xe0000008\n"
177 "adr %1, 2f\n"
178 "str %1, [%0]\n"
179 "adr %1, 1b\n"
180 "mov %0, #0xe0000004\n"
181 "str %1, [%0]\n"
182 "ldr %1, [%2]\n"
183 "add %1, %1, %3\n"
184 "str %1, [%2]\n"
185 "2:\n"
186 "mov %1, #0\n"
187 "str %1, [%0]\n"
188 : "=r" (ras_start), "=r" (start), "+r" (p), "+r" (val));
189 }
190
191 static __inline void
192 atomic_subtract_32(volatile u_int32_t *p, u_int32_t val)
193 {
194 int ras_start, start;
195
196 __asm __volatile("1:\n"
197 "mov %0, #0xe0000008\n"
198 "adr %1, 2f\n"
199 "str %1, [%0]\n"
200 "adr %1, 1b\n"
201 "mov %0, #0xe0000004\n"
202 "str %1, [%0]\n"
203 "ldr %1, [%2]\n"
204 "sub %1, %1, %3\n"
205 "str %1, [%2]\n"
206 "2:\n"
207 "mov %1, #0\n"
208 "str %1, [%0]\n"
209
210 : "=r" (ras_start), "=r" (start), "+r" (p), "+r" (val));
211 }
212
213 static __inline void
214 atomic_set_32(volatile uint32_t *address, uint32_t setmask)
215 {
216 int ras_start, start;
217
218 __asm __volatile("1:\n"
219 "mov %0, #0xe0000008\n"
220 "adr %1, 2f\n"
221 "str %1, [%0]\n"
222 "adr %1, 1b\n"
223 "mov %0, #0xe0000004\n"
224 "str %1, [%0]\n"
225 "ldr %1, [%2]\n"
226 "orr %1, %1, %3\n"
227 "str %1, [%2]\n"
228 "2:\n"
229 "mov %1, #0\n"
230 "str %1, [%0]\n"
231
232 : "=r" (ras_start), "=r" (start), "+r" (address), "+r" (setmask));
233 }
234
235 static __inline void
236 atomic_clear_32(volatile uint32_t *address, uint32_t clearmask)
237 {
238 int ras_start, start;
239
240 __asm __volatile("1:\n"
241 "mov %0, #0xe0000008\n"
242 "adr %1, 2f\n"
243 "str %1, [%0]\n"
244 "adr %1, 1b\n"
245 "mov %0, #0xe0000004\n"
246 "str %1, [%0]\n"
247 "ldr %1, [%2]\n"
248 "bic %1, %1, %3\n"
249 "str %1, [%2]\n"
250 "2:\n"
251 "mov %1, #0\n"
252 "str %1, [%0]\n"
253 : "=r" (ras_start), "=r" (start), "+r" (address), "+r" (clearmask));
254
255 }
256
257 static __inline uint32_t
258 atomic_fetchadd_32(volatile uint32_t *p, uint32_t v)
259 {
260 uint32_t ras_start, start;
261
262 __asm __volatile("1:\n"
263 "mov %0, #0xe0000008\n"
264 "adr %1, 2f\n"
265 "str %1, [%0]\n"
266 "adr %1, 1b\n"
267 "mov %0, #0xe0000004\n"
268 "str %1, [%0]\n"
269 "ldr %1, %2\n"
270 "add %3, %1, %3\n"
271 "str %3, %2\n"
272 "2:\n"
273 "mov %3, #0\n"
274 "str %3, [%0]\n"
275 : "=r" (ras_start), "=r" (start), "=m" (*p), "+r" (v));
276 return (start);
277 }
278
279
280 #endif /* _KERNEL */
281
282 static __inline int
283 atomic_load_32(volatile uint32_t *v)
284 {
285
286 return (*v);
287 }
288
289 static __inline void
290 atomic_store_32(volatile uint32_t *dst, uint32_t src)
291 {
292 *dst = src;
293 }
294
295 static __inline uint32_t
296 atomic_readandclear_32(volatile u_int32_t *p)
297 {
298
299 return (__swp(0, p));
300 }
301
302 #undef __with_interrupts_disabled
303
304 #endif /* _LOCORE */
305
306
307 #define atomic_set_rel_int atomic_set_32
308 #define atomic_set_int atomic_set_32
309 #define atomic_readandclear_int atomic_readandclear_32
310 #define atomic_clear_int atomic_clear_32
311 #define atomic_subtract_int atomic_subtract_32
312 #define atomic_subtract_rel_int atomic_subtract_32
313 #define atomic_subtract_acq_int atomic_subtract_32
314 #define atomic_add_int atomic_add_32
315 #define atomic_add_rel_int atomic_add_32
316 #define atomic_add_acq_int atomic_add_32
317 #define atomic_cmpset_int atomic_cmpset_32
318 #define atomic_cmpset_rel_int atomic_cmpset_32
319 #define atomic_cmpset_rel_ptr atomic_cmpset_ptr
320 #define atomic_cmpset_acq_int atomic_cmpset_32
321 #define atomic_cmpset_acq_ptr atomic_cmpset_ptr
322 #define atomic_store_rel_ptr atomic_store_ptr
323 #define atomic_store_rel_int atomic_store_32
324 #define atomic_cmpset_rel_32 atomic_cmpset_32
325 #define atomic_cmpset_rel_ptr atomic_cmpset_ptr
326 #define atomic_load_acq_int atomic_load_32
327 #define atomic_clear_ptr atomic_clear_32
328 #define atomic_store_ptr atomic_store_32
329 #define atomic_cmpset_ptr atomic_cmpset_32
330 #define atomic_set_ptr atomic_set_32
331 #define atomic_fetchadd_int atomic_fetchadd_32
332
333 #endif /* _MACHINE_ATOMIC_H_ */
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