The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/include/atomic.h

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    1 /* $NetBSD: atomic.h,v 1.1 2002/10/19 12:22:34 bsh Exp $ */
    2 
    3 /*-
    4  * Copyright (C) 2003-2004 Olivier Houchard
    5  * Copyright (C) 1994-1997 Mark Brinicombe
    6  * Copyright (C) 1994 Brini
    7  * All rights reserved.
    8  *
    9  * This code is derived from software written for Brini by Mark Brinicombe
   10  *
   11  * Redistribution and use in source and binary forms, with or without
   12  * modification, are permitted provided that the following conditions
   13  * are met:
   14  * 1. Redistributions of source code must retain the above copyright
   15  *    notice, this list of conditions and the following disclaimer.
   16  * 2. Redistributions in binary form must reproduce the above copyright
   17  *    notice, this list of conditions and the following disclaimer in the
   18  *    documentation and/or other materials provided with the distribution.
   19  * 3. All advertising materials mentioning features or use of this software
   20  *    must display the following acknowledgement:
   21  *      This product includes software developed by Brini.
   22  * 4. The name of Brini may not be used to endorse or promote products
   23  *    derived from this software without specific prior written permission.
   24  *
   25  * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR
   26  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   27  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   28  * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
   29  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
   30  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
   31  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
   32  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
   33  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
   34  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   35  *
   36  * $FreeBSD$
   37  */
   38 
   39 #ifndef _MACHINE_ATOMIC_H_
   40 #define _MACHINE_ATOMIC_H_
   41 
   42 
   43 
   44 #ifndef _LOCORE
   45 
   46 #include <sys/types.h>
   47 
   48 #ifndef I32_bit
   49 #define I32_bit (1 << 7)        /* IRQ disable */
   50 #endif
   51 #ifndef F32_bit
   52 #define F32_bit (1 << 6)        /* FIQ disable */
   53 #endif
   54 
   55 #define __with_interrupts_disabled(expr) \
   56         do {                                            \
   57                 u_int cpsr_save, tmp;                   \
   58                                                         \
   59                 __asm __volatile(                       \
   60                         "mrs  %0, cpsr;"                \
   61                         "orr  %1, %0, %2;"              \
   62                         "msr  cpsr_all, %1;"            \
   63                         : "=r" (cpsr_save), "=r" (tmp)  \
   64                         : "I" (I32_bit | F32_bit)               \
   65                         : "cc" );               \
   66                 (expr);                         \
   67                  __asm __volatile(              \
   68                         "msr  cpsr_all, %0"     \
   69                         : /* no output */       \
   70                         : "r" (cpsr_save)       \
   71                         : "cc" );               \
   72         } while(0)
   73 
   74 #define ARM_RAS_START   0xe0000004
   75 #define ARM_RAS_END     0xe0000008
   76 
   77 static __inline uint32_t
   78 __swp(uint32_t val, volatile uint32_t *ptr)
   79 {
   80         __asm __volatile("swp   %0, %2, [%3]"
   81             : "=&r" (val), "=m" (*ptr)
   82             : "r" (val), "r" (ptr), "m" (*ptr)
   83             : "memory");
   84         return (val);
   85 }
   86 
   87 
   88 #ifdef _KERNEL
   89 static __inline void
   90 atomic_set_32(volatile uint32_t *address, uint32_t setmask)
   91 {
   92         __with_interrupts_disabled(*address |= setmask);
   93 }
   94 
   95 static __inline void
   96 atomic_clear_32(volatile uint32_t *address, uint32_t clearmask)
   97 {
   98         __with_interrupts_disabled(*address &= ~clearmask);
   99 }
  100 
  101 static __inline u_int32_t
  102 atomic_cmpset_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval)
  103 {
  104         int ret;
  105         
  106         __with_interrupts_disabled(
  107          {
  108                 if (*p == cmpval) {
  109                         *p = newval;
  110                         ret = 1;
  111                 } else {
  112                         ret = 0;
  113                 }
  114         });
  115         return (ret);
  116 }
  117 
  118 static __inline void
  119 atomic_add_32(volatile u_int32_t *p, u_int32_t val)
  120 {
  121         __with_interrupts_disabled(*p += val);
  122 }
  123 
  124 static __inline void
  125 atomic_subtract_32(volatile u_int32_t *p, u_int32_t val)
  126 {
  127         __with_interrupts_disabled(*p -= val);
  128 }
  129 
  130 static __inline uint32_t
  131 atomic_fetchadd_32(volatile uint32_t *p, uint32_t v)
  132 {
  133         uint32_t value;
  134 
  135         __with_interrupts_disabled(
  136         {
  137                 value = *p;
  138                 *p += v;
  139         });
  140         return (value);
  141 }
  142 
  143 #else /* !_KERNEL */
  144 
  145 static __inline u_int32_t
  146 atomic_cmpset_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval)
  147 {
  148         register int done, ras_start;
  149 
  150         __asm __volatile("1:\n"
  151             "adr        %1, 1b\n"
  152             "mov        %0, #0xe0000004\n"
  153             "str        %1, [%0]\n"
  154             "mov        %0, #0xe0000008\n"
  155             "adr        %1, 2f\n"
  156             "str        %1, [%0]\n"
  157             "ldr        %1, [%2]\n"
  158             "cmp        %1, %3\n"
  159             "streq      %4, [%2]\n"
  160             "2:\n"
  161             "mov        %1, #0\n"
  162             "mov        %0, #0xe0000004\n"
  163             "str        %1, [%0]\n"
  164             "mov        %1, #0xffffffff\n"
  165             "mov        %0, #0xe0000008\n"
  166             "str        %1, [%0]\n"
  167             "moveq      %1, #1\n"
  168             "movne      %1, #0\n"
  169             : "=r" (ras_start), "=r" (done)
  170             ,"+r" (p), "+r" (cmpval), "+r" (newval) : : "memory");
  171         return (done);
  172 }
  173 
  174 static __inline void
  175 atomic_add_32(volatile u_int32_t *p, u_int32_t val)
  176 {
  177         int ras_start, start;
  178 
  179         __asm __volatile("1:\n"
  180             "adr        %1, 1b\n"
  181             "mov        %0, #0xe0000004\n"
  182             "str        %1, [%0]\n"
  183             "mov        %0, #0xe0000008\n"
  184             "adr        %1, 2f\n"
  185             "str        %1, [%0]\n"
  186             "ldr        %1, [%2]\n"
  187             "add        %1, %1, %3\n"
  188             "str        %1, [%2]\n"
  189             "2:\n"
  190             "mov        %0, #0xe0000004\n"
  191             "mov        %1, #0\n"
  192             "str        %1, [%0]\n"
  193             "mov        %1, #0xffffffff\n"
  194             "mov        %0, #0xe0000008\n"
  195             "str        %1, [%0]\n"
  196             : "=r" (ras_start), "=r" (start), "+r" (p), "+r" (val)
  197             : : "memory");
  198 }
  199 
  200 static __inline void
  201 atomic_subtract_32(volatile u_int32_t *p, u_int32_t val)
  202 {
  203         int ras_start, start;
  204 
  205         __asm __volatile("1:\n"
  206             "adr        %1, 1b\n"
  207             "mov        %0, #0xe0000004\n"
  208             "str        %1, [%0]\n"
  209             "mov        %0, #0xe0000008\n"
  210             "adr        %1, 2f\n"
  211             "str        %1, [%0]\n"
  212             "ldr        %1, [%2]\n"
  213             "sub        %1, %1, %3\n"
  214             "str        %1, [%2]\n"
  215             "2:\n"
  216             "mov        %0, #0xe0000004\n"
  217             "mov        %1, #0\n"
  218             "str        %1, [%0]\n"
  219             "mov        %1, #0xffffffff\n"
  220             "mov        %0, #0xe0000008\n"
  221             "str        %1, [%0]\n"
  222 
  223             : "=r" (ras_start), "=r" (start), "+r" (p), "+r" (val)
  224             : : "memory");
  225 }
  226 
  227 static __inline void
  228 atomic_set_32(volatile uint32_t *address, uint32_t setmask)
  229 {
  230         int ras_start, start;
  231 
  232         __asm __volatile("1:\n"
  233             "adr        %1, 1b\n"
  234             "mov        %0, #0xe0000004\n"
  235             "str        %1, [%0]\n"
  236             "mov        %0, #0xe0000008\n"
  237             "adr        %1, 2f\n"
  238             "str        %1, [%0]\n"
  239             "ldr        %1, [%2]\n"
  240             "orr        %1, %1, %3\n"
  241             "str        %1, [%2]\n"
  242             "2:\n"
  243             "mov        %0, #0xe0000004\n"
  244             "mov        %1, #0\n"
  245             "str        %1, [%0]\n"
  246             "mov        %1, #0xffffffff\n"
  247             "mov        %0, #0xe0000008\n"
  248             "str        %1, [%0]\n"
  249 
  250             : "=r" (ras_start), "=r" (start), "+r" (address), "+r" (setmask)
  251             : : "memory");
  252 }
  253 
  254 static __inline void
  255 atomic_clear_32(volatile uint32_t *address, uint32_t clearmask)
  256 {
  257         int ras_start, start;
  258 
  259         __asm __volatile("1:\n"
  260             "adr        %1, 1b\n"
  261             "mov        %0, #0xe0000004\n"
  262             "str        %1, [%0]\n"
  263             "mov        %0, #0xe0000008\n"
  264             "adr        %1, 2f\n"
  265             "str        %1, [%0]\n"
  266             "ldr        %1, [%2]\n"
  267             "bic        %1, %1, %3\n"
  268             "str        %1, [%2]\n"
  269             "2:\n"
  270             "mov        %0, #0xe0000004\n"
  271             "mov        %1, #0\n"
  272             "str        %1, [%0]\n"
  273             "mov        %1, #0xffffffff\n"
  274             "mov        %0, #0xe0000008\n"
  275             "str        %1, [%0]\n"
  276             : "=r" (ras_start), "=r" (start), "+r" (address), "+r" (clearmask)
  277             : : "memory");
  278 
  279 }
  280 
  281 static __inline uint32_t
  282 atomic_fetchadd_32(volatile uint32_t *p, uint32_t v)
  283 {
  284         uint32_t ras_start, start;
  285 
  286         __asm __volatile("1:\n"
  287             "adr        %1, 1b\n"
  288             "mov        %0, #0xe0000004\n"
  289             "str        %1, [%0]\n"
  290             "mov        %0, #0xe0000008\n"
  291             "adr        %1, 2f\n"
  292             "str        %1, [%0]\n"
  293             "ldr        %1, [%2]\n"
  294             "add        %0, %1, %3\n"
  295             "str        %0, [%2]\n"
  296             "2:\n"
  297             "mov        %0, #0xe0000004\n"
  298             "mov        %3, #0\n"
  299             "str        %3, [%0]\n"
  300             "mov        %0, #0xe0000008\n"
  301             "mov        %3, #0xffffffff\n"
  302             "str        %3, [%0]\n"
  303             : "=r" (ras_start), "=r" (start), "+r" (p), "+r" (v)
  304             : : "memory");
  305         return (start);
  306 }
  307 
  308             
  309 #endif /* _KERNEL */
  310 
  311 static __inline int
  312 atomic_load_32(volatile uint32_t *v)
  313 {
  314 
  315         return (*v);
  316 }
  317 
  318 static __inline void
  319 atomic_store_32(volatile uint32_t *dst, uint32_t src)
  320 {
  321         *dst = src;
  322 }
  323 
  324 static __inline uint32_t
  325 atomic_readandclear_32(volatile u_int32_t *p)
  326 {
  327 
  328         return (__swp(0, p));
  329 }
  330 
  331 #undef __with_interrupts_disabled
  332 
  333 #endif /* _LOCORE */
  334 
  335 #define atomic_add_long(p, v) \
  336         atomic_add_32((volatile u_int *)(p), (u_int)(v))
  337 #define atomic_add_acq_long             atomic_add_long
  338 #define atomic_add_rel_long             atomic_add_long
  339 #define atomic_subtract_long(p, v) \
  340         atomic_subtract_32((volatile u_int *)(p), (u_int)(v))
  341 #define atomic_subtract_acq_long        atomic_subtract_long
  342 #define atomic_subtract_rel_long        atomic_subtract_long
  343 #define atomic_clear_long(p, v) \
  344         atomic_clear_32((volatile u_int *)(p), (u_int)(v))
  345 #define atomic_clear_acq_long           atomic_clear_long
  346 #define atomic_clear_rel_long           atomic_clear_long
  347 #define atomic_set_long(p, v) \
  348         atomic_set_32((volatile u_int *)(p), (u_int)(v))
  349 #define atomic_set_acq_long             atomic_set_long
  350 #define atomic_set_rel_long             atomic_set_long
  351 #define atomic_cmpset_long(dst, old, new) \
  352         atomic_cmpset_32((volatile u_int *)(dst), (u_int)(old), (u_int)(new))
  353 #define atomic_cmpset_acq_long          atomic_cmpset_long
  354 #define atomic_cmpset_rel_long          atomic_cmpset_long
  355 #define atomic_fetchadd_long(p, v) \
  356         atomic_fetchadd_32((volatile u_int *)(p), (u_int)(v))
  357 #define atomic_readandclear_long(p) \
  358         atomic_readandclear_long((volatile u_int *)(p))
  359 #define atomic_load_long(p) \
  360         atomic_load_32((volatile u_int *)(p))
  361 #define atomic_load_acq_long            atomic_load_long
  362 #define atomic_store_rel_long(p, v) \
  363         atomic_store_rel_32((volatile u_int *)(p), (u_int)(v))
  364 
  365 
  366 #define atomic_clear_ptr                atomic_clear_32
  367 #define atomic_set_ptr                  atomic_set_32
  368 #define atomic_cmpset_ptr               atomic_cmpset_32
  369 #define atomic_cmpset_rel_ptr           atomic_cmpset_ptr
  370 #define atomic_cmpset_acq_ptr           atomic_cmpset_ptr
  371 #define atomic_store_ptr                atomic_store_32
  372 #define atomic_store_rel_ptr            atomic_store_ptr
  373 
  374 #define atomic_add_int                  atomic_add_32
  375 #define atomic_add_acq_int              atomic_add_int
  376 #define atomic_add_rel_int              atomic_add_int
  377 #define atomic_subtract_int             atomic_subtract_32
  378 #define atomic_subtract_acq_int         atomic_subtract_int
  379 #define atomic_subtract_rel_int         atomic_subtract_int
  380 #define atomic_clear_int                atomic_clear_32
  381 #define atomic_clear_acq_int            atomic_clear_int
  382 #define atomic_clear_rel_int            atomic_clear_int
  383 #define atomic_set_int                  atomic_set_32
  384 #define atomic_set_acq_int              atomic_set_int
  385 #define atomic_set_rel_int              atomic_set_int
  386 #define atomic_cmpset_int               atomic_cmpset_32
  387 #define atomic_cmpset_acq_int           atomic_cmpset_int
  388 #define atomic_cmpset_rel_int           atomic_cmpset_int
  389 #define atomic_fetchadd_int             atomic_fetchadd_32
  390 #define atomic_readandclear_int         atomic_readandclear_32
  391 #define atomic_load_acq_int             atomic_load_32
  392 #define atomic_store_rel_int            atomic_store_32
  393 
  394 #define atomic_add_acq_32               atomic_add_32
  395 #define atomic_add_rel_32               atomic_add_32
  396 #define atomic_subtract_acq_32          atomic_subtract_32
  397 #define atomic_subtract_rel_32          atomic_subtract_32
  398 #define atomic_clear_acq_32             atomic_clear_32
  399 #define atomic_clear_rel_32             atomic_clear_32
  400 #define atomic_set_acq_32               atomic_set_32
  401 #define atomic_set_rel_32               atomic_set_32
  402 #define atomic_cmpset_acq_32            atomic_cmpset_32
  403 #define atomic_cmpset_rel_32            atomic_cmpset_32
  404 #define atomic_load_acq_32              atomic_load_32
  405 #define atomic_store_rel_32             atomic_store_32
  406 
  407 #endif /* _MACHINE_ATOMIC_H_ */

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