1 /* $NetBSD: cpuconf.h,v 1.8 2003/09/06 08:55:42 rearnsha Exp $ */
2
3 /*-
4 * Copyright (c) 2002 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
23 * written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 *
37 * $FreeBSD: src/sys/arm/include/cpuconf.h,v 1.12 2007/11/01 10:01:15 kevlo Exp $
38 *
39 */
40
41 #ifndef _MACHINE_CPUCONF_H_
42 #define _MACHINE_CPUCONF_H_
43
44 /*
45 * IF YOU CHANGE THIS FILE, MAKE SURE TO UPDATE THE DEFINITION OF
46 * "PMAP_NEEDS_PTE_SYNC" IN <arm/arm32/pmap.h> FOR THE CPU TYPE
47 * YOU ARE ADDING SUPPORT FOR.
48 */
49
50 /*
51 * Step 1: Count the number of CPU types configured into the kernel.
52 */
53 #define CPU_NTYPES (defined(CPU_ARM7TDMI) + \
54 defined(CPU_ARM8) + defined(CPU_ARM9) + \
55 defined(CPU_ARM9E) + \
56 defined(CPU_ARM10) + \
57 defined(CPU_ARM11) + \
58 defined(CPU_SA110) + defined(CPU_SA1100) + \
59 defined(CPU_SA1110) + \
60 defined(CPU_IXP12X0) + \
61 defined(CPU_XSCALE_80200) + \
62 defined(CPU_XSCALE_80321) + \
63 defined(CPU_XSCALE_PXA2X0) + \
64 defined(CPU_XSCALE_IXP425))
65
66 /*
67 * Step 2: Determine which ARM architecture versions are configured.
68 */
69 #if (defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \
70 defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \
71 defined(CPU_IXP12X0) || defined(CPU_XSCALE_IXP425))
72 #define ARM_ARCH_4 1
73 #else
74 #define ARM_ARCH_4 0
75 #endif
76
77 #if (defined(CPU_ARM9E) || defined(CPU_ARM10) || \
78 defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
79 defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) || \
80 defined(CPU_XSCALE_PXA2X0))
81 #define ARM_ARCH_5 1
82 #else
83 #define ARM_ARCH_5 0
84 #endif
85
86 #if defined(CPU_ARM11)
87 #define ARM_ARCH_6 1
88 #else
89 #define ARM_ARCH_6 0
90 #endif
91
92 #define ARM_NARCH (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6)
93 #if ARM_NARCH == 0 && !defined(KLD_MODULE) && defined(_KERNEL)
94 #error ARM_NARCH is 0
95 #endif
96
97 #if ARM_ARCH_5 || ARM_ARCH_6
98 /*
99 * We could support Thumb code on v4T, but the lack of clean interworking
100 * makes that hard.
101 */
102 #define THUMB_CODE
103 #endif
104
105 /*
106 * Step 3: Define which MMU classes are configured:
107 *
108 * ARM_MMU_MEMC Prehistoric, external memory controller
109 * and MMU for ARMv2 CPUs.
110 *
111 * ARM_MMU_GENERIC Generic ARM MMU, compatible with ARM6.
112 *
113 * ARM_MMU_SA1 StrongARM SA-1 MMU. Compatible with generic
114 * ARM MMU, but has no write-through cache mode.
115 *
116 * ARM_MMU_XSCALE XScale MMU. Compatible with generic ARM
117 * MMU, but also has several extensions which
118 * require different PTE layout to use.
119 */
120 #if (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3))
121 #define ARM_MMU_MEMC 1
122 #else
123 #define ARM_MMU_MEMC 0
124 #endif
125
126 #if (defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) || \
127 defined(CPU_ARM8) || defined(CPU_ARM9) || defined(CPU_ARM9E) || \
128 defined(CPU_ARM10) || defined(CPU_ARM11))
129 #define ARM_MMU_GENERIC 1
130 #else
131 #define ARM_MMU_GENERIC 0
132 #endif
133
134 #if (defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) ||\
135 defined(CPU_IXP12X0))
136 #define ARM_MMU_SA1 1
137 #else
138 #define ARM_MMU_SA1 0
139 #endif
140
141 #if(defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
142 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
143 defined(CPU_XSCALE_80219)) || defined(CPU_XSCALE_81342)
144 #define ARM_MMU_XSCALE 1
145 #else
146 #define ARM_MMU_XSCALE 0
147 #endif
148
149 #define ARM_NMMUS (ARM_MMU_MEMC + ARM_MMU_GENERIC + \
150 ARM_MMU_SA1 + ARM_MMU_XSCALE)
151 #if ARM_NMMUS == 0 && !defined(KLD_MODULE) && defined(_KERNEL)
152 #error ARM_NMMUS is 0
153 #endif
154
155 /*
156 * Step 4: Define features that may be present on a subset of CPUs
157 *
158 * ARM_XSCALE_PMU Performance Monitoring Unit on 80200 and 80321
159 */
160
161 #if (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
162 defined(CPU_XSCALE_80219)) || defined(CPU_XSCALE_81342)
163 #define ARM_XSCALE_PMU 1
164 #else
165 #define ARM_XSCALE_PMU 0
166 #endif
167
168 #if defined(CPU_XSCALE_81342)
169 #define CPU_XSCALE_CORE3
170 #endif
171 #endif /* _MACHINE_CPUCONF_H_ */
172 Cache object: 7a7c3a2fe9c9cfbe1696b14cbc26afa9
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