Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/arm/include/cpuconf.h
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1 /* $NetBSD: cpuconf.h,v 1.8 2003/09/06 08:55:42 rearnsha Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 * 37 * $FreeBSD: releng/10.1/sys/arm/include/cpuconf.h 271327 2014-09-09 18:17:43Z ian $ 38 * 39 */ 40 41 #ifndef _MACHINE_CPUCONF_H_ 42 #define _MACHINE_CPUCONF_H_ 43 44 /* 45 * IF YOU CHANGE THIS FILE, MAKE SURE TO UPDATE THE DEFINITION OF 46 * "PMAP_NEEDS_PTE_SYNC" IN <arm/arm32/pmap.h> FOR THE CPU TYPE 47 * YOU ARE ADDING SUPPORT FOR. 48 */ 49 50 /* 51 * Step 1: Count the number of CPU types configured into the kernel. 52 */ 53 #define CPU_NTYPES (defined(CPU_ARM9) + \ 54 defined(CPU_ARM9E) + \ 55 defined(CPU_ARM10) + \ 56 defined(CPU_ARM1136) + \ 57 defined(CPU_ARM1176) + \ 58 defined(CPU_XSCALE_80200) + \ 59 defined(CPU_XSCALE_80321) + \ 60 defined(CPU_XSCALE_PXA2X0) + \ 61 defined(CPU_FA526) + \ 62 defined(CPU_FA626TE) + \ 63 defined(CPU_XSCALE_IXP425)) + \ 64 defined(CPU_CORTEXA) + \ 65 defined(CPU_KRAIT) + \ 66 defined(CPU_MV_PJ4B) 67 68 /* 69 * Step 2: Determine which ARM architecture versions are configured. 70 */ 71 #if defined(CPU_ARM9) || defined(CPU_FA526) 72 #define ARM_ARCH_4 1 73 #else 74 #define ARM_ARCH_4 0 75 #endif 76 77 #if (defined(CPU_ARM9E) || defined(CPU_ARM10) || \ 78 defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 79 defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) || \ 80 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 81 defined(CPU_FA626TE)) 82 #define ARM_ARCH_5 1 83 #else 84 #define ARM_ARCH_5 0 85 #endif 86 87 #if !defined(ARM_ARCH_6) 88 #if defined(CPU_ARM1136) || defined(CPU_ARM1176) || defined(CPU_MV_PJ4B) 89 #define ARM_ARCH_6 1 90 #else 91 #define ARM_ARCH_6 0 92 #endif 93 #endif 94 95 #if defined(CPU_CORTEXA) || defined(CPU_KRAIT) 96 #define ARM_ARCH_7A 1 97 #else 98 #define ARM_ARCH_7A 0 99 #endif 100 101 #define ARM_NARCH (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6 | ARM_ARCH_7A) 102 #if ARM_NARCH == 0 && !defined(KLD_MODULE) && defined(_KERNEL) 103 #error ARM_NARCH is 0 104 #endif 105 106 #if ARM_ARCH_5 || ARM_ARCH_6 || ARM_ARCH_7A 107 /* 108 * We could support Thumb code on v4T, but the lack of clean interworking 109 * makes that hard. 110 */ 111 #define THUMB_CODE 112 #endif 113 114 /* 115 * Step 3: Define which MMU classes are configured: 116 * 117 * ARM_MMU_MEMC Prehistoric, external memory controller 118 * and MMU for ARMv2 CPUs. 119 * 120 * ARM_MMU_GENERIC Generic ARM MMU, compatible with ARMv4 and v5. 121 * 122 * ARM_MMU_V6 ARMv6 MMU. 123 * 124 * ARM_MMU_V7 ARMv7 MMU. 125 * 126 * ARM_MMU_XSCALE XScale MMU. Compatible with generic ARM 127 * MMU, but also has several extensions which 128 * require different PTE layout to use. 129 */ 130 #if (defined(CPU_ARM9) || defined(CPU_ARM9E) || \ 131 defined(CPU_ARM10) || defined(CPU_FA526) || \ 132 defined(CPU_FA626TE)) 133 #define ARM_MMU_GENERIC 1 134 #else 135 #define ARM_MMU_GENERIC 0 136 #endif 137 138 #if defined(CPU_ARM1136) || defined(CPU_ARM1176) 139 #define ARM_MMU_V6 1 140 #else 141 #define ARM_MMU_V6 0 142 #endif 143 144 #if defined(CPU_CORTEXA) || defined(CPU_KRAIT) || defined(CPU_MV_PJ4B) 145 #define ARM_MMU_V7 1 146 #else 147 #define ARM_MMU_V7 0 148 #endif 149 150 #if (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 151 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 152 defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)) 153 #define ARM_MMU_XSCALE 1 154 #else 155 #define ARM_MMU_XSCALE 0 156 #endif 157 158 #define ARM_NMMUS (ARM_MMU_GENERIC + ARM_MMU_V6 + \ 159 ARM_MMU_V7 + ARM_MMU_XSCALE) 160 #if ARM_NMMUS == 0 && !defined(KLD_MODULE) && defined(_KERNEL) 161 #error ARM_NMMUS is 0 162 #endif 163 164 /* 165 * Step 4: Define features that may be present on a subset of CPUs 166 * 167 * ARM_XSCALE_PMU Performance Monitoring Unit on 80200 and 80321 168 */ 169 170 #if (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 171 defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)) 172 #define ARM_XSCALE_PMU 1 173 #else 174 #define ARM_XSCALE_PMU 0 175 #endif 176 177 #if defined(CPU_XSCALE_81342) 178 #define CPU_XSCALE_CORE3 179 #endif 180 #endif /* _MACHINE_CPUCONF_H_ */
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