The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/include/cpuconf.h

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    1 /*      $NetBSD: cpuconf.h,v 1.8 2003/09/06 08:55:42 rearnsha Exp $     */
    2 
    3 /*-
    4  * Copyright (c) 2002 Wasabi Systems, Inc.
    5  * All rights reserved.
    6  *
    7  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
    8  *
    9  * Redistribution and use in source and binary forms, with or without
   10  * modification, are permitted provided that the following conditions
   11  * are met:
   12  * 1. Redistributions of source code must retain the above copyright
   13  *    notice, this list of conditions and the following disclaimer.
   14  * 2. Redistributions in binary form must reproduce the above copyright
   15  *    notice, this list of conditions and the following disclaimer in the
   16  *    documentation and/or other materials provided with the distribution.
   17  * 3. All advertising materials mentioning features or use of this software
   18  *    must display the following acknowledgement:
   19  *      This product includes software developed for the NetBSD Project by
   20  *      Wasabi Systems, Inc.
   21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
   22  *    or promote products derived from this software without specific prior
   23  *    written permission.
   24  *
   25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
   26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
   29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   35  * POSSIBILITY OF SUCH DAMAGE.
   36  *
   37  * $FreeBSD: releng/6.3/sys/arm/include/cpuconf.h 146649 2005-05-26 16:05:22Z cognet $
   38  *
   39  */
   40 
   41 #ifndef _MACHINE_CPUCONF_H_
   42 #define _MACHINE_CPUCONF_H_
   43 
   44 /*
   45  * IF YOU CHANGE THIS FILE, MAKE SURE TO UPDATE THE DEFINITION OF
   46  * "PMAP_NEEDS_PTE_SYNC" IN <arm/arm32/pmap.h> FOR THE CPU TYPE
   47  * YOU ARE ADDING SUPPORT FOR.
   48  */
   49 
   50 /*
   51  * Step 1: Count the number of CPU types configured into the kernel.
   52  */
   53 #define CPU_NTYPES      2
   54 
   55 /*
   56  * Step 2: Determine which ARM architecture versions are configured.
   57  */
   58 
   59 #if (defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \
   60      defined(CPU_ARM10) || defined(CPU_SA110) || defined(CPU_SA1100) || \
   61      defined(CPU_SA1110) || defined(CPU_IXP12X0) || defined(CPU_XSCALE_IXP425))
   62 #define ARM_ARCH_4      1
   63 #else
   64 #define ARM_ARCH_4      0
   65 #endif
   66 
   67 #if (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) ||          \
   68      defined(CPU_XSCALE_PXA2X0))
   69 #define ARM_ARCH_5      1
   70 #else
   71 #define ARM_ARCH_5      0
   72 #endif
   73 
   74 #define ARM_NARCH       (ARM_ARCH_4 + ARM_ARCH_5)
   75 #if ARM_NARCH == 0 && !defined(KLD_MODULE)
   76 #error ARM_NARCH is 0
   77 #endif
   78 
   79 /*
   80  * Step 3: Define which MMU classes are configured:
   81  *
   82  *      ARM_MMU_MEMC            Prehistoric, external memory controller
   83  *                              and MMU for ARMv2 CPUs.
   84  *
   85  *      ARM_MMU_GENERIC         Generic ARM MMU, compatible with ARM6.
   86  *
   87  *      ARM_MMU_SA1             StrongARM SA-1 MMU.  Compatible with generic
   88  *                              ARM MMU, but has no write-through cache mode.
   89  *
   90  *      ARM_MMU_XSCALE          XScale MMU.  Compatible with generic ARM
   91  *                              MMU, but also has several extensions which
   92  *                              require different PTE layout to use.
   93  */
   94 #if (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3))
   95 #define ARM_MMU_MEMC            1
   96 #else
   97 #define ARM_MMU_MEMC            0
   98 #endif
   99 
  100 #if (defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) || \
  101      defined(CPU_ARM8) || defined(CPU_ARM9) || defined(CPU_ARM10))
  102 #define ARM_MMU_GENERIC         1
  103 #else
  104 #define ARM_MMU_GENERIC         0
  105 #endif
  106 
  107 #if (defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) ||\
  108      defined(CPU_IXP12X0))
  109 #define ARM_MMU_SA1             1
  110 #else
  111 #define ARM_MMU_SA1             0
  112 #endif
  113 
  114 #if(defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) ||           \
  115      defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425))
  116 #define ARM_MMU_XSCALE          1
  117 #else
  118 #define ARM_MMU_XSCALE          0
  119 #endif
  120 
  121 #define ARM_NMMUS               (ARM_MMU_MEMC + ARM_MMU_GENERIC +       \
  122                                  ARM_MMU_SA1 + ARM_MMU_XSCALE)
  123 #if ARM_NMMUS == 0 && !defined(KLD_MODULE)
  124 #error ARM_NMMUS is 0
  125 #endif
  126 
  127 /*
  128  * Step 4: Define features that may be present on a subset of CPUs
  129  *
  130  *      ARM_XSCALE_PMU          Performance Monitoring Unit on 80200 and 80321
  131  */
  132 
  133 #if (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321))
  134 #define ARM_XSCALE_PMU  1
  135 #else
  136 #define ARM_XSCALE_PMU  0
  137 #endif
  138 
  139 #endif /* _MACHINE_CPUCONF_H_ */

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