The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/include/cpuconf.h

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    1 /*      $NetBSD: cpuconf.h,v 1.8 2003/09/06 08:55:42 rearnsha Exp $     */
    2 
    3 /*-
    4  * Copyright (c) 2002 Wasabi Systems, Inc.
    5  * All rights reserved.
    6  *
    7  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
    8  *
    9  * Redistribution and use in source and binary forms, with or without
   10  * modification, are permitted provided that the following conditions
   11  * are met:
   12  * 1. Redistributions of source code must retain the above copyright
   13  *    notice, this list of conditions and the following disclaimer.
   14  * 2. Redistributions in binary form must reproduce the above copyright
   15  *    notice, this list of conditions and the following disclaimer in the
   16  *    documentation and/or other materials provided with the distribution.
   17  * 3. All advertising materials mentioning features or use of this software
   18  *    must display the following acknowledgement:
   19  *      This product includes software developed for the NetBSD Project by
   20  *      Wasabi Systems, Inc.
   21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
   22  *    or promote products derived from this software without specific prior
   23  *    written permission.
   24  *
   25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
   26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
   29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   35  * POSSIBILITY OF SUCH DAMAGE.
   36  *
   37  * $FreeBSD: releng/9.0/sys/arm/include/cpuconf.h 215031 2010-11-09 09:34:21Z kevlo $
   38  *
   39  */
   40 
   41 #ifndef _MACHINE_CPUCONF_H_
   42 #define _MACHINE_CPUCONF_H_
   43 
   44 /*
   45  * IF YOU CHANGE THIS FILE, MAKE SURE TO UPDATE THE DEFINITION OF
   46  * "PMAP_NEEDS_PTE_SYNC" IN <arm/arm32/pmap.h> FOR THE CPU TYPE
   47  * YOU ARE ADDING SUPPORT FOR.
   48  */
   49 
   50 /*
   51  * Step 1: Count the number of CPU types configured into the kernel.
   52  */
   53 #define CPU_NTYPES      (defined(CPU_ARM7TDMI) +                        \
   54                          defined(CPU_ARM8) + defined(CPU_ARM9) +        \
   55                          defined(CPU_ARM9E) +                           \
   56                          defined(CPU_ARM10) +                           \
   57                          defined(CPU_ARM11) +                           \
   58                          defined(CPU_SA110) + defined(CPU_SA1100) +     \
   59                          defined(CPU_SA1110) +                          \
   60                          defined(CPU_IXP12X0) +                         \
   61                          defined(CPU_XSCALE_80200) +                    \
   62                          defined(CPU_XSCALE_80321) +                    \
   63                          defined(CPU_XSCALE_PXA2X0) +                   \
   64                          defined(CPU_FA526) +                           \
   65                          defined(CPU_FA626TE) +                         \
   66                          defined(CPU_XSCALE_IXP425))
   67 
   68 /*
   69  * Step 2: Determine which ARM architecture versions are configured.
   70  */
   71 #if (defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \
   72      defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \
   73      defined(CPU_IXP12X0) || defined(CPU_FA526))
   74 #define ARM_ARCH_4      1
   75 #else
   76 #define ARM_ARCH_4      0
   77 #endif
   78 
   79 #if (defined(CPU_ARM9E) || defined(CPU_ARM10) ||                        \
   80      defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) ||          \
   81      defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) ||          \
   82      defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) ||        \
   83      defined(CPU_FA626TE))
   84 #define ARM_ARCH_5      1
   85 #else
   86 #define ARM_ARCH_5      0
   87 #endif
   88 
   89 #if defined(CPU_ARM11)
   90 #define ARM_ARCH_6      1
   91 #else
   92 #define ARM_ARCH_6      0
   93 #endif
   94 
   95 #define ARM_NARCH       (ARM_ARCH_4 + ARM_ARCH_5 + ARM_ARCH_6)
   96 #if ARM_NARCH == 0 && !defined(KLD_MODULE) && defined(_KERNEL)
   97 #error ARM_NARCH is 0
   98 #endif
   99 
  100 #if ARM_ARCH_5 || ARM_ARCH_6
  101 /*
  102  * We could support Thumb code on v4T, but the lack of clean interworking
  103  * makes that hard.
  104  */
  105 #define THUMB_CODE
  106 #endif
  107 
  108 /*
  109  * Step 3: Define which MMU classes are configured:
  110  *
  111  *      ARM_MMU_MEMC            Prehistoric, external memory controller
  112  *                              and MMU for ARMv2 CPUs.
  113  *
  114  *      ARM_MMU_GENERIC         Generic ARM MMU, compatible with ARM6.
  115  *
  116  *      ARM_MMU_SA1             StrongARM SA-1 MMU.  Compatible with generic
  117  *                              ARM MMU, but has no write-through cache mode.
  118  *
  119  *      ARM_MMU_XSCALE          XScale MMU.  Compatible with generic ARM
  120  *                              MMU, but also has several extensions which
  121  *                              require different PTE layout to use.
  122  */
  123 #if (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3))
  124 #define ARM_MMU_MEMC            1
  125 #else
  126 #define ARM_MMU_MEMC            0
  127 #endif
  128 
  129 #if (defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) || \
  130      defined(CPU_ARM8) || defined(CPU_ARM9) || defined(CPU_ARM9E) ||    \
  131      defined(CPU_ARM10) || defined(CPU_ARM11) || defined(CPU_FA526) ||  \
  132      defined(CPU_FA626TE))
  133 #define ARM_MMU_GENERIC         1
  134 #else
  135 #define ARM_MMU_GENERIC         0
  136 #endif
  137 
  138 #if (defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) ||\
  139      defined(CPU_IXP12X0))
  140 #define ARM_MMU_SA1             1
  141 #else
  142 #define ARM_MMU_SA1             0
  143 #endif
  144 
  145 #if (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) ||          \
  146      defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) ||        \
  147      defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342))
  148 #define ARM_MMU_XSCALE          1
  149 #else
  150 #define ARM_MMU_XSCALE          0
  151 #endif
  152 
  153 #define ARM_NMMUS               (ARM_MMU_MEMC + ARM_MMU_GENERIC +       \
  154                                  ARM_MMU_SA1 + ARM_MMU_XSCALE)
  155 #if ARM_NMMUS == 0 && !defined(KLD_MODULE) && defined(_KERNEL)
  156 #error ARM_NMMUS is 0
  157 #endif
  158 
  159 /*
  160  * Step 4: Define features that may be present on a subset of CPUs
  161  *
  162  *      ARM_XSCALE_PMU          Performance Monitoring Unit on 80200 and 80321
  163  */
  164 
  165 #if (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
  166      defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342))
  167 #define ARM_XSCALE_PMU  1
  168 #else
  169 #define ARM_XSCALE_PMU  0
  170 #endif
  171 
  172 #if defined(CPU_XSCALE_81342)
  173 #define CPU_XSCALE_CORE3
  174 #endif
  175 #endif /* _MACHINE_CPUCONF_H_ */

Cache object: 14a054cd31c2dec38f8718393ff0d1d7


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