1 /* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */
2
3 /*-
4 * Copyright (c) 1997 Mark Brinicombe.
5 * Copyright (c) 1997 Causality Limited
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Causality Limited.
19 * 4. The name of Causality Limited may not be used to endorse or promote
20 * products derived from this software without specific prior written
21 * permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
24 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 *
35 * RiscBSD kernel project
36 *
37 * cpufunc.h
38 *
39 * Prototypes for cpu, mmu and tlb related functions.
40 *
41 * $FreeBSD: releng/6.4/sys/arm/include/cpufunc.h 146948 2005-06-03 19:49:53Z cognet $
42 */
43
44 #ifndef _MACHINE_CPUFUNC_H_
45 #define _MACHINE_CPUFUNC_H_
46
47 #ifdef _KERNEL
48
49 #include <sys/types.h>
50 #include <machine/cpuconf.h>
51 #include <machine/katelib.h> /* For in[bwl] and out[bwl] */
52
53 static __inline void
54 breakpoint(void)
55 {
56 __asm(".word 0xe7ffffff");
57 }
58
59 struct cpu_functions {
60
61 /* CPU functions */
62
63 u_int (*cf_id) (void);
64 void (*cf_cpwait) (void);
65
66 /* MMU functions */
67
68 u_int (*cf_control) (u_int bic, u_int eor);
69 void (*cf_domains) (u_int domains);
70 void (*cf_setttb) (u_int ttb);
71 u_int (*cf_faultstatus) (void);
72 u_int (*cf_faultaddress) (void);
73
74 /* TLB functions */
75
76 void (*cf_tlb_flushID) (void);
77 void (*cf_tlb_flushID_SE) (u_int va);
78 void (*cf_tlb_flushI) (void);
79 void (*cf_tlb_flushI_SE) (u_int va);
80 void (*cf_tlb_flushD) (void);
81 void (*cf_tlb_flushD_SE) (u_int va);
82
83 /*
84 * Cache operations:
85 *
86 * We define the following primitives:
87 *
88 * icache_sync_all Synchronize I-cache
89 * icache_sync_range Synchronize I-cache range
90 *
91 * dcache_wbinv_all Write-back and Invalidate D-cache
92 * dcache_wbinv_range Write-back and Invalidate D-cache range
93 * dcache_inv_range Invalidate D-cache range
94 * dcache_wb_range Write-back D-cache range
95 *
96 * idcache_wbinv_all Write-back and Invalidate D-cache,
97 * Invalidate I-cache
98 * idcache_wbinv_range Write-back and Invalidate D-cache,
99 * Invalidate I-cache range
100 *
101 * Note that the ARM term for "write-back" is "clean". We use
102 * the term "write-back" since it's a more common way to describe
103 * the operation.
104 *
105 * There are some rules that must be followed:
106 *
107 * I-cache Synch (all or range):
108 * The goal is to synchronize the instruction stream,
109 * so you may beed to write-back dirty D-cache blocks
110 * first. If a range is requested, and you can't
111 * synchronize just a range, you have to hit the whole
112 * thing.
113 *
114 * D-cache Write-Back and Invalidate range:
115 * If you can't WB-Inv a range, you must WB-Inv the
116 * entire D-cache.
117 *
118 * D-cache Invalidate:
119 * If you can't Inv the D-cache, you must Write-Back
120 * and Invalidate. Code that uses this operation
121 * MUST NOT assume that the D-cache will not be written
122 * back to memory.
123 *
124 * D-cache Write-Back:
125 * If you can't Write-back without doing an Inv,
126 * that's fine. Then treat this as a WB-Inv.
127 * Skipping the invalidate is merely an optimization.
128 *
129 * All operations:
130 * Valid virtual addresses must be passed to each
131 * cache operation.
132 */
133 void (*cf_icache_sync_all) (void);
134 void (*cf_icache_sync_range) (vm_offset_t, vm_size_t);
135
136 void (*cf_dcache_wbinv_all) (void);
137 void (*cf_dcache_wbinv_range) (vm_offset_t, vm_size_t);
138 void (*cf_dcache_inv_range) (vm_offset_t, vm_size_t);
139 void (*cf_dcache_wb_range) (vm_offset_t, vm_size_t);
140
141 void (*cf_idcache_wbinv_all) (void);
142 void (*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t);
143
144 /* Other functions */
145
146 void (*cf_flush_prefetchbuf) (void);
147 void (*cf_drain_writebuf) (void);
148 void (*cf_flush_brnchtgt_C) (void);
149 void (*cf_flush_brnchtgt_E) (u_int va);
150
151 void (*cf_sleep) (int mode);
152
153 /* Soft functions */
154
155 int (*cf_dataabt_fixup) (void *arg);
156 int (*cf_prefetchabt_fixup) (void *arg);
157
158 void (*cf_context_switch) (void);
159
160 void (*cf_setup) (char *string);
161 };
162
163 extern struct cpu_functions cpufuncs;
164 extern u_int cputype;
165
166 #define cpu_id() cpufuncs.cf_id()
167 #define cpu_cpwait() cpufuncs.cf_cpwait()
168
169 #define cpu_control(c, e) cpufuncs.cf_control(c, e)
170 #define cpu_domains(d) cpufuncs.cf_domains(d)
171 #define cpu_setttb(t) cpufuncs.cf_setttb(t)
172 #define cpu_faultstatus() cpufuncs.cf_faultstatus()
173 #define cpu_faultaddress() cpufuncs.cf_faultaddress()
174
175 #define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID()
176 #define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e)
177 #define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI()
178 #define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e)
179 #define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD()
180 #define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e)
181
182 #define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all()
183 #define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s))
184
185 #define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all()
186 #define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s))
187 #define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s))
188 #define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s))
189
190 #define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all()
191 #define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s))
192
193 #define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf()
194 #define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf()
195 #define cpu_flush_brnchtgt_C() cpufuncs.cf_flush_brnchtgt_C()
196 #define cpu_flush_brnchtgt_E(e) cpufuncs.cf_flush_brnchtgt_E(e)
197
198 #define cpu_sleep(m) cpufuncs.cf_sleep(m)
199
200 #define cpu_dataabt_fixup(a) cpufuncs.cf_dataabt_fixup(a)
201 #define cpu_prefetchabt_fixup(a) cpufuncs.cf_prefetchabt_fixup(a)
202 #define ABORT_FIXUP_OK 0 /* fixup succeeded */
203 #define ABORT_FIXUP_FAILED 1 /* fixup failed */
204 #define ABORT_FIXUP_RETURN 2 /* abort handler should return */
205
206 #define cpu_setup(a) cpufuncs.cf_setup(a)
207
208 int set_cpufuncs (void);
209 #define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */
210 #define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */
211
212 void cpufunc_nullop (void);
213 int cpufunc_null_fixup (void *);
214 int early_abort_fixup (void *);
215 int late_abort_fixup (void *);
216 u_int cpufunc_id (void);
217 u_int cpufunc_control (u_int clear, u_int bic);
218 void cpufunc_domains (u_int domains);
219 u_int cpufunc_faultstatus (void);
220 u_int cpufunc_faultaddress (void);
221
222 #ifdef CPU_ARM3
223 u_int arm3_control (u_int clear, u_int bic);
224 void arm3_cache_flush (void);
225 #endif /* CPU_ARM3 */
226
227 #if defined(CPU_ARM6) || defined(CPU_ARM7)
228 void arm67_setttb (u_int ttb);
229 void arm67_tlb_flush (void);
230 void arm67_tlb_purge (u_int va);
231 void arm67_cache_flush (void);
232 void arm67_context_switch (void);
233 #endif /* CPU_ARM6 || CPU_ARM7 */
234
235 #ifdef CPU_ARM6
236 void arm6_setup (char *string);
237 #endif /* CPU_ARM6 */
238
239 #ifdef CPU_ARM7
240 void arm7_setup (char *string);
241 #endif /* CPU_ARM7 */
242
243 #ifdef CPU_ARM7TDMI
244 int arm7_dataabt_fixup (void *arg);
245 void arm7tdmi_setup (char *string);
246 void arm7tdmi_setttb (u_int ttb);
247 void arm7tdmi_tlb_flushID (void);
248 void arm7tdmi_tlb_flushID_SE (u_int va);
249 void arm7tdmi_cache_flushID (void);
250 void arm7tdmi_context_switch (void);
251 #endif /* CPU_ARM7TDMI */
252
253 #ifdef CPU_ARM8
254 void arm8_setttb (u_int ttb);
255 void arm8_tlb_flushID (void);
256 void arm8_tlb_flushID_SE (u_int va);
257 void arm8_cache_flushID (void);
258 void arm8_cache_flushID_E (u_int entry);
259 void arm8_cache_cleanID (void);
260 void arm8_cache_cleanID_E (u_int entry);
261 void arm8_cache_purgeID (void);
262 void arm8_cache_purgeID_E (u_int entry);
263
264 void arm8_cache_syncI (void);
265 void arm8_cache_cleanID_rng (vm_offset_t start, vm_size_t end);
266 void arm8_cache_cleanD_rng (vm_offset_t start, vm_size_t end);
267 void arm8_cache_purgeID_rng (vm_offset_t start, vm_size_t end);
268 void arm8_cache_purgeD_rng (vm_offset_t start, vm_size_t end);
269 void arm8_cache_syncI_rng (vm_offset_t start, vm_size_t end);
270
271 void arm8_context_switch (void);
272
273 void arm8_setup (char *string);
274
275 u_int arm8_clock_config (u_int, u_int);
276 #endif
277
278 #ifdef CPU_SA110
279 void sa110_setup (char *string);
280 void sa110_context_switch (void);
281 #endif /* CPU_SA110 */
282
283 #if defined(CPU_SA1100) || defined(CPU_SA1110)
284 void sa11x0_drain_readbuf (void);
285
286 void sa11x0_context_switch (void);
287 void sa11x0_cpu_sleep (int mode);
288
289 void sa11x0_setup (char *string);
290 #endif
291
292 #if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110)
293 void sa1_setttb (u_int ttb);
294
295 void sa1_tlb_flushID_SE (u_int va);
296
297 void sa1_cache_flushID (void);
298 void sa1_cache_flushI (void);
299 void sa1_cache_flushD (void);
300 void sa1_cache_flushD_SE (u_int entry);
301
302 void sa1_cache_cleanID (void);
303 void sa1_cache_cleanD (void);
304 void sa1_cache_cleanD_E (u_int entry);
305
306 void sa1_cache_purgeID (void);
307 void sa1_cache_purgeID_E (u_int entry);
308 void sa1_cache_purgeD (void);
309 void sa1_cache_purgeD_E (u_int entry);
310
311 void sa1_cache_syncI (void);
312 void sa1_cache_cleanID_rng (vm_offset_t start, vm_size_t end);
313 void sa1_cache_cleanD_rng (vm_offset_t start, vm_size_t end);
314 void sa1_cache_purgeID_rng (vm_offset_t start, vm_size_t end);
315 void sa1_cache_purgeD_rng (vm_offset_t start, vm_size_t end);
316 void sa1_cache_syncI_rng (vm_offset_t start, vm_size_t end);
317
318 #endif
319
320 #ifdef CPU_ARM9
321 void arm9_setttb (u_int);
322
323 void arm9_tlb_flushID_SE (u_int va);
324
325 void arm9_icache_sync_all __P((void));
326 void arm9_icache_sync_range __P((vm_offset_t, vm_size_t));
327
328 void arm9_dcache_wbinv_all __P((void));
329 void arm9_dcache_wbinv_range __P((vm_offset_t, vm_size_t));
330 void arm9_dcache_inv_range __P((vm_offset_t, vm_size_t));
331 void arm9_dcache_wb_range __P((vm_offset_t, vm_size_t));
332
333 void arm9_idcache_wbinv_all __P((void));
334 void arm9_idcache_wbinv_range __P((vm_offset_t, vm_size_t));
335
336 void arm9_context_switch (void);
337
338 void arm9_setup (char *string);
339
340 extern unsigned arm9_dcache_sets_max;
341 extern unsigned arm9_dcache_sets_inc;
342 extern unsigned arm9_dcache_index_max;
343 extern unsigned arm9_dcache_index_inc;
344 #endif
345
346 #ifdef CPU_ARM10
347 void arm10_setttb (u_int);
348
349 void arm10_tlb_flushID_SE (u_int);
350 void arm10_tlb_flushI_SE (u_int);
351
352 void arm10_icache_sync_all (void);
353 void arm10_icache_sync_range (vm_offset_t, vm_size_t);
354
355 void arm10_dcache_wbinv_all (void);
356 void arm10_dcache_wbinv_range (vm_offset_t, vm_size_t);
357 void arm10_dcache_inv_range (vm_offset_t, vm_size_t);
358 void arm10_dcache_wb_range (vm_offset_t, vm_size_t);
359
360 void arm10_idcache_wbinv_all (void);
361 void arm10_idcache_wbinv_range (vm_offset_t, vm_size_t);
362
363 void arm10_context_switch (void);
364
365 void arm10_setup (char *string);
366
367 extern unsigned arm10_dcache_sets_max;
368 extern unsigned arm10_dcache_sets_inc;
369 extern unsigned arm10_dcache_index_max;
370 extern unsigned arm10_dcache_index_inc;
371 #endif
372
373 #if defined(CPU_ARM9) || defined(CPU_ARM10) || defined(CPU_SA110) || \
374 defined(CPU_SA1100) || defined(CPU_SA1110) || \
375 defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
376 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
377
378 void armv4_tlb_flushID (void);
379 void armv4_tlb_flushI (void);
380 void armv4_tlb_flushD (void);
381 void armv4_tlb_flushD_SE (u_int va);
382
383 void armv4_drain_writebuf (void);
384 #endif
385
386 #if defined(CPU_IXP12X0)
387 void ixp12x0_drain_readbuf (void);
388 void ixp12x0_context_switch (void);
389 void ixp12x0_setup (char *string);
390 #endif
391
392 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
393 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
394 void xscale_cpwait (void);
395
396 void xscale_cpu_sleep (int mode);
397
398 u_int xscale_control (u_int clear, u_int bic);
399
400 void xscale_setttb (u_int ttb);
401
402 void xscale_tlb_flushID_SE (u_int va);
403
404 void xscale_cache_flushID (void);
405 void xscale_cache_flushI (void);
406 void xscale_cache_flushD (void);
407 void xscale_cache_flushD_SE (u_int entry);
408
409 void xscale_cache_cleanID (void);
410 void xscale_cache_cleanD (void);
411 void xscale_cache_cleanD_E (u_int entry);
412
413 void xscale_cache_clean_minidata (void);
414
415 void xscale_cache_purgeID (void);
416 void xscale_cache_purgeID_E (u_int entry);
417 void xscale_cache_purgeD (void);
418 void xscale_cache_purgeD_E (u_int entry);
419
420 void xscale_cache_syncI (void);
421 void xscale_cache_cleanID_rng (vm_offset_t start, vm_size_t end);
422 void xscale_cache_cleanD_rng (vm_offset_t start, vm_size_t end);
423 void xscale_cache_purgeID_rng (vm_offset_t start, vm_size_t end);
424 void xscale_cache_purgeD_rng (vm_offset_t start, vm_size_t end);
425 void xscale_cache_syncI_rng (vm_offset_t start, vm_size_t end);
426 void xscale_cache_flushD_rng (vm_offset_t start, vm_size_t end);
427
428 void xscale_context_switch (void);
429
430 void xscale_setup (char *string);
431 #endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */
432
433 #define tlb_flush cpu_tlb_flushID
434 #define setttb cpu_setttb
435 #define drain_writebuf cpu_drain_writebuf
436
437 /*
438 * Macros for manipulating CPU interrupts
439 */
440 static __inline u_int32_t __set_cpsr_c(u_int bic, u_int eor) __attribute__((__unused__));
441
442 static __inline u_int32_t
443 __set_cpsr_c(u_int bic, u_int eor)
444 {
445 u_int32_t tmp, ret;
446
447 __asm __volatile(
448 "mrs %0, cpsr\n" /* Get the CPSR */
449 "bic %1, %0, %2\n" /* Clear bits */
450 "eor %1, %1, %3\n" /* XOR bits */
451 "msr cpsr_c, %1\n" /* Set the control field of CPSR */
452 : "=&r" (ret), "=&r" (tmp)
453 : "r" (bic), "r" (eor) : "memory");
454
455 return ret;
456 }
457
458 #define disable_interrupts(mask) \
459 (__set_cpsr_c((mask) & (I32_bit | F32_bit), \
460 (mask) & (I32_bit | F32_bit)))
461
462 #define enable_interrupts(mask) \
463 (__set_cpsr_c((mask | F32_bit) & (I32_bit | F32_bit), 0))
464
465 #define restore_interrupts(old_cpsr) \
466 (__set_cpsr_c((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit)))
467
468 #define intr_disable() \
469 disable_interrupts(I32_bit | F32_bit)
470 #define intr_restore(s) \
471 restore_interrupts(s)
472 /* Functions to manipulate the CPSR. */
473 u_int SetCPSR(u_int bic, u_int eor);
474 u_int GetCPSR(void);
475
476 /*
477 * Functions to manipulate cpu r13
478 * (in arm/arm32/setstack.S)
479 */
480
481 void set_stackptr __P((u_int mode, u_int address));
482 u_int get_stackptr __P((u_int mode));
483
484 /*
485 * Miscellany
486 */
487
488 int get_pc_str_offset __P((void));
489
490 /*
491 * CPU functions from locore.S
492 */
493
494 void cpu_reset __P((void)) __attribute__((__noreturn__));
495
496 /*
497 * Cache info variables.
498 */
499
500 /* PRIMARY CACHE VARIABLES */
501 extern int arm_picache_size;
502 extern int arm_picache_line_size;
503 extern int arm_picache_ways;
504
505 extern int arm_pdcache_size; /* and unified */
506 extern int arm_pdcache_line_size;
507 extern int arm_pdcache_ways;
508
509 extern int arm_pcache_type;
510 extern int arm_pcache_unified;
511
512 extern int arm_dcache_align;
513 extern int arm_dcache_align_mask;
514
515 #endif /* _KERNEL */
516 #endif /* _MACHINE_CPUFUNC_H_ */
517
518 /* End of cpufunc.h */
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