pl310.h

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (c) 2012 Olivier Houchard.  All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  *
   15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   25  */
   26 
   27 /*
   28  * $FreeBSD$
   29  */
   30 
   31 #ifndef PL310_H_
   32 #define PL310_H_
   33 
   34 /**
   35  *      PL310 - L2 Cache Controller register offsets.
   36  *
   37  */
   38 #define PL310_CACHE_ID                  0x000
   39 #define         CACHE_ID_RELEASE_SHIFT          0
   40 #define         CACHE_ID_RELEASE_MASK           0x3f
   41 #define         CACHE_ID_RELEASE_r0p0           0x00
   42 #define         CACHE_ID_RELEASE_r1p0           0x02
   43 #define         CACHE_ID_RELEASE_r2p0           0x04
   44 #define         CACHE_ID_RELEASE_r3p0           0x05
   45 #define         CACHE_ID_RELEASE_r3p1           0x06
   46 #define         CACHE_ID_RELEASE_r3p2           0x08
   47 #define         CACHE_ID_RELEASE_r3p3           0x09
   48 #define         CACHE_ID_PARTNUM_SHIFT          6
   49 #define         CACHE_ID_PARTNUM_MASK           0xf
   50 #define         CACHE_ID_PARTNUM_VALUE          0x3
   51 #define PL310_CACHE_TYPE                0x004
   52 #define PL310_CTRL                      0x100
   53 #define         CTRL_ENABLED                    0x01
   54 #define         CTRL_DISABLED                   0x00
   55 #define PL310_AUX_CTRL                  0x104
   56 #define         AUX_CTRL_MASK                   0xc0000fff
   57 #define         AUX_CTRL_ASSOCIATIVITY_SHIFT    16
   58 #define         AUX_CTRL_WAY_SIZE_SHIFT         17
   59 #define         AUX_CTRL_WAY_SIZE_MASK          (0x7 << 17)
   60 #define         AUX_CTRL_SHARE_OVERRIDE         (1 << 22)
   61 #define         AUX_CTRL_NS_LOCKDOWN            (1 << 26)
   62 #define         AUX_CTRL_NS_INT_CTRL            (1 << 27)
   63 #define         AUX_CTRL_DATA_PREFETCH          (1 << 28)
   64 #define         AUX_CTRL_INSTR_PREFETCH         (1 << 29)
   65 #define         AUX_CTRL_EARLY_BRESP            (1 << 30)
   66 #define PL310_TAG_RAM_CTRL                      0x108
   67 #define PL310_DATA_RAM_CTRL                     0x10C
   68 #define         RAM_CTRL_WRITE_SHIFT            8
   69 #define         RAM_CTRL_WRITE_MASK             (0x7 << 8)
   70 #define         RAM_CTRL_READ_SHIFT             4
   71 #define         RAM_CTRL_READ_MASK              (0x7 << 4)
   72 #define         RAM_CTRL_SETUP_SHIFT            0
   73 #define         RAM_CTRL_SETUP_MASK             (0x7 << 0)
   74 #define PL310_EVENT_COUNTER_CTRL        0x200
   75 #define         EVENT_COUNTER_CTRL_ENABLED      (1 << 0)
   76 #define         EVENT_COUNTER_CTRL_C0_RESET     (1 << 1)
   77 #define         EVENT_COUNTER_CTRL_C1_RESET     (1 << 2)
   78 #define PL310_EVENT_COUNTER1_CONF       0x204
   79 #define PL310_EVENT_COUNTER0_CONF       0x208
   80 #define         EVENT_COUNTER_CONF_NOINTR       0
   81 #define         EVENT_COUNTER_CONF_INCR         1
   82 #define         EVENT_COUNTER_CONF_OVFW         2
   83 #define         EVENT_COUNTER_CONF_NOEV         (0 << 2)
   84 #define         EVENT_COUNTER_CONF_CO           (1 << 2)
   85 #define         EVENT_COUNTER_CONF_DRHIT        (2 << 2)
   86 #define         EVENT_COUNTER_CONF_DRREQ        (3 << 2)
   87 #define         EVENT_COUNTER_CONF_DWHIT        (4 << 2)
   88 #define         EVENT_COUNTER_CONF_DWREQ        (5 << 2)
   89 #define         EVENT_COUNTER_CONF_DWTREQ       (6 << 2)
   90 #define         EVENT_COUNTER_CONF_DIRHIT       (7 << 2)
   91 #define         EVENT_COUNTER_CONF_DIRREQ       (8 << 2)
   92 #define         EVENT_COUNTER_CONF_WA           (9 << 2)
   93 #define PL310_EVENT_COUNTER1_VAL        0x20C
   94 #define PL310_EVENT_COUNTER0_VAL        0x210
   95 #define PL310_INTR_MASK                 0x214
   96 #define PL310_MASKED_INTR_STAT          0x218
   97 #define PL310_RAW_INTR_STAT             0x21C
   98 #define PL310_INTR_CLEAR                0x220
   99 #define         INTR_MASK_ALL                   ((1 << 9) - 1)
  100 #define         INTR_MASK_ECNTR                 (1 << 0)
  101 #define         INTR_MASK_PARRT                 (1 << 1)
  102 #define         INTR_MASK_PARRD                 (1 << 2)
  103 #define         INTR_MASK_ERRWT                 (1 << 3)
  104 #define         INTR_MASK_ERRWD                 (1 << 4)
  105 #define         INTR_MASK_ERRRT                 (1 << 5)
  106 #define         INTR_MASK_ERRRD                 (1 << 6)
  107 #define         INTR_MASK_SLVERR                (1 << 7)
  108 #define         INTR_MASK_DECERR                (1 << 8)
  109 #define PL310_CACHE_SYNC                0x730
  110 #define PL310_INV_LINE_PA               0x770
  111 #define PL310_INV_WAY                   0x77C
  112 #define PL310_CLEAN_LINE_PA             0x7B0
  113 #define PL310_CLEAN_LINE_IDX            0x7B8
  114 #define PL310_CLEAN_WAY                 0x7BC
  115 #define PL310_CLEAN_INV_LINE_PA         0x7F0
  116 #define PL310_CLEAN_INV_LINE_IDX        0x7F8
  117 #define PL310_CLEAN_INV_WAY             0x7FC
  118 #define PL310_LOCKDOWN_D_WAY(x)         (0x900 + ((x) * 8))
  119 #define PL310_LOCKDOWN_I_WAY(x)         (0x904 + ((x) * 8))
  120 #define PL310_LOCKDOWN_LINE_ENABLE      0x950
  121 #define PL310_UNLOCK_ALL_LINES_WAY      0x954
  122 #define PL310_ADDR_FILTER_STAR          0xC00
  123 #define PL310_ADDR_FILTER_END           0xC04
  124 #define PL310_DEBUG_CTRL                0xF40
  125 #define         DEBUG_CTRL_DISABLE_LINEFILL     (1 << 0)
  126 #define         DEBUG_CTRL_DISABLE_WRITEBACK    (1 << 1)
  127 #define         DEBUG_CTRL_SPNIDEN              (1 << 2)
  128 #define PL310_PREFETCH_CTRL             0xF60
  129 #define         PREFETCH_CTRL_OFFSET_MASK       (0x1f)
  130 #define         PREFETCH_CTRL_NOTSAMEID         (1 << 21)
  131 #define         PREFETCH_CTRL_INCR_DL           (1 << 23)
  132 #define         PREFETCH_CTRL_PREFETCH_DROP     (1 << 24)
  133 #define         PREFETCH_CTRL_DL_ON_WRAP        (1 << 27)
  134 #define         PREFETCH_CTRL_DATA_PREFETCH     (1 << 28)
  135 #define         PREFETCH_CTRL_INSTR_PREFETCH    (1 << 29)
  136 #define         PREFETCH_CTRL_DL                (1 << 30)
  137 #define PL310_POWER_CTRL                0xF80
  138 #define         POWER_CTRL_ENABLE_GATING        (1 << 1)
  139 #define         POWER_CTRL_ENABLE_STANDBY       (1 << 0)
  140 
  141 struct intr_config_hook;
  142 
  143 struct pl310_softc {
  144         device_t        sc_dev;
  145         struct resource *sc_mem_res;
  146         struct resource *sc_irq_res;
  147         void*           sc_irq_h;
  148         int             sc_enabled;
  149         struct mtx      sc_mtx;
  150         u_int           sc_rtl_revision;
  151         struct intr_config_hook *sc_ich;
  152         boolean_t       sc_io_coherent;
  153 };
  154 
  155 /**
  156  *      pl310_read4 - read a 32-bit value from the PL310 registers
  157  *      pl310_write4 - write a 32-bit value from the PL310 registers
  158  *      @off: byte offset within the register set to read from
  159  *      @val: the value to write into the register
  160  *
  161  *
  162  *      LOCKING:
  163  *      None
  164  *
  165  *      RETURNS:
  166  *      nothing in case of write function, if read function returns the value read.
  167  */
  168 static __inline uint32_t
  169 pl310_read4(struct pl310_softc *sc, bus_size_t off)
  170 {
  171 
  172         return bus_read_4(sc->sc_mem_res, off);
  173 }
  174 
  175 static __inline void
  176 pl310_write4(struct pl310_softc *sc, bus_size_t off, uint32_t val)
  177 {
  178 
  179         bus_write_4(sc->sc_mem_res, off, val);
  180 }
  181 
  182 void pl310_set_ram_latency(struct pl310_softc *sc, uint32_t which_reg,
  183     uint32_t read, uint32_t write, uint32_t setup);
  184 
  185 #ifndef PLATFORM
  186 void platform_pl310_init(struct pl310_softc *);
  187 void platform_pl310_write_ctrl(struct pl310_softc *, uint32_t);
  188 void platform_pl310_write_debug(struct pl310_softc *, uint32_t);
  189 #endif
  190 
  191 #endif /* PL310_H_ */

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FreeBSD/Linux Kernel Cross Reference sys/arm/include/pl310.h

FreeBSD/Linux Kernel Cross Reference
sys/arm/include/pl310.h