The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/arm/include/pmap.h

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    1 /*-
    2  * Copyright (c) 1991 Regents of the University of California.
    3  * All rights reserved.
    4  *
    5  * This code is derived from software contributed to Berkeley by
    6  * the Systems Programming Group of the University of Utah Computer
    7  * Science Department and William Jolitz of UUNET Technologies Inc.
    8  *
    9  * Redistribution and use in source and binary forms, with or without
   10  * modification, are permitted provided that the following conditions
   11  * are met:
   12  * 1. Redistributions of source code must retain the above copyright
   13  *    notice, this list of conditions and the following disclaimer.
   14  * 2. Redistributions in binary form must reproduce the above copyright
   15  *    notice, this list of conditions and the following disclaimer in the
   16  *    documentation and/or other materials provided with the distribution.
   17  * 3. All advertising materials mentioning features or use of this software
   18  *    must display the following acknowledgement:
   19  *      This product includes software developed by the University of
   20  *      California, Berkeley and its contributors.
   21  * 4. Neither the name of the University nor the names of its contributors
   22  *    may be used to endorse or promote products derived from this software
   23  *    without specific prior written permission.
   24  *
   25  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   27  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   28  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   29  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   30  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   31  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   32  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   33  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   34  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   35  * SUCH DAMAGE.
   36  *
   37  * Derived from hp300 version by Mike Hibler, this version by William
   38  * Jolitz uses a recursive map [a pde points to the page directory] to
   39  * map the page tables using the pagetables themselves. This is done to
   40  * reduce the impact on kernel virtual memory for lots of sparse address
   41  * space, and to reduce the cost of memory to each process.
   42  *
   43  *      from: hp300: @(#)pmap.h 7.2 (Berkeley) 12/16/90
   44  *      from: @(#)pmap.h        7.4 (Berkeley) 5/12/91
   45  *      from: FreeBSD: src/sys/i386/include/pmap.h,v 1.70 2000/11/30
   46  *
   47  * $FreeBSD: releng/10.3/sys/arm/include/pmap.h 278614 2015-02-12 04:15:55Z ian $
   48  */
   49 
   50 #ifndef _MACHINE_PMAP_H_
   51 #define _MACHINE_PMAP_H_
   52 
   53 #include <machine/pte.h>
   54 #include <machine/cpuconf.h>
   55 /*
   56  * Pte related macros
   57  */
   58 #if ARM_ARCH_6 || ARM_ARCH_7A
   59 #ifdef SMP
   60 #define PTE_NOCACHE     2
   61 #else
   62 #define PTE_NOCACHE     1
   63 #endif
   64 #define PTE_CACHE       6
   65 #define PTE_DEVICE      2
   66 #define PTE_PAGETABLE   6
   67 #else
   68 #define PTE_NOCACHE     1
   69 #define PTE_CACHE       2
   70 #define PTE_DEVICE      PTE_NOCACHE
   71 #define PTE_PAGETABLE   3
   72 #endif
   73 
   74 enum mem_type {
   75         STRONG_ORD = 0,
   76         DEVICE_NOSHARE,
   77         DEVICE_SHARE,
   78         NRML_NOCACHE,
   79         NRML_IWT_OWT,
   80         NRML_IWB_OWB,
   81         NRML_IWBA_OWBA
   82 };
   83 
   84 #ifndef LOCORE
   85 
   86 #include <sys/queue.h>
   87 #include <sys/_cpuset.h>
   88 #include <sys/_lock.h>
   89 #include <sys/_mutex.h>
   90 
   91 #define PDESIZE         sizeof(pd_entry_t)      /* for assembly files */
   92 #define PTESIZE         sizeof(pt_entry_t)      /* for assembly files */
   93 
   94 #ifdef _KERNEL
   95 
   96 #define vtophys(va)     pmap_kextract((vm_offset_t)(va))
   97 
   98 #endif
   99 
  100 #define pmap_page_get_memattr(m)        ((m)->md.pv_memattr)
  101 #define pmap_page_is_write_mapped(m)    (((m)->aflags & PGA_WRITEABLE) != 0)
  102 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0
  103 boolean_t pmap_page_is_mapped(vm_page_t);
  104 #else
  105 #define pmap_page_is_mapped(m)  (!TAILQ_EMPTY(&(m)->md.pv_list))
  106 #endif
  107 void pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma);
  108 
  109 /*
  110  * Pmap stuff
  111  */
  112 
  113 /*
  114  * This structure is used to hold a virtual<->physical address
  115  * association and is used mostly by bootstrap code
  116  */
  117 struct pv_addr {
  118         SLIST_ENTRY(pv_addr) pv_list;
  119         vm_offset_t     pv_va;
  120         vm_paddr_t      pv_pa;
  121 };
  122 
  123 struct  pv_entry;
  124 struct  pv_chunk;
  125 
  126 struct  md_page {
  127         int pvh_attrs;
  128         vm_memattr_t     pv_memattr;
  129 #if (ARM_MMU_V6 + ARM_MMU_V7) == 0
  130         vm_offset_t pv_kva;             /* first kernel VA mapping */
  131 #endif
  132         TAILQ_HEAD(,pv_entry)   pv_list;
  133 };
  134 
  135 struct l1_ttable;
  136 struct l2_dtable;
  137 
  138 
  139 /*
  140  * The number of L2 descriptor tables which can be tracked by an l2_dtable.
  141  * A bucket size of 16 provides for 16MB of contiguous virtual address
  142  * space per l2_dtable. Most processes will, therefore, require only two or
  143  * three of these to map their whole working set.
  144  */
  145 #define L2_BUCKET_LOG2  4
  146 #define L2_BUCKET_SIZE  (1 << L2_BUCKET_LOG2)
  147 /*
  148  * Given the above "L2-descriptors-per-l2_dtable" constant, the number
  149  * of l2_dtable structures required to track all possible page descriptors
  150  * mappable by an L1 translation table is given by the following constants:
  151  */
  152 #define L2_LOG2         ((32 - L1_S_SHIFT) - L2_BUCKET_LOG2)
  153 #define L2_SIZE         (1 << L2_LOG2)
  154 
  155 struct  pmap {
  156         struct mtx              pm_mtx;
  157         u_int8_t                pm_domain;
  158         struct l1_ttable        *pm_l1;
  159         struct l2_dtable        *pm_l2[L2_SIZE];
  160         cpuset_t                pm_active;      /* active on cpus */
  161         struct pmap_statistics  pm_stats;       /* pmap statictics */
  162 #if (ARM_MMU_V6 + ARM_MMU_V7) != 0
  163         TAILQ_HEAD(,pv_chunk)   pm_pvchunk;     /* list of mappings in pmap */
  164 #else
  165         TAILQ_HEAD(,pv_entry)   pm_pvlist;      /* list of mappings in pmap */
  166 #endif
  167 };
  168 
  169 typedef struct pmap *pmap_t;
  170 
  171 #ifdef _KERNEL
  172 extern struct pmap      kernel_pmap_store;
  173 #define kernel_pmap     (&kernel_pmap_store)
  174 #define pmap_kernel() kernel_pmap
  175 
  176 #define PMAP_ASSERT_LOCKED(pmap) \
  177                                 mtx_assert(&(pmap)->pm_mtx, MA_OWNED)
  178 #define PMAP_LOCK(pmap)         mtx_lock(&(pmap)->pm_mtx)
  179 #define PMAP_LOCK_DESTROY(pmap) mtx_destroy(&(pmap)->pm_mtx)
  180 #define PMAP_LOCK_INIT(pmap)    mtx_init(&(pmap)->pm_mtx, "pmap", \
  181                                     NULL, MTX_DEF | MTX_DUPOK)
  182 #define PMAP_OWNED(pmap)        mtx_owned(&(pmap)->pm_mtx)
  183 #define PMAP_MTX(pmap)          (&(pmap)->pm_mtx)
  184 #define PMAP_TRYLOCK(pmap)      mtx_trylock(&(pmap)->pm_mtx)
  185 #define PMAP_UNLOCK(pmap)       mtx_unlock(&(pmap)->pm_mtx)
  186 #endif
  187 
  188 
  189 /*
  190  * For each vm_page_t, there is a list of all currently valid virtual
  191  * mappings of that page.  An entry is a pv_entry_t, the list is pv_list.
  192  */
  193 typedef struct pv_entry {
  194         vm_offset_t     pv_va;          /* virtual address for mapping */
  195         TAILQ_ENTRY(pv_entry)   pv_list;
  196         int             pv_flags;       /* flags (wired, etc...) */
  197 #if (ARM_MMU_V6 + ARM_MMU_V7) == 0
  198         pmap_t          pv_pmap;        /* pmap where mapping lies */
  199         TAILQ_ENTRY(pv_entry)   pv_plist;
  200 #endif
  201 } *pv_entry_t;
  202 
  203 /*
  204  * pv_entries are allocated in chunks per-process.  This avoids the
  205  * need to track per-pmap assignments.
  206  */
  207 #define _NPCM   8
  208 #define _NPCPV  252
  209 
  210 struct pv_chunk {
  211         pmap_t                  pc_pmap;
  212         TAILQ_ENTRY(pv_chunk)   pc_list;
  213         uint32_t                pc_map[_NPCM];  /* bitmap; 1 = free */
  214         uint32_t                pc_dummy[3];    /* aligns pv_chunk to 4KB */
  215         TAILQ_ENTRY(pv_chunk)   pc_lru;
  216         struct pv_entry         pc_pventry[_NPCPV];
  217 };
  218 
  219 #ifdef _KERNEL
  220 
  221 boolean_t pmap_get_pde_pte(pmap_t, vm_offset_t, pd_entry_t **, pt_entry_t **);
  222 
  223 /*
  224  * virtual address to page table entry and
  225  * to physical address. Likewise for alternate address space.
  226  * Note: these work recursively, thus vtopte of a pte will give
  227  * the corresponding pde that in turn maps it.
  228  */
  229 
  230 /*
  231  * The current top of kernel VM.
  232  */
  233 extern vm_offset_t pmap_curmaxkvaddr;
  234 
  235 struct pcb;
  236 
  237 void    pmap_set_pcb_pagedir(pmap_t, struct pcb *);
  238 /* Virtual address to page table entry */
  239 static __inline pt_entry_t *
  240 vtopte(vm_offset_t va)
  241 {
  242         pd_entry_t *pdep;
  243         pt_entry_t *ptep;
  244 
  245         if (pmap_get_pde_pte(pmap_kernel(), va, &pdep, &ptep) == FALSE)
  246                 return (NULL);
  247         return (ptep);
  248 }
  249 
  250 extern vm_paddr_t phys_avail[];
  251 extern vm_offset_t virtual_avail;
  252 extern vm_offset_t virtual_end;
  253 
  254 void    pmap_bootstrap(vm_offset_t firstaddr, struct pv_addr *l1pt);
  255 int     pmap_change_attr(vm_offset_t, vm_size_t, int);
  256 void    pmap_kenter(vm_offset_t va, vm_paddr_t pa);
  257 void    pmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa);
  258 void    pmap_kenter_device(vm_offset_t va, vm_paddr_t pa);
  259 void    *pmap_kenter_temporary(vm_paddr_t pa, int i);
  260 void    pmap_kenter_user(vm_offset_t va, vm_paddr_t pa);
  261 vm_paddr_t pmap_kextract(vm_offset_t va);
  262 void    pmap_kremove(vm_offset_t);
  263 void    *pmap_mapdev(vm_offset_t, vm_size_t);
  264 void    pmap_unmapdev(vm_offset_t, vm_size_t);
  265 vm_page_t       pmap_use_pt(pmap_t, vm_offset_t);
  266 void    pmap_debug(int);
  267 #if (ARM_MMU_V6 + ARM_MMU_V7) == 0
  268 void    pmap_map_section(vm_offset_t, vm_offset_t, vm_offset_t, int, int);
  269 #endif
  270 void    pmap_link_l2pt(vm_offset_t, vm_offset_t, struct pv_addr *);
  271 vm_size_t       pmap_map_chunk(vm_offset_t, vm_offset_t, vm_offset_t, vm_size_t, int, int);
  272 void
  273 pmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot,
  274     int cache);
  275 int pmap_fault_fixup(pmap_t, vm_offset_t, vm_prot_t, int);
  276 int pmap_dmap_iscurrent(pmap_t pmap);
  277 
  278 /*
  279  * Definitions for MMU domains
  280  */
  281 #define PMAP_DOMAINS            15      /* 15 'user' domains (1-15) */
  282 #define PMAP_DOMAIN_KERNEL      0       /* The kernel uses domain #0 */
  283 
  284 /*
  285  * The new pmap ensures that page-tables are always mapping Write-Thru.
  286  * Thus, on some platforms we can run fast and loose and avoid syncing PTEs
  287  * on every change.
  288  *
  289  * Unfortunately, not all CPUs have a write-through cache mode.  So we
  290  * define PMAP_NEEDS_PTE_SYNC for C code to conditionally do PTE syncs,
  291  * and if there is the chance for PTE syncs to be needed, we define
  292  * PMAP_INCLUDE_PTE_SYNC so e.g. assembly code can include (and run)
  293  * the code.
  294  */
  295 extern int pmap_needs_pte_sync;
  296 
  297 /*
  298  * These macros define the various bit masks in the PTE.
  299  *
  300  * We use these macros since we use different bits on different processor
  301  * models.
  302  */
  303 
  304 #define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C)
  305 #define L1_S_CACHE_MASK_xscale  (L1_S_B|L1_S_C|L1_S_XSCALE_TEX(TEX_XSCALE_X)|\
  306                                 L1_S_XSCALE_TEX(TEX_XSCALE_T))
  307 
  308 #define L2_L_CACHE_MASK_generic (L2_B|L2_C)
  309 #define L2_L_CACHE_MASK_xscale  (L2_B|L2_C|L2_XSCALE_L_TEX(TEX_XSCALE_X) | \
  310                                 L2_XSCALE_L_TEX(TEX_XSCALE_T))
  311 
  312 #define L2_S_PROT_U_generic     (L2_AP(AP_U))
  313 #define L2_S_PROT_W_generic     (L2_AP(AP_W))
  314 #define L2_S_PROT_MASK_generic  (L2_S_PROT_U|L2_S_PROT_W)
  315 
  316 #define L2_S_PROT_U_xscale      (L2_AP0(AP_U))
  317 #define L2_S_PROT_W_xscale      (L2_AP0(AP_W))
  318 #define L2_S_PROT_MASK_xscale   (L2_S_PROT_U|L2_S_PROT_W)
  319 
  320 #define L2_S_CACHE_MASK_generic (L2_B|L2_C)
  321 #define L2_S_CACHE_MASK_xscale  (L2_B|L2_C|L2_XSCALE_T_TEX(TEX_XSCALE_X)| \
  322                                  L2_XSCALE_T_TEX(TEX_XSCALE_X))
  323 
  324 #define L1_S_PROTO_generic      (L1_TYPE_S | L1_S_IMP)
  325 #define L1_S_PROTO_xscale       (L1_TYPE_S)
  326 
  327 #define L1_C_PROTO_generic      (L1_TYPE_C | L1_C_IMP2)
  328 #define L1_C_PROTO_xscale       (L1_TYPE_C)
  329 
  330 #define L2_L_PROTO              (L2_TYPE_L)
  331 
  332 #define L2_S_PROTO_generic      (L2_TYPE_S)
  333 #define L2_S_PROTO_xscale       (L2_TYPE_XSCALE_XS)
  334 
  335 /*
  336  * User-visible names for the ones that vary with MMU class.
  337  */
  338 #if (ARM_MMU_V6 + ARM_MMU_V7) != 0
  339 #define L2_AP(x)        (L2_AP0(x))
  340 #else
  341 #define L2_AP(x)        (L2_AP0(x) | L2_AP1(x) | L2_AP2(x) | L2_AP3(x))
  342 #endif
  343 
  344 #if (ARM_MMU_V6 + ARM_MMU_V7) != 0
  345 /*
  346  * AP[2:1] access permissions model:
  347  *
  348  * AP[2](APX)   - Write Disable
  349  * AP[1]        - User Enable
  350  * AP[0]        - Reference Flag
  351  *
  352  * AP[2]     AP[1]     Kernel     User
  353  *  0          0        R/W        N
  354  *  0          1        R/W       R/W
  355  *  1          0         R         N
  356  *  1          1         R         R
  357  *
  358  */
  359 #define L2_S_PROT_R             (0)             /* kernel read */
  360 #define L2_S_PROT_U             (L2_AP0(2))     /* user read */
  361 #define L2_S_REF                (L2_AP0(1))     /* reference flag */
  362 
  363 #define L2_S_PROT_MASK          (L2_S_PROT_U|L2_S_PROT_R|L2_APX)
  364 #define L2_S_EXECUTABLE(pte)    (!(pte & L2_XN))
  365 #define L2_S_WRITABLE(pte)      (!(pte & L2_APX))
  366 #define L2_S_REFERENCED(pte)    (!!(pte & L2_S_REF))
  367 
  368 #ifndef SMP
  369 #define L1_S_CACHE_MASK         (L1_S_TEX_MASK|L1_S_B|L1_S_C)
  370 #define L2_L_CACHE_MASK         (L2_L_TEX_MASK|L2_B|L2_C)
  371 #define L2_S_CACHE_MASK         (L2_S_TEX_MASK|L2_B|L2_C)
  372 #else
  373 #define L1_S_CACHE_MASK         (L1_S_TEX_MASK|L1_S_B|L1_S_C|L1_SHARED)
  374 #define L2_L_CACHE_MASK         (L2_L_TEX_MASK|L2_B|L2_C|L2_SHARED)
  375 #define L2_S_CACHE_MASK         (L2_S_TEX_MASK|L2_B|L2_C|L2_SHARED)
  376 #endif  /* SMP */
  377 
  378 #define L1_S_PROTO              (L1_TYPE_S)
  379 #define L1_C_PROTO              (L1_TYPE_C)
  380 #define L2_S_PROTO              (L2_TYPE_S)
  381 
  382 /*
  383  * Promotion to a 1MB (SECTION) mapping requires that the corresponding
  384  * 4KB (SMALL) page mappings have identical settings for the following fields:
  385  */
  386 #define L2_S_PROMOTE            (L2_S_REF | L2_SHARED | L2_S_PROT_MASK | \
  387                                  L2_XN | L2_S_PROTO)
  388 
  389 /*
  390  * In order to compare 1MB (SECTION) entry settings with the 4KB (SMALL)
  391  * page mapping it is necessary to read and shift appropriate bits from
  392  * L1 entry to positions of the corresponding bits in the L2 entry.
  393  */
  394 #define L1_S_DEMOTE(l1pd)       ((((l1pd) & L1_S_PROTO) >> 0) | \
  395                                 (((l1pd) & L1_SHARED) >> 6) | \
  396                                 (((l1pd) & L1_S_REF) >> 6) | \
  397                                 (((l1pd) & L1_S_PROT_MASK) >> 6) | \
  398                                 (((l1pd) & L1_S_XN) >> 4))
  399 
  400 #ifndef SMP
  401 #define ARM_L1S_STRONG_ORD      (0)
  402 #define ARM_L1S_DEVICE_NOSHARE  (L1_S_TEX(2))
  403 #define ARM_L1S_DEVICE_SHARE    (L1_S_B)
  404 #define ARM_L1S_NRML_NOCACHE    (L1_S_TEX(1))
  405 #define ARM_L1S_NRML_IWT_OWT    (L1_S_C)
  406 #define ARM_L1S_NRML_IWB_OWB    (L1_S_C|L1_S_B)
  407 #define ARM_L1S_NRML_IWBA_OWBA  (L1_S_TEX(1)|L1_S_C|L1_S_B)
  408 
  409 #define ARM_L2L_STRONG_ORD      (0)
  410 #define ARM_L2L_DEVICE_NOSHARE  (L2_L_TEX(2))
  411 #define ARM_L2L_DEVICE_SHARE    (L2_B)
  412 #define ARM_L2L_NRML_NOCACHE    (L2_L_TEX(1))
  413 #define ARM_L2L_NRML_IWT_OWT    (L2_C)
  414 #define ARM_L2L_NRML_IWB_OWB    (L2_C|L2_B)
  415 #define ARM_L2L_NRML_IWBA_OWBA  (L2_L_TEX(1)|L2_C|L2_B)
  416 
  417 #define ARM_L2S_STRONG_ORD      (0)
  418 #define ARM_L2S_DEVICE_NOSHARE  (L2_S_TEX(2))
  419 #define ARM_L2S_DEVICE_SHARE    (L2_B)
  420 #define ARM_L2S_NRML_NOCACHE    (L2_S_TEX(1))
  421 #define ARM_L2S_NRML_IWT_OWT    (L2_C)
  422 #define ARM_L2S_NRML_IWB_OWB    (L2_C|L2_B)
  423 #define ARM_L2S_NRML_IWBA_OWBA  (L2_S_TEX(1)|L2_C|L2_B)
  424 #else
  425 #define ARM_L1S_STRONG_ORD      (0)
  426 #define ARM_L1S_DEVICE_NOSHARE  (L1_S_TEX(2))
  427 #define ARM_L1S_DEVICE_SHARE    (L1_S_B)
  428 #define ARM_L1S_NRML_NOCACHE    (L1_S_TEX(1)|L1_SHARED)
  429 #define ARM_L1S_NRML_IWT_OWT    (L1_S_C|L1_SHARED)
  430 #define ARM_L1S_NRML_IWB_OWB    (L1_S_C|L1_S_B|L1_SHARED)
  431 #define ARM_L1S_NRML_IWBA_OWBA  (L1_S_TEX(1)|L1_S_C|L1_S_B|L1_SHARED)
  432 
  433 #define ARM_L2L_STRONG_ORD      (0)
  434 #define ARM_L2L_DEVICE_NOSHARE  (L2_L_TEX(2))
  435 #define ARM_L2L_DEVICE_SHARE    (L2_B)
  436 #define ARM_L2L_NRML_NOCACHE    (L2_L_TEX(1)|L2_SHARED)
  437 #define ARM_L2L_NRML_IWT_OWT    (L2_C|L2_SHARED)
  438 #define ARM_L2L_NRML_IWB_OWB    (L2_C|L2_B|L2_SHARED)
  439 #define ARM_L2L_NRML_IWBA_OWBA  (L2_L_TEX(1)|L2_C|L2_B|L2_SHARED)
  440 
  441 #define ARM_L2S_STRONG_ORD      (0)
  442 #define ARM_L2S_DEVICE_NOSHARE  (L2_S_TEX(2))
  443 #define ARM_L2S_DEVICE_SHARE    (L2_B)
  444 #define ARM_L2S_NRML_NOCACHE    (L2_S_TEX(1)|L2_SHARED)
  445 #define ARM_L2S_NRML_IWT_OWT    (L2_C|L2_SHARED)
  446 #define ARM_L2S_NRML_IWB_OWB    (L2_C|L2_B|L2_SHARED)
  447 #define ARM_L2S_NRML_IWBA_OWBA  (L2_S_TEX(1)|L2_C|L2_B|L2_SHARED)
  448 #endif /* SMP */
  449 
  450 #elif ARM_NMMUS > 1
  451 /* More than one MMU class configured; use variables. */
  452 #define L2_S_PROT_U             pte_l2_s_prot_u
  453 #define L2_S_PROT_W             pte_l2_s_prot_w
  454 #define L2_S_PROT_MASK          pte_l2_s_prot_mask
  455 
  456 #define L1_S_CACHE_MASK         pte_l1_s_cache_mask
  457 #define L2_L_CACHE_MASK         pte_l2_l_cache_mask
  458 #define L2_S_CACHE_MASK         pte_l2_s_cache_mask
  459 
  460 #define L1_S_PROTO              pte_l1_s_proto
  461 #define L1_C_PROTO              pte_l1_c_proto
  462 #define L2_S_PROTO              pte_l2_s_proto
  463 
  464 #elif ARM_MMU_GENERIC != 0
  465 #define L2_S_PROT_U             L2_S_PROT_U_generic
  466 #define L2_S_PROT_W             L2_S_PROT_W_generic
  467 #define L2_S_PROT_MASK          L2_S_PROT_MASK_generic
  468 
  469 #define L1_S_CACHE_MASK         L1_S_CACHE_MASK_generic
  470 #define L2_L_CACHE_MASK         L2_L_CACHE_MASK_generic
  471 #define L2_S_CACHE_MASK         L2_S_CACHE_MASK_generic
  472 
  473 #define L1_S_PROTO              L1_S_PROTO_generic
  474 #define L1_C_PROTO              L1_C_PROTO_generic
  475 #define L2_S_PROTO              L2_S_PROTO_generic
  476 
  477 #elif ARM_MMU_XSCALE == 1
  478 #define L2_S_PROT_U             L2_S_PROT_U_xscale
  479 #define L2_S_PROT_W             L2_S_PROT_W_xscale
  480 #define L2_S_PROT_MASK          L2_S_PROT_MASK_xscale
  481 
  482 #define L1_S_CACHE_MASK         L1_S_CACHE_MASK_xscale
  483 #define L2_L_CACHE_MASK         L2_L_CACHE_MASK_xscale
  484 #define L2_S_CACHE_MASK         L2_S_CACHE_MASK_xscale
  485 
  486 #define L1_S_PROTO              L1_S_PROTO_xscale
  487 #define L1_C_PROTO              L1_C_PROTO_xscale
  488 #define L2_S_PROTO              L2_S_PROTO_xscale
  489 
  490 #endif /* ARM_NMMUS > 1 */
  491 
  492 #if defined(CPU_XSCALE_81342) || ARM_ARCH_6 || ARM_ARCH_7A
  493 #define PMAP_NEEDS_PTE_SYNC     1
  494 #define PMAP_INCLUDE_PTE_SYNC
  495 #else
  496 #define PMAP_NEEDS_PTE_SYNC     0
  497 #endif
  498 
  499 /*
  500  * These macros return various bits based on kernel/user and protection.
  501  * Note that the compiler will usually fold these at compile time.
  502  */
  503 #if (ARM_MMU_V6 + ARM_MMU_V7) == 0
  504 
  505 #define L1_S_PROT_U             (L1_S_AP(AP_U))
  506 #define L1_S_PROT_W             (L1_S_AP(AP_W))
  507 #define L1_S_PROT_MASK          (L1_S_PROT_U|L1_S_PROT_W)
  508 #define L1_S_WRITABLE(pd)       ((pd) & L1_S_PROT_W)
  509 
  510 #define L1_S_PROT(ku, pr)       ((((ku) == PTE_USER) ? L1_S_PROT_U : 0) | \
  511                                  (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : 0))
  512 
  513 #define L2_L_PROT_U             (L2_AP(AP_U))
  514 #define L2_L_PROT_W             (L2_AP(AP_W))
  515 #define L2_L_PROT_MASK          (L2_L_PROT_U|L2_L_PROT_W)
  516 
  517 #define L2_L_PROT(ku, pr)       ((((ku) == PTE_USER) ? L2_L_PROT_U : 0) | \
  518                                  (((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : 0))
  519 
  520 #define L2_S_PROT(ku, pr)       ((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \
  521                                  (((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : 0))
  522 #else
  523 #define L1_S_PROT_U             (L1_S_AP(AP_U))
  524 #define L1_S_PROT_W             (L1_S_APX)              /* Write disable */
  525 #define L1_S_PROT_MASK          (L1_S_PROT_W|L1_S_PROT_U)
  526 #define L1_S_REF                (L1_S_AP(AP_REF))       /* Reference flag */
  527 #define L1_S_WRITABLE(pd)       (!((pd) & L1_S_PROT_W))
  528 #define L1_S_EXECUTABLE(pd)     (!((pd) & L1_S_XN))
  529 #define L1_S_REFERENCED(pd)     ((pd) & L1_S_REF)
  530 
  531 #define L1_S_PROT(ku, pr)       (((((ku) == PTE_KERNEL) ? 0 : L1_S_PROT_U) | \
  532                                  (((pr) & VM_PROT_WRITE) ? 0 : L1_S_PROT_W) | \
  533                                  (((pr) & VM_PROT_EXECUTE) ? 0 : L1_S_XN)))
  534 
  535 #define L2_L_PROT_MASK          (L2_APX|L2_AP0(0x3))
  536 #define L2_L_PROT(ku, pr)       (L2_L_PROT_MASK & ~((((ku) == PTE_KERNEL) ? L2_S_PROT_U : 0) | \
  537                                  (((pr) & VM_PROT_WRITE) ? L2_APX : 0)))
  538 
  539 #define L2_S_PROT(ku, pr)       (L2_S_PROT_MASK & ~((((ku) == PTE_KERNEL) ? L2_S_PROT_U : 0) | \
  540                                  (((pr) & VM_PROT_WRITE) ? L2_APX : 0)))
  541 
  542 #endif
  543 
  544 /*
  545  * Macros to test if a mapping is mappable with an L1 Section mapping
  546  * or an L2 Large Page mapping.
  547  */
  548 #define L1_S_MAPPABLE_P(va, pa, size)                                   \
  549         ((((va) | (pa)) & L1_S_OFFSET) == 0 && (size) >= L1_S_SIZE)
  550 
  551 #define L2_L_MAPPABLE_P(va, pa, size)                                   \
  552         ((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE)
  553 
  554 /*
  555  * Provide a fallback in case we were not able to determine it at
  556  * compile-time.
  557  */
  558 #ifndef PMAP_NEEDS_PTE_SYNC
  559 #define PMAP_NEEDS_PTE_SYNC     pmap_needs_pte_sync
  560 #define PMAP_INCLUDE_PTE_SYNC
  561 #endif
  562 
  563 #ifdef ARM_L2_PIPT
  564 #define _sync_l2(pte, size)     cpu_l2cache_wb_range(vtophys(pte), size)
  565 #else
  566 #define _sync_l2(pte, size)     cpu_l2cache_wb_range(pte, size)
  567 #endif
  568 
  569 #define PTE_SYNC(pte)                                                   \
  570 do {                                                                    \
  571         if (PMAP_NEEDS_PTE_SYNC) {                                      \
  572                 cpu_dcache_wb_range((vm_offset_t)(pte), sizeof(pt_entry_t));\
  573                 cpu_drain_writebuf();                                   \
  574                 _sync_l2((vm_offset_t)(pte), sizeof(pt_entry_t));\
  575         } else                                                          \
  576                 cpu_drain_writebuf();                                   \
  577 } while (/*CONSTCOND*/0)
  578 
  579 #define PTE_SYNC_RANGE(pte, cnt)                                        \
  580 do {                                                                    \
  581         if (PMAP_NEEDS_PTE_SYNC) {                                      \
  582                 cpu_dcache_wb_range((vm_offset_t)(pte),                 \
  583                     (cnt) << 2); /* * sizeof(pt_entry_t) */             \
  584                 cpu_drain_writebuf();                                   \
  585                 _sync_l2((vm_offset_t)(pte),                            \
  586                     (cnt) << 2); /* * sizeof(pt_entry_t) */             \
  587         } else                                                          \
  588                 cpu_drain_writebuf();                                   \
  589 } while (/*CONSTCOND*/0)
  590 
  591 extern pt_entry_t               pte_l1_s_cache_mode;
  592 extern pt_entry_t               pte_l1_s_cache_mask;
  593 
  594 extern pt_entry_t               pte_l2_l_cache_mode;
  595 extern pt_entry_t               pte_l2_l_cache_mask;
  596 
  597 extern pt_entry_t               pte_l2_s_cache_mode;
  598 extern pt_entry_t               pte_l2_s_cache_mask;
  599 
  600 extern pt_entry_t               pte_l1_s_cache_mode_pt;
  601 extern pt_entry_t               pte_l2_l_cache_mode_pt;
  602 extern pt_entry_t               pte_l2_s_cache_mode_pt;
  603 
  604 extern pt_entry_t               pte_l2_s_prot_u;
  605 extern pt_entry_t               pte_l2_s_prot_w;
  606 extern pt_entry_t               pte_l2_s_prot_mask;
  607 
  608 extern pt_entry_t               pte_l1_s_proto;
  609 extern pt_entry_t               pte_l1_c_proto;
  610 extern pt_entry_t               pte_l2_s_proto;
  611 
  612 extern void (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t);
  613 extern void (*pmap_copy_page_offs_func)(vm_paddr_t a_phys,
  614     vm_offset_t a_offs, vm_paddr_t b_phys, vm_offset_t b_offs, int cnt);
  615 extern void (*pmap_zero_page_func)(vm_paddr_t, int, int);
  616 
  617 #if (ARM_MMU_GENERIC + ARM_MMU_V6 + ARM_MMU_V7) != 0 || defined(CPU_XSCALE_81342)
  618 void    pmap_copy_page_generic(vm_paddr_t, vm_paddr_t);
  619 void    pmap_zero_page_generic(vm_paddr_t, int, int);
  620 
  621 void    pmap_pte_init_generic(void);
  622 #if defined(CPU_ARM9)
  623 void    pmap_pte_init_arm9(void);
  624 #endif /* CPU_ARM9 */
  625 #if defined(CPU_ARM10)
  626 void    pmap_pte_init_arm10(void);
  627 #endif /* CPU_ARM10 */
  628 #if (ARM_MMU_V6 + ARM_MMU_V7) != 0
  629 void    pmap_pte_init_mmu_v6(void);
  630 #endif /* (ARM_MMU_V6 + ARM_MMU_V7) != 0 */
  631 #endif /* (ARM_MMU_GENERIC + ARM_MMU_V6 + ARM_MMU_V7) != 0 */
  632 
  633 #if ARM_MMU_XSCALE == 1
  634 void    pmap_copy_page_xscale(vm_paddr_t, vm_paddr_t);
  635 void    pmap_zero_page_xscale(vm_paddr_t, int, int);
  636 
  637 void    pmap_pte_init_xscale(void);
  638 
  639 void    xscale_setup_minidata(vm_offset_t, vm_offset_t, vm_offset_t);
  640 
  641 void    pmap_use_minicache(vm_offset_t, vm_size_t);
  642 #endif /* ARM_MMU_XSCALE == 1 */
  643 #if defined(CPU_XSCALE_81342)
  644 #define ARM_HAVE_SUPERSECTIONS
  645 #endif
  646 
  647 #define PTE_KERNEL      0
  648 #define PTE_USER        1
  649 #define l1pte_valid(pde)        ((pde) != 0)
  650 #define l1pte_section_p(pde)    (((pde) & L1_TYPE_MASK) == L1_TYPE_S)
  651 #define l1pte_page_p(pde)       (((pde) & L1_TYPE_MASK) == L1_TYPE_C)
  652 #define l1pte_fpage_p(pde)      (((pde) & L1_TYPE_MASK) == L1_TYPE_F)
  653 
  654 #define l2pte_index(v)          (((v) & L2_ADDR_BITS) >> L2_S_SHIFT)
  655 #define l2pte_valid(pte)        ((pte) != 0)
  656 #define l2pte_pa(pte)           ((pte) & L2_S_FRAME)
  657 #define l2pte_minidata(pte)     (((pte) & \
  658                                  (L2_B | L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X)))\
  659                                  == (L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X)))
  660 
  661 /* L1 and L2 page table macros */
  662 #define pmap_pde_v(pde)         l1pte_valid(*(pde))
  663 #define pmap_pde_section(pde)   l1pte_section_p(*(pde))
  664 #define pmap_pde_page(pde)      l1pte_page_p(*(pde))
  665 #define pmap_pde_fpage(pde)     l1pte_fpage_p(*(pde))
  666 
  667 #define pmap_pte_v(pte)         l2pte_valid(*(pte))
  668 #define pmap_pte_pa(pte)        l2pte_pa(*(pte))
  669 
  670 /*
  671  * Flags that indicate attributes of pages or mappings of pages.
  672  *
  673  * The PVF_MOD and PVF_REF flags are stored in the mdpage for each
  674  * page.  PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual
  675  * pv_entry's for each page.  They live in the same "namespace" so
  676  * that we can clear multiple attributes at a time.
  677  *
  678  * Note the "non-cacheable" flag generally means the page has
  679  * multiple mappings in a given address space.
  680  */
  681 #define PVF_MOD         0x01            /* page is modified */
  682 #define PVF_REF         0x02            /* page is referenced */
  683 #define PVF_WIRED       0x04            /* mapping is wired */
  684 #define PVF_WRITE       0x08            /* mapping is writable */
  685 #define PVF_EXEC        0x10            /* mapping is executable */
  686 #define PVF_NC          0x20            /* mapping is non-cacheable */
  687 #define PVF_MWC         0x40            /* mapping is used multiple times in userland */
  688 #define PVF_UNMAN       0x80            /* mapping is unmanaged */
  689 
  690 void vector_page_setprot(int);
  691 
  692 #define SECTION_CACHE   0x1
  693 #define SECTION_PT      0x2
  694 void    pmap_kenter_section(vm_offset_t, vm_paddr_t, int flags);
  695 #ifdef ARM_HAVE_SUPERSECTIONS
  696 void    pmap_kenter_supersection(vm_offset_t, uint64_t, int flags);
  697 #endif
  698 
  699 extern char *_tmppt;
  700 
  701 void    pmap_postinit(void);
  702 
  703 extern vm_paddr_t dump_avail[];
  704 #endif  /* _KERNEL */
  705 
  706 #endif  /* !LOCORE */
  707 
  708 #endif  /* !_MACHINE_PMAP_H_ */

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