FreeBSD/Linux Kernel Cross Reference
sys/arm/include/pmap.h
1 /*-
2 * Copyright (c) 1991 Regents of the University of California.
3 * All rights reserved.
4 *
5 * This code is derived from software contributed to Berkeley by
6 * the Systems Programming Group of the University of Utah Computer
7 * Science Department and William Jolitz of UUNET Technologies Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by the University of
20 * California, Berkeley and its contributors.
21 * 4. Neither the name of the University nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * SUCH DAMAGE.
36 *
37 * Derived from hp300 version by Mike Hibler, this version by William
38 * Jolitz uses a recursive map [a pde points to the page directory] to
39 * map the page tables using the pagetables themselves. This is done to
40 * reduce the impact on kernel virtual memory for lots of sparse address
41 * space, and to reduce the cost of memory to each process.
42 *
43 * from: hp300: @(#)pmap.h 7.2 (Berkeley) 12/16/90
44 * from: @(#)pmap.h 7.4 (Berkeley) 5/12/91
45 * from: FreeBSD: src/sys/i386/include/pmap.h,v 1.70 2000/11/30
46 *
47 * $FreeBSD$
48 */
49
50 #ifndef _MACHINE_PMAP_H_
51 #define _MACHINE_PMAP_H_
52
53 #include <machine/pte.h>
54 #include <machine/cpuconf.h>
55 /*
56 * Pte related macros
57 */
58 #define PTE_NOCACHE 0
59 #define PTE_CACHE 1
60 #define PTE_PAGETABLE 2
61
62 #ifndef LOCORE
63
64 #include <sys/queue.h>
65 #include <sys/_cpuset.h>
66 #include <sys/_lock.h>
67 #include <sys/_mutex.h>
68
69 #define PDESIZE sizeof(pd_entry_t) /* for assembly files */
70 #define PTESIZE sizeof(pt_entry_t) /* for assembly files */
71
72 #ifdef _KERNEL
73
74 #define vtophys(va) pmap_extract(pmap_kernel(), (vm_offset_t)(va))
75 #define pmap_kextract(va) pmap_extract(pmap_kernel(), (vm_offset_t)(va))
76
77 #endif
78
79 #define pmap_page_get_memattr(m) ((m)->md.pv_memattr)
80 #define pmap_page_is_mapped(m) (!TAILQ_EMPTY(&(m)->md.pv_list))
81 #define pmap_page_is_write_mapped(m) (((m)->aflags & PGA_WRITEABLE) != 0)
82 void pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma);
83
84 /*
85 * Pmap stuff
86 */
87
88 /*
89 * This structure is used to hold a virtual<->physical address
90 * association and is used mostly by bootstrap code
91 */
92 struct pv_addr {
93 SLIST_ENTRY(pv_addr) pv_list;
94 vm_offset_t pv_va;
95 vm_paddr_t pv_pa;
96 };
97
98 struct pv_entry;
99
100 struct md_page {
101 int pvh_attrs;
102 vm_memattr_t pv_memattr;
103 vm_offset_t pv_kva; /* first kernel VA mapping */
104 TAILQ_HEAD(,pv_entry) pv_list;
105 };
106
107 #define VM_MDPAGE_INIT(pg) \
108 do { \
109 TAILQ_INIT(&pg->pv_list); \
110 mtx_init(&(pg)->md_page.pvh_mtx, "MDPAGE Mutex", NULL, MTX_DEV);\
111 (pg)->mdpage.pvh_attrs = 0; \
112 } while (/*CONSTCOND*/0)
113
114 struct l1_ttable;
115 struct l2_dtable;
116
117
118 /*
119 * The number of L2 descriptor tables which can be tracked by an l2_dtable.
120 * A bucket size of 16 provides for 16MB of contiguous virtual address
121 * space per l2_dtable. Most processes will, therefore, require only two or
122 * three of these to map their whole working set.
123 */
124 #define L2_BUCKET_LOG2 4
125 #define L2_BUCKET_SIZE (1 << L2_BUCKET_LOG2)
126 /*
127 * Given the above "L2-descriptors-per-l2_dtable" constant, the number
128 * of l2_dtable structures required to track all possible page descriptors
129 * mappable by an L1 translation table is given by the following constants:
130 */
131 #define L2_LOG2 ((32 - L1_S_SHIFT) - L2_BUCKET_LOG2)
132 #define L2_SIZE (1 << L2_LOG2)
133
134 struct pmap {
135 struct mtx pm_mtx;
136 u_int8_t pm_domain;
137 struct l1_ttable *pm_l1;
138 struct l2_dtable *pm_l2[L2_SIZE];
139 pd_entry_t *pm_pdir; /* KVA of page directory */
140 cpuset_t pm_active; /* active on cpus */
141 struct pmap_statistics pm_stats; /* pmap statictics */
142 TAILQ_HEAD(,pv_entry) pm_pvlist; /* list of mappings in pmap */
143 };
144
145 typedef struct pmap *pmap_t;
146
147 #ifdef _KERNEL
148 extern struct pmap kernel_pmap_store;
149 #define kernel_pmap (&kernel_pmap_store)
150 #define pmap_kernel() kernel_pmap
151
152 #define PMAP_ASSERT_LOCKED(pmap) \
153 mtx_assert(&(pmap)->pm_mtx, MA_OWNED)
154 #define PMAP_LOCK(pmap) mtx_lock(&(pmap)->pm_mtx)
155 #define PMAP_LOCK_DESTROY(pmap) mtx_destroy(&(pmap)->pm_mtx)
156 #define PMAP_LOCK_INIT(pmap) mtx_init(&(pmap)->pm_mtx, "pmap", \
157 NULL, MTX_DEF | MTX_DUPOK)
158 #define PMAP_OWNED(pmap) mtx_owned(&(pmap)->pm_mtx)
159 #define PMAP_MTX(pmap) (&(pmap)->pm_mtx)
160 #define PMAP_TRYLOCK(pmap) mtx_trylock(&(pmap)->pm_mtx)
161 #define PMAP_UNLOCK(pmap) mtx_unlock(&(pmap)->pm_mtx)
162 #endif
163
164
165 /*
166 * For each vm_page_t, there is a list of all currently valid virtual
167 * mappings of that page. An entry is a pv_entry_t, the list is pv_list.
168 */
169 typedef struct pv_entry {
170 pmap_t pv_pmap; /* pmap where mapping lies */
171 vm_offset_t pv_va; /* virtual address for mapping */
172 TAILQ_ENTRY(pv_entry) pv_list;
173 TAILQ_ENTRY(pv_entry) pv_plist;
174 int pv_flags; /* flags (wired, etc...) */
175 } *pv_entry_t;
176
177 #ifdef _KERNEL
178
179 boolean_t pmap_get_pde_pte(pmap_t, vm_offset_t, pd_entry_t **, pt_entry_t **);
180
181 /*
182 * virtual address to page table entry and
183 * to physical address. Likewise for alternate address space.
184 * Note: these work recursively, thus vtopte of a pte will give
185 * the corresponding pde that in turn maps it.
186 */
187
188 /*
189 * The current top of kernel VM.
190 */
191 extern vm_offset_t pmap_curmaxkvaddr;
192
193 struct pcb;
194
195 void pmap_set_pcb_pagedir(pmap_t, struct pcb *);
196 /* Virtual address to page table entry */
197 static __inline pt_entry_t *
198 vtopte(vm_offset_t va)
199 {
200 pd_entry_t *pdep;
201 pt_entry_t *ptep;
202
203 if (pmap_get_pde_pte(pmap_kernel(), va, &pdep, &ptep) == FALSE)
204 return (NULL);
205 return (ptep);
206 }
207
208 extern vm_paddr_t phys_avail[];
209 extern vm_offset_t virtual_avail;
210 extern vm_offset_t virtual_end;
211
212 void pmap_bootstrap(vm_offset_t, vm_offset_t, struct pv_addr *);
213 void pmap_kenter(vm_offset_t va, vm_paddr_t pa);
214 void pmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa);
215 void *pmap_kenter_temp(vm_paddr_t pa, int i);
216 void pmap_kenter_user(vm_offset_t va, vm_paddr_t pa);
217 void pmap_kremove(vm_offset_t);
218 void *pmap_mapdev(vm_offset_t, vm_size_t);
219 void pmap_unmapdev(vm_offset_t, vm_size_t);
220 vm_page_t pmap_use_pt(pmap_t, vm_offset_t);
221 void pmap_debug(int);
222 void pmap_map_section(vm_offset_t, vm_offset_t, vm_offset_t, int, int);
223 void pmap_link_l2pt(vm_offset_t, vm_offset_t, struct pv_addr *);
224 vm_size_t pmap_map_chunk(vm_offset_t, vm_offset_t, vm_offset_t, vm_size_t, int, int);
225 void
226 pmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot,
227 int cache);
228 int pmap_fault_fixup(pmap_t, vm_offset_t, vm_prot_t, int);
229
230 /*
231 * Definitions for MMU domains
232 */
233 #define PMAP_DOMAINS 15 /* 15 'user' domains (1-15) */
234 #define PMAP_DOMAIN_KERNEL 0 /* The kernel uses domain #0 */
235
236 /*
237 * The new pmap ensures that page-tables are always mapping Write-Thru.
238 * Thus, on some platforms we can run fast and loose and avoid syncing PTEs
239 * on every change.
240 *
241 * Unfortunately, not all CPUs have a write-through cache mode. So we
242 * define PMAP_NEEDS_PTE_SYNC for C code to conditionally do PTE syncs,
243 * and if there is the chance for PTE syncs to be needed, we define
244 * PMAP_INCLUDE_PTE_SYNC so e.g. assembly code can include (and run)
245 * the code.
246 */
247 extern int pmap_needs_pte_sync;
248
249 /*
250 * These macros define the various bit masks in the PTE.
251 *
252 * We use these macros since we use different bits on different processor
253 * models.
254 */
255 #define L1_S_PROT_U (L1_S_AP(AP_U))
256 #define L1_S_PROT_W (L1_S_AP(AP_W))
257 #define L1_S_PROT_MASK (L1_S_PROT_U|L1_S_PROT_W)
258
259 #define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C)
260 #define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XSCALE_TEX(TEX_XSCALE_X)|\
261 L1_S_XSCALE_TEX(TEX_XSCALE_T))
262
263 #define L2_L_PROT_U (L2_AP(AP_U))
264 #define L2_L_PROT_W (L2_AP(AP_W))
265 #define L2_L_PROT_MASK (L2_L_PROT_U|L2_L_PROT_W)
266
267 #define L2_L_CACHE_MASK_generic (L2_B|L2_C)
268 #define L2_L_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_L_TEX(TEX_XSCALE_X) | \
269 L2_XSCALE_L_TEX(TEX_XSCALE_T))
270
271 #define L2_S_PROT_U_generic (L2_AP(AP_U))
272 #define L2_S_PROT_W_generic (L2_AP(AP_W))
273 #define L2_S_PROT_MASK_generic (L2_S_PROT_U|L2_S_PROT_W)
274
275 #define L2_S_PROT_U_xscale (L2_AP0(AP_U))
276 #define L2_S_PROT_W_xscale (L2_AP0(AP_W))
277 #define L2_S_PROT_MASK_xscale (L2_S_PROT_U|L2_S_PROT_W)
278
279 #define L2_S_CACHE_MASK_generic (L2_B|L2_C)
280 #define L2_S_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_T_TEX(TEX_XSCALE_X)| \
281 L2_XSCALE_T_TEX(TEX_XSCALE_X))
282
283 #define L1_S_PROTO_generic (L1_TYPE_S | L1_S_IMP)
284 #define L1_S_PROTO_xscale (L1_TYPE_S)
285
286 #define L1_C_PROTO_generic (L1_TYPE_C | L1_C_IMP2)
287 #define L1_C_PROTO_xscale (L1_TYPE_C)
288
289 #define L2_L_PROTO (L2_TYPE_L)
290
291 #define L2_S_PROTO_generic (L2_TYPE_S)
292 #define L2_S_PROTO_xscale (L2_TYPE_XSCALE_XS)
293
294 /*
295 * User-visible names for the ones that vary with MMU class.
296 */
297
298 #if ARM_NMMUS > 1
299 /* More than one MMU class configured; use variables. */
300 #define L2_S_PROT_U pte_l2_s_prot_u
301 #define L2_S_PROT_W pte_l2_s_prot_w
302 #define L2_S_PROT_MASK pte_l2_s_prot_mask
303
304 #define L1_S_CACHE_MASK pte_l1_s_cache_mask
305 #define L2_L_CACHE_MASK pte_l2_l_cache_mask
306 #define L2_S_CACHE_MASK pte_l2_s_cache_mask
307
308 #define L1_S_PROTO pte_l1_s_proto
309 #define L1_C_PROTO pte_l1_c_proto
310 #define L2_S_PROTO pte_l2_s_proto
311
312 #elif (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0
313 #define L2_S_PROT_U L2_S_PROT_U_generic
314 #define L2_S_PROT_W L2_S_PROT_W_generic
315 #define L2_S_PROT_MASK L2_S_PROT_MASK_generic
316
317 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic
318 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic
319 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic
320
321 #define L1_S_PROTO L1_S_PROTO_generic
322 #define L1_C_PROTO L1_C_PROTO_generic
323 #define L2_S_PROTO L2_S_PROTO_generic
324
325 #elif ARM_MMU_XSCALE == 1
326 #define L2_S_PROT_U L2_S_PROT_U_xscale
327 #define L2_S_PROT_W L2_S_PROT_W_xscale
328 #define L2_S_PROT_MASK L2_S_PROT_MASK_xscale
329
330 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_xscale
331 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_xscale
332 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_xscale
333
334 #define L1_S_PROTO L1_S_PROTO_xscale
335 #define L1_C_PROTO L1_C_PROTO_xscale
336 #define L2_S_PROTO L2_S_PROTO_xscale
337
338 #endif /* ARM_NMMUS > 1 */
339
340 #if (ARM_MMU_SA1 == 1) && (ARM_NMMUS == 1)
341 #define PMAP_NEEDS_PTE_SYNC 1
342 #define PMAP_INCLUDE_PTE_SYNC
343 #elif defined(CPU_XSCALE_81342)
344 #define PMAP_NEEDS_PTE_SYNC 1
345 #define PMAP_INCLUDE_PTE_SYNC
346 #elif (ARM_MMU_SA1 == 0)
347 #define PMAP_NEEDS_PTE_SYNC 0
348 #endif
349
350 /*
351 * These macros return various bits based on kernel/user and protection.
352 * Note that the compiler will usually fold these at compile time.
353 */
354 #define L1_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L1_S_PROT_U : 0) | \
355 (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : 0))
356
357 #define L2_L_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_L_PROT_U : 0) | \
358 (((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : 0))
359
360 #define L2_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \
361 (((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : 0))
362
363 /*
364 * Macros to test if a mapping is mappable with an L1 Section mapping
365 * or an L2 Large Page mapping.
366 */
367 #define L1_S_MAPPABLE_P(va, pa, size) \
368 ((((va) | (pa)) & L1_S_OFFSET) == 0 && (size) >= L1_S_SIZE)
369
370 #define L2_L_MAPPABLE_P(va, pa, size) \
371 ((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE)
372
373 /*
374 * Provide a fallback in case we were not able to determine it at
375 * compile-time.
376 */
377 #ifndef PMAP_NEEDS_PTE_SYNC
378 #define PMAP_NEEDS_PTE_SYNC pmap_needs_pte_sync
379 #define PMAP_INCLUDE_PTE_SYNC
380 #endif
381
382 #define PTE_SYNC(pte) \
383 do { \
384 if (PMAP_NEEDS_PTE_SYNC) { \
385 cpu_dcache_wb_range((vm_offset_t)(pte), sizeof(pt_entry_t));\
386 cpu_l2cache_wb_range((vm_offset_t)(pte), sizeof(pt_entry_t));\
387 } else \
388 cpu_drain_writebuf(); \
389 } while (/*CONSTCOND*/0)
390
391 #define PTE_SYNC_RANGE(pte, cnt) \
392 do { \
393 if (PMAP_NEEDS_PTE_SYNC) { \
394 cpu_dcache_wb_range((vm_offset_t)(pte), \
395 (cnt) << 2); /* * sizeof(pt_entry_t) */ \
396 cpu_l2cache_wb_range((vm_offset_t)(pte), \
397 (cnt) << 2); /* * sizeof(pt_entry_t) */ \
398 } else \
399 cpu_drain_writebuf(); \
400 } while (/*CONSTCOND*/0)
401
402 extern pt_entry_t pte_l1_s_cache_mode;
403 extern pt_entry_t pte_l1_s_cache_mask;
404
405 extern pt_entry_t pte_l2_l_cache_mode;
406 extern pt_entry_t pte_l2_l_cache_mask;
407
408 extern pt_entry_t pte_l2_s_cache_mode;
409 extern pt_entry_t pte_l2_s_cache_mask;
410
411 extern pt_entry_t pte_l1_s_cache_mode_pt;
412 extern pt_entry_t pte_l2_l_cache_mode_pt;
413 extern pt_entry_t pte_l2_s_cache_mode_pt;
414
415 extern pt_entry_t pte_l2_s_prot_u;
416 extern pt_entry_t pte_l2_s_prot_w;
417 extern pt_entry_t pte_l2_s_prot_mask;
418
419 extern pt_entry_t pte_l1_s_proto;
420 extern pt_entry_t pte_l1_c_proto;
421 extern pt_entry_t pte_l2_s_proto;
422
423 extern void (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t);
424 extern void (*pmap_copy_page_offs_func)(vm_paddr_t a_phys,
425 vm_offset_t a_offs, vm_paddr_t b_phys, vm_offset_t b_offs, int cnt);
426 extern void (*pmap_zero_page_func)(vm_paddr_t, int, int);
427
428 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 || defined(CPU_XSCALE_81342)
429 void pmap_copy_page_generic(vm_paddr_t, vm_paddr_t);
430 void pmap_zero_page_generic(vm_paddr_t, int, int);
431
432 void pmap_pte_init_generic(void);
433 #if defined(CPU_ARM8)
434 void pmap_pte_init_arm8(void);
435 #endif
436 #if defined(CPU_ARM9)
437 void pmap_pte_init_arm9(void);
438 #endif /* CPU_ARM9 */
439 #if defined(CPU_ARM10)
440 void pmap_pte_init_arm10(void);
441 #endif /* CPU_ARM10 */
442 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */
443
444 #if /* ARM_MMU_SA1 == */1
445 void pmap_pte_init_sa1(void);
446 #endif /* ARM_MMU_SA1 == 1 */
447
448 #if ARM_MMU_XSCALE == 1
449 void pmap_copy_page_xscale(vm_paddr_t, vm_paddr_t);
450 void pmap_zero_page_xscale(vm_paddr_t, int, int);
451
452 void pmap_pte_init_xscale(void);
453
454 void xscale_setup_minidata(vm_offset_t, vm_offset_t, vm_offset_t);
455
456 void pmap_use_minicache(vm_offset_t, vm_size_t);
457 #endif /* ARM_MMU_XSCALE == 1 */
458 #if defined(CPU_XSCALE_81342)
459 #define ARM_HAVE_SUPERSECTIONS
460 #endif
461
462 #define PTE_KERNEL 0
463 #define PTE_USER 1
464 #define l1pte_valid(pde) ((pde) != 0)
465 #define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S)
466 #define l1pte_page_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_C)
467 #define l1pte_fpage_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_F)
468
469 #define l2pte_index(v) (((v) & L2_ADDR_BITS) >> L2_S_SHIFT)
470 #define l2pte_valid(pte) ((pte) != 0)
471 #define l2pte_pa(pte) ((pte) & L2_S_FRAME)
472 #define l2pte_minidata(pte) (((pte) & \
473 (L2_B | L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X)))\
474 == (L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X)))
475
476 /* L1 and L2 page table macros */
477 #define pmap_pde_v(pde) l1pte_valid(*(pde))
478 #define pmap_pde_section(pde) l1pte_section_p(*(pde))
479 #define pmap_pde_page(pde) l1pte_page_p(*(pde))
480 #define pmap_pde_fpage(pde) l1pte_fpage_p(*(pde))
481
482 #define pmap_pte_v(pte) l2pte_valid(*(pte))
483 #define pmap_pte_pa(pte) l2pte_pa(*(pte))
484
485 /*
486 * Flags that indicate attributes of pages or mappings of pages.
487 *
488 * The PVF_MOD and PVF_REF flags are stored in the mdpage for each
489 * page. PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual
490 * pv_entry's for each page. They live in the same "namespace" so
491 * that we can clear multiple attributes at a time.
492 *
493 * Note the "non-cacheable" flag generally means the page has
494 * multiple mappings in a given address space.
495 */
496 #define PVF_MOD 0x01 /* page is modified */
497 #define PVF_REF 0x02 /* page is referenced */
498 #define PVF_WIRED 0x04 /* mapping is wired */
499 #define PVF_WRITE 0x08 /* mapping is writable */
500 #define PVF_EXEC 0x10 /* mapping is executable */
501 #define PVF_NC 0x20 /* mapping is non-cacheable */
502 #define PVF_MWC 0x40 /* mapping is used multiple times in userland */
503 #define PVF_UNMAN 0x80 /* mapping is unmanaged */
504
505 void vector_page_setprot(int);
506
507 void pmap_update(pmap_t);
508
509 /*
510 * This structure is used by machine-dependent code to describe
511 * static mappings of devices, created at bootstrap time.
512 */
513 struct pmap_devmap {
514 vm_offset_t pd_va; /* virtual address */
515 vm_paddr_t pd_pa; /* physical address */
516 vm_size_t pd_size; /* size of region */
517 vm_prot_t pd_prot; /* protection code */
518 int pd_cache; /* cache attributes */
519 };
520
521 const struct pmap_devmap *pmap_devmap_find_pa(vm_paddr_t, vm_size_t);
522 const struct pmap_devmap *pmap_devmap_find_va(vm_offset_t, vm_size_t);
523
524 void pmap_devmap_bootstrap(vm_offset_t, const struct pmap_devmap *);
525 void pmap_devmap_register(const struct pmap_devmap *);
526
527 #define SECTION_CACHE 0x1
528 #define SECTION_PT 0x2
529 void pmap_kenter_section(vm_offset_t, vm_paddr_t, int flags);
530 #ifdef ARM_HAVE_SUPERSECTIONS
531 void pmap_kenter_supersection(vm_offset_t, uint64_t, int flags);
532 #endif
533
534 extern char *_tmppt;
535
536 void pmap_postinit(void);
537
538 #ifdef ARM_USE_SMALL_ALLOC
539 void arm_add_smallalloc_pages(void *, void *, int, int);
540 vm_offset_t arm_ptovirt(vm_paddr_t);
541 void arm_init_smallalloc(void);
542 struct arm_small_page {
543 void *addr;
544 TAILQ_ENTRY(arm_small_page) pg_list;
545 };
546
547 #endif
548
549 #define ARM_NOCACHE_KVA_SIZE 0x1000000
550 extern vm_offset_t arm_nocache_startaddr;
551 void *arm_remap_nocache(void *, vm_size_t);
552 void arm_unmap_nocache(void *, vm_size_t);
553
554 extern vm_paddr_t dump_avail[];
555 #endif /* _KERNEL */
556
557 #endif /* !LOCORE */
558
559 #endif /* !_MACHINE_PMAP_H_ */
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