The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/arm/include/pte-v4.h

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    1 /*      $NetBSD: pte.h,v 1.1 2001/11/23 17:39:04 thorpej Exp $  */
    2 
    3 /*-
    4  * Copyright (c) 1994 Mark Brinicombe.
    5  * All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  * 3. All advertising materials mentioning features or use of this software
   16  *    must display the following acknowledgement:
   17  *      This product includes software developed by the RiscBSD team.
   18  * 4. The name "RiscBSD" nor the name of the author may be used to
   19  *    endorse or promote products derived from this software without specific
   20  *    prior written permission.
   21  *
   22  * THIS SOFTWARE IS PROVIDED BY RISCBSD ``AS IS'' AND ANY EXPRESS OR IMPLIED
   23  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
   24  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   25  * IN NO EVENT SHALL RISCBSD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
   26  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
   27  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
   28  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   32  * SUCH DAMAGE.
   33  *
   34  * $FreeBSD: releng/11.2/sys/arm/include/pte-v4.h 295801 2016-02-19 09:23:32Z skra $
   35  */
   36 
   37 #ifndef _MACHINE_PTE_V4_H_
   38 #define _MACHINE_PTE_V4_H_
   39 
   40 #ifndef LOCORE
   41 typedef uint32_t        pd_entry_t;             /* page directory entry */
   42 typedef uint32_t        pt_entry_t;             /* page table entry */
   43 typedef pt_entry_t      pt2_entry_t;            /* compatibility with v6 */
   44 #endif
   45 
   46 #define PG_FRAME        0xfffff000
   47 
   48 /* The PT_SIZE definition is misleading... A page table is only 0x400
   49  * bytes long. But since VM mapping can only be done to 0x1000 a single
   50  * 1KB blocks cannot be steered to a va by itself. Therefore the
   51  * pages tables are allocated in blocks of 4. i.e. if a 1 KB block
   52  * was allocated for a PT then the other 3KB would also get mapped
   53  * whenever the 1KB was mapped.
   54  */
   55 
   56 #define PT_RSIZE        0x0400          /* Real page table size */
   57 #define PT_SIZE         0x1000
   58 #define PD_SIZE         0x4000
   59 
   60 /* Page table types and masks */
   61 #define L1_PAGE         0x01    /* L1 page table mapping */
   62 #define L1_SECTION      0x02    /* L1 section mapping */
   63 #define L1_FPAGE        0x03    /* L1 fine page mapping */
   64 #define L1_MASK         0x03    /* Mask for L1 entry type */
   65 #define L2_LPAGE        0x01    /* L2 large page (64KB) */
   66 #define L2_SPAGE        0x02    /* L2 small page (4KB) */
   67 #define L2_MASK         0x03    /* Mask for L2 entry type */
   68 #define L2_INVAL        0x00    /* L2 invalid type */
   69 
   70 /*
   71  * The ARM MMU architecture was introduced with ARM v3 (previous ARM
   72  * architecture versions used an optional off-CPU memory controller
   73  * to perform address translation).
   74  *
   75  * The ARM MMU consists of a TLB and translation table walking logic.
   76  * There is typically one TLB per memory interface (or, put another
   77  * way, one TLB per software-visible cache).
   78  *
   79  * The ARM MMU is capable of mapping memory in the following chunks:
   80  *
   81  *      1M      Sections (L1 table)
   82  *
   83  *      64K     Large Pages (L2 table)
   84  *
   85  *      4K      Small Pages (L2 table)
   86  *
   87  *      1K      Tiny Pages (L2 table)
   88  *
   89  * There are two types of L2 tables: Coarse Tables and Fine Tables.
   90  * Coarse Tables can map Large and Small Pages.  Fine Tables can
   91  * map Tiny Pages.
   92  *
   93  * Coarse Tables can define 4 Subpages within Large and Small pages.
   94  * Subpages define different permissions for each Subpage within
   95  * a Page.
   96  *
   97  * Coarse Tables are 1K in length.  Fine tables are 4K in length.
   98  *
   99  * The Translation Table Base register holds the pointer to the
  100  * L1 Table.  The L1 Table is a 16K contiguous chunk of memory
  101  * aligned to a 16K boundary.  Each entry in the L1 Table maps
  102  * 1M of virtual address space, either via a Section mapping or
  103  * via an L2 Table.
  104  *
  105  * In addition, the Fast Context Switching Extension (FCSE) is available
  106  * on some ARM v4 and ARM v5 processors.  FCSE is a way of eliminating
  107  * TLB/cache flushes on context switch by use of a smaller address space
  108  * and a "process ID" that modifies the virtual address before being
  109  * presented to the translation logic.
  110  */
  111 
  112 /* ARMv6 super-sections. */
  113 #define L1_SUP_SIZE     0x01000000      /* 16M */
  114 #define L1_SUP_OFFSET   (L1_SUP_SIZE - 1)
  115 #define L1_SUP_FRAME    (~L1_SUP_OFFSET)
  116 #define L1_SUP_SHIFT    24
  117 
  118 #define L1_S_SIZE       0x00100000      /* 1M */
  119 #define L1_S_OFFSET     (L1_S_SIZE - 1)
  120 #define L1_S_FRAME      (~L1_S_OFFSET)
  121 #define L1_S_SHIFT      20
  122 
  123 #define L2_L_SIZE       0x00010000      /* 64K */
  124 #define L2_L_OFFSET     (L2_L_SIZE - 1)
  125 #define L2_L_FRAME      (~L2_L_OFFSET)
  126 #define L2_L_SHIFT      16
  127 
  128 #define L2_S_SIZE       0x00001000      /* 4K */
  129 #define L2_S_OFFSET     (L2_S_SIZE - 1)
  130 #define L2_S_FRAME      (~L2_S_OFFSET)
  131 #define L2_S_SHIFT      12
  132 
  133 #define L2_T_SIZE       0x00000400      /* 1K */
  134 #define L2_T_OFFSET     (L2_T_SIZE - 1)
  135 #define L2_T_FRAME      (~L2_T_OFFSET)
  136 #define L2_T_SHIFT      10
  137 
  138 /*
  139  * The NetBSD VM implementation only works on whole pages (4K),
  140  * whereas the ARM MMU's Coarse tables are sized in terms of 1K
  141  * (16K L1 table, 1K L2 table).
  142  *
  143  * So, we allocate L2 tables 4 at a time, thus yielding a 4K L2
  144  * table.
  145  */
  146 #define L1_TABLE_SIZE   0x4000          /* 16K */
  147 #define L2_TABLE_SIZE   0x1000          /* 4K */
  148 /*
  149  * The new pmap deals with the 1KB coarse L2 tables by
  150  * allocating them from a pool. Until every port has been converted,
  151  * keep the old L2_TABLE_SIZE define lying around. Converted ports
  152  * should use L2_TABLE_SIZE_REAL until then.
  153  */
  154 #define L2_TABLE_SIZE_REAL      0x400   /* 1K */
  155 
  156 /* Total number of page table entries in L2 table */
  157 #define L2_PTE_NUM_TOTAL        (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t))
  158 
  159 /*
  160  * ARM L1 Descriptors
  161  */
  162 
  163 #define L1_TYPE_INV     0x00            /* Invalid (fault) */
  164 #define L1_TYPE_C       0x01            /* Coarse L2 */
  165 #define L1_TYPE_S       0x02            /* Section */
  166 #define L1_TYPE_F       0x03            /* Fine L2 */
  167 #define L1_TYPE_MASK    0x03            /* mask of type bits */
  168 
  169 /* L1 Section Descriptor */
  170 #define L1_S_B          0x00000004      /* bufferable Section */
  171 #define L1_S_C          0x00000008      /* cacheable Section */
  172 #define L1_S_IMP        0x00000010      /* implementation defined */
  173 #define L1_S_XN         (1 << 4)        /* execute not */
  174 #define L1_S_DOM(x)     ((x) << 5)      /* domain */
  175 #define L1_S_DOM_MASK   L1_S_DOM(0xf)
  176 #define L1_S_AP(x)      ((x) << 10)     /* access permissions */
  177 #define L1_S_ADDR_MASK  0xfff00000      /* phys address of section */
  178 #define L1_S_TEX(x)     (((x) & 0x7) << 12)     /* Type Extension */
  179 #define L1_S_TEX_MASK   (0x7 << 12)     /* Type Extension */
  180 #define L1_S_APX        (1 << 15)
  181 #define L1_SHARED       (1 << 16)
  182 
  183 #define L1_S_XSCALE_P   0x00000200      /* ECC enable for this section */
  184 #define L1_S_XSCALE_TEX(x) ((x) << 12)  /* Type Extension */
  185 
  186 #define L1_S_SUPERSEC   ((1) << 18)     /* Section is a super-section. */
  187 
  188 /* L1 Coarse Descriptor */
  189 #define L1_C_IMP0       0x00000004      /* implementation defined */
  190 #define L1_C_IMP1       0x00000008      /* implementation defined */
  191 #define L1_C_IMP2       0x00000010      /* implementation defined */
  192 #define L1_C_DOM(x)     ((x) << 5)      /* domain */
  193 #define L1_C_DOM_MASK   L1_C_DOM(0xf)
  194 #define L1_C_ADDR_MASK  0xfffffc00      /* phys address of L2 Table */
  195 
  196 #define L1_C_XSCALE_P   0x00000200      /* ECC enable for this section */
  197 
  198 /* L1 Fine Descriptor */
  199 #define L1_F_IMP0       0x00000004      /* implementation defined */
  200 #define L1_F_IMP1       0x00000008      /* implementation defined */
  201 #define L1_F_IMP2       0x00000010      /* implementation defined */
  202 #define L1_F_DOM(x)     ((x) << 5)      /* domain */
  203 #define L1_F_DOM_MASK   L1_F_DOM(0xf)
  204 #define L1_F_ADDR_MASK  0xfffff000      /* phys address of L2 Table */
  205 
  206 #define L1_F_XSCALE_P   0x00000200      /* ECC enable for this section */
  207 
  208 /*
  209  * ARM L2 Descriptors
  210  */
  211 
  212 #define L2_TYPE_INV     0x00            /* Invalid (fault) */
  213 #define L2_TYPE_L       0x01            /* Large Page */
  214 #define L2_TYPE_S       0x02            /* Small Page */
  215 #define L2_TYPE_T       0x03            /* Tiny Page */
  216 #define L2_TYPE_MASK    0x03            /* mask of type bits */
  217 
  218         /*
  219          * This L2 Descriptor type is available on XScale processors
  220          * when using a Coarse L1 Descriptor.  The Extended Small
  221          * Descriptor has the same format as the XScale Tiny Descriptor,
  222          * but describes a 4K page, rather than a 1K page.
  223          */
  224 #define L2_TYPE_XSCALE_XS 0x03          /* XScale Extended Small Page */
  225 
  226 #define L2_B            0x00000004      /* Bufferable page */
  227 #define L2_C            0x00000008      /* Cacheable page */
  228 #define L2_AP0(x)       ((x) << 4)      /* access permissions (sp 0) */
  229 #define L2_AP1(x)       ((x) << 6)      /* access permissions (sp 1) */
  230 #define L2_AP2(x)       ((x) << 8)      /* access permissions (sp 2) */
  231 #define L2_AP3(x)       ((x) << 10)     /* access permissions (sp 3) */
  232 
  233 #define L2_SHARED       (1 << 10)
  234 #define L2_APX          (1 << 9)
  235 #define L2_XN           (1 << 0)
  236 #define L2_L_TEX_MASK   (0x7 << 12)     /* Type Extension */
  237 #define L2_L_TEX(x)     (((x) & 0x7) << 12)
  238 #define L2_S_TEX_MASK   (0x7 << 6)      /* Type Extension */
  239 #define L2_S_TEX(x)     (((x) & 0x7) << 6)
  240 
  241 #define L2_XSCALE_L_TEX(x) ((x) << 12)  /* Type Extension */
  242 #define L2_XSCALE_L_S(x)   (1 << 15)    /* Shared */
  243 #define L2_XSCALE_T_TEX(x) ((x) << 6)   /* Type Extension */
  244 
  245 /*
  246  * Access Permissions for L1 and L2 Descriptors.
  247  */
  248 #define AP_W            0x01            /* writable */
  249 #define AP_REF          0x01            /* referenced flag */
  250 #define AP_U            0x02            /* user */
  251 
  252 /*
  253  * Short-hand for common AP_* constants.
  254  *
  255  * Note: These values assume the S (System) bit is set and
  256  * the R (ROM) bit is clear in CP15 register 1.
  257  */
  258 #define AP_KR           0x00            /* kernel read */
  259 #define AP_KRW          0x01            /* kernel read/write */
  260 #define AP_KRWUR        0x02            /* kernel read/write usr read */
  261 #define AP_KRWURW       0x03            /* kernel read/write usr read/write */
  262 
  263 /*
  264  * Domain Types for the Domain Access Control Register.
  265  */
  266 #define DOMAIN_FAULT    0x00            /* no access */
  267 #define DOMAIN_CLIENT   0x01            /* client */
  268 #define DOMAIN_RESERVED 0x02            /* reserved */
  269 #define DOMAIN_MANAGER  0x03            /* manager */
  270 
  271 /*
  272  * Type Extension bits for XScale processors.
  273  *
  274  * Behavior of C and B when X == 0:
  275  *
  276  * C B  Cacheable  Bufferable  Write Policy  Line Allocate Policy
  277  * 0 0      N          N            -                 -
  278  * 0 1      N          Y            -                 -
  279  * 1 0      Y          Y       Write-through    Read Allocate
  280  * 1 1      Y          Y        Write-back      Read Allocate
  281  *
  282  * Behavior of C and B when X == 1:
  283  * C B  Cacheable  Bufferable  Write Policy  Line Allocate Policy
  284  * 0 0      -          -            -                 -           DO NOT USE
  285  * 0 1      N          Y            -                 -
  286  * 1 0  Mini-Data      -            -                 -
  287  * 1 1      Y          Y        Write-back       R/W Allocate
  288  */
  289 #define TEX_XSCALE_X    0x01            /* X modifies C and B */
  290 #define TEX_XSCALE_E    0x02
  291 #define TEX_XSCALE_T    0x04
  292 
  293 /* Xscale core 3 */
  294 
  295 /*
  296  *
  297  * Cache attributes with L2 present, S = 0
  298  * T E X C B   L1 i-cache L1 d-cache L1 DC WP  L2 cacheable write coalesce
  299  * 0 0 0 0 0    N         N             -       N               N
  300  * 0 0 0 0 1    N         N             -       N               Y
  301  * 0 0 0 1 0    Y         Y             WT      N               Y
  302  * 0 0 0 1 1    Y         Y             WB      Y               Y
  303  * 0 0 1 0 0    N         N             -       Y               Y
  304  * 0 0 1 0 1    N         N             -       N               N
  305  * 0 0 1 1 0    Y         Y             -       -               N
  306  * 0 0 1 1 1    Y         Y             WT      Y               Y
  307  * 0 1 0 0 0    N         N             -       N               N
  308  * 0 1 0 0 1    N/A     N/A             N/A     N/A             N/A
  309  * 0 1 0 1 0    N/A     N/A             N/A     N/A             N/A
  310  * 0 1 0 1 1    N/A     N/A             N/A     N/A             N/A
  311  * 0 1 1 X X    N/A     N/A             N/A     N/A             N/A
  312  * 1 X 0 0 0    N         N             -       N               Y
  313  * 1 X 0 0 1    Y         N             WB      N               Y
  314  * 1 X 0 1 0    Y         N             WT      N               Y
  315  * 1 X 0 1 1    Y         N             WB      Y               Y
  316  * 1 X 1 0 0    N         N             -       Y               Y
  317  * 1 X 1 0 1    Y         Y             WB      Y               Y
  318  * 1 X 1 1 0    Y         Y             WT      Y               Y
  319  * 1 X 1 1 1    Y         Y             WB      Y               Y
  320  *
  321  *
  322  *
  323  *
  324   * Cache attributes with L2 present, S = 1
  325  * T E X C B   L1 i-cache L1 d-cache L1 DC WP  L2 cacheable write coalesce
  326  * 0 0 0 0 0    N         N             -       N               N
  327  * 0 0 0 0 1    N         N             -       N               Y
  328  * 0 0 0 1 0    Y         Y             -       N               Y
  329  * 0 0 0 1 1    Y         Y             WT      Y               Y
  330  * 0 0 1 0 0    N         N             -       Y               Y
  331  * 0 0 1 0 1    N         N             -       N               N
  332  * 0 0 1 1 0    Y         Y             -       -               N
  333  * 0 0 1 1 1    Y         Y             WT      Y               Y
  334  * 0 1 0 0 0    N         N             -       N               N
  335  * 0 1 0 0 1    N/A     N/A             N/A     N/A             N/A
  336  * 0 1 0 1 0    N/A     N/A             N/A     N/A             N/A
  337  * 0 1 0 1 1    N/A     N/A             N/A     N/A             N/A
  338  * 0 1 1 X X    N/A     N/A             N/A     N/A             N/A
  339  * 1 X 0 0 0    N         N             -       N               Y
  340  * 1 X 0 0 1    Y         N             -       N               Y
  341  * 1 X 0 1 0    Y         N             -       N               Y
  342  * 1 X 0 1 1    Y         N             -       Y               Y
  343  * 1 X 1 0 0    N         N             -       Y               Y
  344  * 1 X 1 0 1    Y         Y             WT      Y               Y
  345  * 1 X 1 1 0    Y         Y             WT      Y               Y
  346  * 1 X 1 1 1    Y         Y             WT      Y               Y
  347  */
  348 #endif /* !_MACHINE_PTE_V4_H_ */
  349 
  350 /* End of pte.h */

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