FreeBSD/Linux Kernel Cross Reference
sys/arm/include/pte.h
1 /* $NetBSD: pte.h,v 1.1 2001/11/23 17:39:04 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 1994 Mark Brinicombe.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by the RiscBSD team.
18 * 4. The name "RiscBSD" nor the name of the author may be used to
19 * endorse or promote products derived from this software without specific
20 * prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY RISCBSD ``AS IS'' AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL RISCBSD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * $FreeBSD: releng/10.0/sys/arm/include/pte.h 254918 2013-08-26 17:12:30Z raj $
35 */
36
37 #ifndef _MACHINE_PTE_H_
38 #define _MACHINE_PTE_H_
39
40 #ifndef LOCORE
41 typedef uint32_t pd_entry_t; /* page directory entry */
42 typedef uint32_t pt_entry_t; /* page table entry */
43 #endif
44
45 #define PG_FRAME 0xfffff000
46
47 /* The PT_SIZE definition is misleading... A page table is only 0x400
48 * bytes long. But since VM mapping can only be done to 0x1000 a single
49 * 1KB blocks cannot be steered to a va by itself. Therefore the
50 * pages tables are allocated in blocks of 4. i.e. if a 1 KB block
51 * was allocated for a PT then the other 3KB would also get mapped
52 * whenever the 1KB was mapped.
53 */
54
55 #define PT_RSIZE 0x0400 /* Real page table size */
56 #define PT_SIZE 0x1000
57 #define PD_SIZE 0x4000
58
59 /* Page table types and masks */
60 #define L1_PAGE 0x01 /* L1 page table mapping */
61 #define L1_SECTION 0x02 /* L1 section mapping */
62 #define L1_FPAGE 0x03 /* L1 fine page mapping */
63 #define L1_MASK 0x03 /* Mask for L1 entry type */
64 #define L2_LPAGE 0x01 /* L2 large page (64KB) */
65 #define L2_SPAGE 0x02 /* L2 small page (4KB) */
66 #define L2_MASK 0x03 /* Mask for L2 entry type */
67 #define L2_INVAL 0x00 /* L2 invalid type */
68
69 /* L1 and L2 address masks */
70 #define L1_ADDR_MASK 0xfffffc00
71 #define L2_ADDR_MASK 0xfffff000
72
73 /*
74 * The ARM MMU architecture was introduced with ARM v3 (previous ARM
75 * architecture versions used an optional off-CPU memory controller
76 * to perform address translation).
77 *
78 * The ARM MMU consists of a TLB and translation table walking logic.
79 * There is typically one TLB per memory interface (or, put another
80 * way, one TLB per software-visible cache).
81 *
82 * The ARM MMU is capable of mapping memory in the following chunks:
83 *
84 * 1M Sections (L1 table)
85 *
86 * 64K Large Pages (L2 table)
87 *
88 * 4K Small Pages (L2 table)
89 *
90 * 1K Tiny Pages (L2 table)
91 *
92 * There are two types of L2 tables: Coarse Tables and Fine Tables.
93 * Coarse Tables can map Large and Small Pages. Fine Tables can
94 * map Tiny Pages.
95 *
96 * Coarse Tables can define 4 Subpages within Large and Small pages.
97 * Subpages define different permissions for each Subpage within
98 * a Page.
99 *
100 * Coarse Tables are 1K in length. Fine tables are 4K in length.
101 *
102 * The Translation Table Base register holds the pointer to the
103 * L1 Table. The L1 Table is a 16K contiguous chunk of memory
104 * aligned to a 16K boundary. Each entry in the L1 Table maps
105 * 1M of virtual address space, either via a Section mapping or
106 * via an L2 Table.
107 *
108 * In addition, the Fast Context Switching Extension (FCSE) is available
109 * on some ARM v4 and ARM v5 processors. FCSE is a way of eliminating
110 * TLB/cache flushes on context switch by use of a smaller address space
111 * and a "process ID" that modifies the virtual address before being
112 * presented to the translation logic.
113 */
114
115 /* ARMv6 super-sections. */
116 #define L1_SUP_SIZE 0x01000000 /* 16M */
117 #define L1_SUP_OFFSET (L1_SUP_SIZE - 1)
118 #define L1_SUP_FRAME (~L1_SUP_OFFSET)
119 #define L1_SUP_SHIFT 24
120
121 #define L1_S_SIZE 0x00100000 /* 1M */
122 #define L1_S_OFFSET (L1_S_SIZE - 1)
123 #define L1_S_FRAME (~L1_S_OFFSET)
124 #define L1_S_SHIFT 20
125
126 #define L2_L_SIZE 0x00010000 /* 64K */
127 #define L2_L_OFFSET (L2_L_SIZE - 1)
128 #define L2_L_FRAME (~L2_L_OFFSET)
129 #define L2_L_SHIFT 16
130
131 #define L2_S_SIZE 0x00001000 /* 4K */
132 #define L2_S_OFFSET (L2_S_SIZE - 1)
133 #define L2_S_FRAME (~L2_S_OFFSET)
134 #define L2_S_SHIFT 12
135
136 #define L2_T_SIZE 0x00000400 /* 1K */
137 #define L2_T_OFFSET (L2_T_SIZE - 1)
138 #define L2_T_FRAME (~L2_T_OFFSET)
139 #define L2_T_SHIFT 10
140
141 /*
142 * The NetBSD VM implementation only works on whole pages (4K),
143 * whereas the ARM MMU's Coarse tables are sized in terms of 1K
144 * (16K L1 table, 1K L2 table).
145 *
146 * So, we allocate L2 tables 4 at a time, thus yielding a 4K L2
147 * table.
148 */
149 #define L1_ADDR_BITS 0xfff00000 /* L1 PTE address bits */
150 #define L2_ADDR_BITS 0x000ff000 /* L2 PTE address bits */
151
152 #define L1_TABLE_SIZE 0x4000 /* 16K */
153 #define L2_TABLE_SIZE 0x1000 /* 4K */
154 /*
155 * The new pmap deals with the 1KB coarse L2 tables by
156 * allocating them from a pool. Until every port has been converted,
157 * keep the old L2_TABLE_SIZE define lying around. Converted ports
158 * should use L2_TABLE_SIZE_REAL until then.
159 */
160 #define L2_TABLE_SIZE_REAL 0x400 /* 1K */
161
162 /* Total number of page table entries in L2 table */
163 #define L2_PTE_NUM_TOTAL (L2_TABLE_SIZE_REAL / sizeof(pt_entry_t))
164
165 /*
166 * ARM L1 Descriptors
167 */
168
169 #define L1_TYPE_INV 0x00 /* Invalid (fault) */
170 #define L1_TYPE_C 0x01 /* Coarse L2 */
171 #define L1_TYPE_S 0x02 /* Section */
172 #define L1_TYPE_F 0x03 /* Fine L2 */
173 #define L1_TYPE_MASK 0x03 /* mask of type bits */
174
175 /* L1 Section Descriptor */
176 #define L1_S_B 0x00000004 /* bufferable Section */
177 #define L1_S_C 0x00000008 /* cacheable Section */
178 #define L1_S_IMP 0x00000010 /* implementation defined */
179 #define L1_S_XN (1 << 4) /* execute not */
180 #define L1_S_DOM(x) ((x) << 5) /* domain */
181 #define L1_S_DOM_MASK L1_S_DOM(0xf)
182 #define L1_S_AP(x) ((x) << 10) /* access permissions */
183 #define L1_S_ADDR_MASK 0xfff00000 /* phys address of section */
184 #define L1_S_TEX(x) (((x) & 0x7) << 12) /* Type Extension */
185 #define L1_S_TEX_MASK (0x7 << 12) /* Type Extension */
186 #define L1_S_APX (1 << 15)
187 #define L1_SHARED (1 << 16)
188
189 #define L1_S_XSCALE_P 0x00000200 /* ECC enable for this section */
190 #define L1_S_XSCALE_TEX(x) ((x) << 12) /* Type Extension */
191
192 #define L1_S_SUPERSEC ((1) << 18) /* Section is a super-section. */
193
194 /* L1 Coarse Descriptor */
195 #define L1_C_IMP0 0x00000004 /* implementation defined */
196 #define L1_C_IMP1 0x00000008 /* implementation defined */
197 #define L1_C_IMP2 0x00000010 /* implementation defined */
198 #define L1_C_DOM(x) ((x) << 5) /* domain */
199 #define L1_C_DOM_MASK L1_C_DOM(0xf)
200 #define L1_C_ADDR_MASK 0xfffffc00 /* phys address of L2 Table */
201
202 #define L1_C_XSCALE_P 0x00000200 /* ECC enable for this section */
203
204 /* L1 Fine Descriptor */
205 #define L1_F_IMP0 0x00000004 /* implementation defined */
206 #define L1_F_IMP1 0x00000008 /* implementation defined */
207 #define L1_F_IMP2 0x00000010 /* implementation defined */
208 #define L1_F_DOM(x) ((x) << 5) /* domain */
209 #define L1_F_DOM_MASK L1_F_DOM(0xf)
210 #define L1_F_ADDR_MASK 0xfffff000 /* phys address of L2 Table */
211
212 #define L1_F_XSCALE_P 0x00000200 /* ECC enable for this section */
213
214 /*
215 * ARM L2 Descriptors
216 */
217
218 #define L2_TYPE_INV 0x00 /* Invalid (fault) */
219 #define L2_TYPE_L 0x01 /* Large Page */
220 #define L2_TYPE_S 0x02 /* Small Page */
221 #define L2_TYPE_T 0x03 /* Tiny Page */
222 #define L2_TYPE_MASK 0x03 /* mask of type bits */
223
224 /*
225 * This L2 Descriptor type is available on XScale processors
226 * when using a Coarse L1 Descriptor. The Extended Small
227 * Descriptor has the same format as the XScale Tiny Descriptor,
228 * but describes a 4K page, rather than a 1K page.
229 */
230 #define L2_TYPE_XSCALE_XS 0x03 /* XScale Extended Small Page */
231
232 #define L2_B 0x00000004 /* Bufferable page */
233 #define L2_C 0x00000008 /* Cacheable page */
234 #define L2_AP0(x) ((x) << 4) /* access permissions (sp 0) */
235 #define L2_AP1(x) ((x) << 6) /* access permissions (sp 1) */
236 #define L2_AP2(x) ((x) << 8) /* access permissions (sp 2) */
237 #define L2_AP3(x) ((x) << 10) /* access permissions (sp 3) */
238
239 #define L2_SHARED (1 << 10)
240 #define L2_APX (1 << 9)
241 #define L2_XN (1 << 0)
242 #define L2_L_TEX_MASK (0x7 << 12) /* Type Extension */
243 #define L2_L_TEX(x) (((x) & 0x7) << 12)
244 #define L2_S_TEX_MASK (0x7 << 6) /* Type Extension */
245 #define L2_S_TEX(x) (((x) & 0x7) << 6)
246
247 #define L2_XSCALE_L_TEX(x) ((x) << 12) /* Type Extension */
248 #define L2_XSCALE_L_S(x) (1 << 15) /* Shared */
249 #define L2_XSCALE_T_TEX(x) ((x) << 6) /* Type Extension */
250
251 /*
252 * Access Permissions for L1 and L2 Descriptors.
253 */
254 #define AP_W 0x01 /* writable */
255 #define AP_REF 0x01 /* referenced flag */
256 #define AP_U 0x02 /* user */
257
258 /*
259 * Short-hand for common AP_* constants.
260 *
261 * Note: These values assume the S (System) bit is set and
262 * the R (ROM) bit is clear in CP15 register 1.
263 */
264 #define AP_KR 0x00 /* kernel read */
265 #define AP_KRW 0x01 /* kernel read/write */
266 #define AP_KRWUR 0x02 /* kernel read/write usr read */
267 #define AP_KRWURW 0x03 /* kernel read/write usr read/write */
268
269 /*
270 * Domain Types for the Domain Access Control Register.
271 */
272 #define DOMAIN_FAULT 0x00 /* no access */
273 #define DOMAIN_CLIENT 0x01 /* client */
274 #define DOMAIN_RESERVED 0x02 /* reserved */
275 #define DOMAIN_MANAGER 0x03 /* manager */
276
277 /*
278 * Type Extension bits for XScale processors.
279 *
280 * Behavior of C and B when X == 0:
281 *
282 * C B Cacheable Bufferable Write Policy Line Allocate Policy
283 * 0 0 N N - -
284 * 0 1 N Y - -
285 * 1 0 Y Y Write-through Read Allocate
286 * 1 1 Y Y Write-back Read Allocate
287 *
288 * Behavior of C and B when X == 1:
289 * C B Cacheable Bufferable Write Policy Line Allocate Policy
290 * 0 0 - - - - DO NOT USE
291 * 0 1 N Y - -
292 * 1 0 Mini-Data - - -
293 * 1 1 Y Y Write-back R/W Allocate
294 */
295 #define TEX_XSCALE_X 0x01 /* X modifies C and B */
296 #define TEX_XSCALE_E 0x02
297 #define TEX_XSCALE_T 0x04
298
299 /* Xscale core 3 */
300
301 /*
302 *
303 * Cache attributes with L2 present, S = 0
304 * T E X C B L1 i-cache L1 d-cache L1 DC WP L2 cacheable write coalesce
305 * 0 0 0 0 0 N N - N N
306 * 0 0 0 0 1 N N - N Y
307 * 0 0 0 1 0 Y Y WT N Y
308 * 0 0 0 1 1 Y Y WB Y Y
309 * 0 0 1 0 0 N N - Y Y
310 * 0 0 1 0 1 N N - N N
311 * 0 0 1 1 0 Y Y - - N
312 * 0 0 1 1 1 Y Y WT Y Y
313 * 0 1 0 0 0 N N - N N
314 * 0 1 0 0 1 N/A N/A N/A N/A N/A
315 * 0 1 0 1 0 N/A N/A N/A N/A N/A
316 * 0 1 0 1 1 N/A N/A N/A N/A N/A
317 * 0 1 1 X X N/A N/A N/A N/A N/A
318 * 1 X 0 0 0 N N - N Y
319 * 1 X 0 0 1 Y N WB N Y
320 * 1 X 0 1 0 Y N WT N Y
321 * 1 X 0 1 1 Y N WB Y Y
322 * 1 X 1 0 0 N N - Y Y
323 * 1 X 1 0 1 Y Y WB Y Y
324 * 1 X 1 1 0 Y Y WT Y Y
325 * 1 X 1 1 1 Y Y WB Y Y
326 *
327 *
328 *
329 *
330 * Cache attributes with L2 present, S = 1
331 * T E X C B L1 i-cache L1 d-cache L1 DC WP L2 cacheable write coalesce
332 * 0 0 0 0 0 N N - N N
333 * 0 0 0 0 1 N N - N Y
334 * 0 0 0 1 0 Y Y - N Y
335 * 0 0 0 1 1 Y Y WT Y Y
336 * 0 0 1 0 0 N N - Y Y
337 * 0 0 1 0 1 N N - N N
338 * 0 0 1 1 0 Y Y - - N
339 * 0 0 1 1 1 Y Y WT Y Y
340 * 0 1 0 0 0 N N - N N
341 * 0 1 0 0 1 N/A N/A N/A N/A N/A
342 * 0 1 0 1 0 N/A N/A N/A N/A N/A
343 * 0 1 0 1 1 N/A N/A N/A N/A N/A
344 * 0 1 1 X X N/A N/A N/A N/A N/A
345 * 1 X 0 0 0 N N - N Y
346 * 1 X 0 0 1 Y N - N Y
347 * 1 X 0 1 0 Y N - N Y
348 * 1 X 0 1 1 Y N - Y Y
349 * 1 X 1 0 0 N N - Y Y
350 * 1 X 1 0 1 Y Y WT Y Y
351 * 1 X 1 1 0 Y Y WT Y Y
352 * 1 X 1 1 1 Y Y WT Y Y
353 */
354 #endif /* !_MACHINE_PTE_H_ */
355
356 /* End of pte.h */
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