The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/include/sysreg.h

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    1 /*-
    2  * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
    3  * Copyright 2014 Michal Meloun <meloun@miracle.cz>
    4  * All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  *
   15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   18  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   25  * SUCH DAMAGE.
   26  *
   27  * $FreeBSD: releng/10.2/sys/arm/include/sysreg.h 278684 2015-02-13 17:53:11Z ian $
   28  */
   29 
   30 /*
   31  * Macros to make working with the System Control Registers simpler.
   32  *
   33  * Note that when register r0 is hard-coded in these definitions it means the
   34  * cp15 operation neither reads nor writes the register, and r0 is used only
   35  * because some syntatically-valid register name has to appear at that point to
   36  * keep the asm parser happy.
   37  */
   38 
   39 #ifndef MACHINE_SYSREG_H
   40 #define MACHINE_SYSREG_H
   41 
   42 #include <machine/acle-compat.h>
   43 
   44 /*
   45  * CP15 C0 registers
   46  */
   47 #define CP15_MIDR(rr)           p15, 0, rr, c0, c0,  0 /* Main ID Register */
   48 #define CP15_CTR(rr)            p15, 0, rr, c0, c0,  1 /* Cache Type Register */
   49 #define CP15_TCMTR(rr)          p15, 0, rr, c0, c0,  2 /* TCM Type Register */
   50 #define CP15_TLBTR(rr)          p15, 0, rr, c0, c0,  3 /* TLB Type Register */
   51 #define CP15_MPIDR(rr)          p15, 0, rr, c0, c0,  5 /* Multiprocessor Affinity Register */
   52 #define CP15_REVIDR(rr)         p15, 0, rr, c0, c0,  6 /* Revision ID Register */
   53 
   54 #define CP15_ID_PFR0(rr)        p15, 0, rr, c0, c1,  0 /* Processor Feature Register 0 */
   55 #define CP15_ID_PFR1(rr)        p15, 0, rr, c0, c1,  1 /* Processor Feature Register 1 */
   56 #define CP15_ID_DFR0(rr)        p15, 0, rr, c0, c1,  2 /* Debug Feature Register 0 */
   57 #define CP15_ID_AFR0(rr)        p15, 0, rr, c0, c1,  3 /* Auxiliary Feature Register  0 */
   58 #define CP15_ID_MMFR0(rr)       p15, 0, rr, c0, c1,  4 /* Memory Model Feature Register 0 */
   59 #define CP15_ID_MMFR1(rr)       p15, 0, rr, c0, c1,  5 /* Memory Model Feature Register 1 */
   60 #define CP15_ID_MMFR2(rr)       p15, 0, rr, c0, c1,  6 /* Memory Model Feature Register 2 */
   61 #define CP15_ID_MMFR3(rr)       p15, 0, rr, c0, c1,  7 /* Memory Model Feature Register 3 */
   62 
   63 #define CP15_ID_ISAR0(rr)       p15, 0, rr, c0, c2,  0 /* Instruction Set Attribute Register 0 */
   64 #define CP15_ID_ISAR1(rr)       p15, 0, rr, c0, c2,  1 /* Instruction Set Attribute Register 1 */
   65 #define CP15_ID_ISAR2(rr)       p15, 0, rr, c0, c2,  2 /* Instruction Set Attribute Register 2 */
   66 #define CP15_ID_ISAR3(rr)       p15, 0, rr, c0, c2,  3 /* Instruction Set Attribute Register 3 */
   67 #define CP15_ID_ISAR4(rr)       p15, 0, rr, c0, c2,  4 /* Instruction Set Attribute Register 4 */
   68 #define CP15_ID_ISAR5(rr)       p15, 0, rr, c0, c2,  5 /* Instruction Set Attribute Register 5 */
   69 
   70 #define CP15_CCSIDR(rr)         p15, 1, rr, c0, c0,  0 /* Cache Size ID Registers */
   71 #define CP15_CLIDR(rr)          p15, 1, rr, c0, c0,  1 /* Cache Level ID Register */
   72 #define CP15_AIDR(rr)           p15, 1, rr, c0, c0,  7 /* Auxiliary ID Register */
   73 
   74 #define CP15_CSSELR(rr)         p15, 2, rr, c0, c0,  0 /* Cache Size Selection Register */
   75 
   76 /*
   77  * CP15 C1 registers
   78  */
   79 #define CP15_SCTLR(rr)          p15, 0, rr, c1, c0,  0 /* System Control Register */
   80 #define CP15_ACTLR(rr)          p15, 0, rr, c1, c0,  1 /* IMPLEMENTATION DEFINED Auxiliary Control Register */
   81 #define CP15_CPACR(rr)          p15, 0, rr, c1, c0,  2 /* Coprocessor Access Control Register */
   82 
   83 #define CP15_SCR(rr)            p15, 0, rr, c1, c1,  0 /* Secure Configuration Register */
   84 #define CP15_SDER(rr)           p15, 0, rr, c1, c1,  1 /* Secure Debug Enable Register */
   85 #define CP15_NSACR(rr)          p15, 0, rr, c1, c1,  2 /* Non-Secure Access Control Register */
   86 
   87 /*
   88  * CP15 C2 registers
   89  */
   90 #define CP15_TTBR0(rr)          p15, 0, rr, c2, c0,  0 /* Translation Table Base Register 0 */
   91 #define CP15_TTBR1(rr)          p15, 0, rr, c2, c0,  1 /* Translation Table Base Register 1 */
   92 #define CP15_TTBCR(rr)          p15, 0, rr, c2, c0,  2 /* Translation Table Base Control Register */
   93 
   94 /*
   95  * CP15 C3 registers
   96  */
   97 #define CP15_DACR(rr)           p15, 0, rr, c3, c0,  0 /* Domain Access Control Register */
   98 
   99 /*
  100  * CP15 C5 registers
  101  */
  102 #define CP15_DFSR(rr)           p15, 0, rr, c5, c0,  0 /* Data Fault Status Register */
  103 
  104 #if __ARM_ARCH >= 6
  105 /* From ARMv6: */
  106 #define CP15_IFSR(rr)           p15, 0, rr, c5, c0,  1 /* Instruction Fault Status Register */
  107 #endif
  108 #if __ARM_ARCH >= 7
  109 /* From ARMv7: */
  110 #define CP15_ADFSR(rr)          p15, 0, rr, c5, c1,  0 /* Auxiliary Data Fault Status Register */
  111 #define CP15_AIFSR(rr)          p15, 0, rr, c5, c1,  1 /* Auxiliary Instruction Fault Status Register */
  112 #endif
  113 
  114 /*
  115  * CP15 C6 registers
  116  */
  117 #define CP15_DFAR(rr)           p15, 0, rr, c6, c0,  0 /* Data Fault Address Register */
  118 
  119 #if __ARM_ARCH >= 6
  120 /* From ARMv6k: */
  121 #define CP15_IFAR(rr)           p15, 0, rr, c6, c0,  2 /* Instruction Fault Address Register */
  122 #endif
  123 
  124 /*
  125  * CP15 C7 registers
  126  */
  127 #if __ARM_ARCH >= 7 && defined(SMP)
  128 /* From ARMv7: */
  129 #define CP15_ICIALLUIS          p15, 0, r0, c7, c1,  0 /* Instruction cache invalidate all PoU, IS */
  130 #define CP15_BPIALLIS           p15, 0, r0, c7, c1,  6 /* Branch predictor invalidate all IS */
  131 #endif
  132 
  133 #define CP15_PAR                p15, 0, r0, c7, c4,  0 /* Physical Address Register */
  134 
  135 #define CP15_ICIALLU            p15, 0, r0, c7, c5,  0 /* Instruction cache invalidate all PoU */
  136 #define CP15_ICIMVAU(rr)        p15, 0, rr, c7, c5,  1 /* Instruction cache invalidate */
  137 #if __ARM_ARCH == 6
  138 /* Deprecated in ARMv7 */
  139 #define CP15_CP15ISB            p15, 0, r0, c7, c5,  4 /* ISB */
  140 #endif
  141 #define CP15_BPIALL             p15, 0, r0, c7, c5,  6 /* Branch predictor invalidate all */
  142 #define CP15_BPIMVA             p15, 0, rr, c7, c5,  7 /* Branch predictor invalidate by MVA */
  143 
  144 #if __ARM_ARCH == 6
  145 /* Only ARMv6: */
  146 #define CP15_DCIALL             p15, 0, r0, c7, c6,  0 /* Data cache invalidate all */
  147 #endif
  148 #define CP15_DCIMVAC(rr)        p15, 0, rr, c7, c6,  1 /* Data cache invalidate by MVA PoC */
  149 #define CP15_DCISW(rr)          p15, 0, rr, c7, c6,  2 /* Data cache invalidate by set/way */
  150 
  151 #define CP15_ATS1CPR(rr)        p15, 0, rr, c7, c8,  0 /* Stage 1 Current state PL1 read */
  152 #define CP15_ATS1CPW(rr)        p15, 0, rr, c7, c8,  1 /* Stage 1 Current state PL1 write */
  153 #define CP15_ATS1CUR(rr)        p15, 0, rr, c7, c8,  2 /* Stage 1 Current state unprivileged read */
  154 #define CP15_ATS1CUW(rr)        p15, 0, rr, c7, c8,  3 /* Stage 1 Current state unprivileged write */
  155 
  156 #if __ARM_ARCH >= 7
  157 /* From ARMv7: */
  158 #define CP15_ATS12NSOPR(rr)     p15, 0, rr, c7, c8,  4 /* Stages 1 and 2 Non-secure only PL1 read */
  159 #define CP15_ATS12NSOPW(rr)     p15, 0, rr, c7, c8,  5 /* Stages 1 and 2 Non-secure only PL1 write */
  160 #define CP15_ATS12NSOUR(rr)     p15, 0, rr, c7, c8,  6 /* Stages 1 and 2 Non-secure only unprivileged read */
  161 #define CP15_ATS12NSOUW(rr)     p15, 0, rr, c7, c8,  7 /* Stages 1 and 2 Non-secure only unprivileged write */
  162 #endif
  163 
  164 #if __ARM_ARCH == 6
  165 /* Only ARMv6: */
  166 #define CP15_DCCALL             p15, 0, r0, c7, c10, 0 /* Data cache clean all */
  167 #endif
  168 #define CP15_DCCMVAC(rr)        p15, 0, rr, c7, c10, 1 /* Data cache clean by MVA PoC */
  169 #define CP15_DCCSW(rr)          p15, 0, rr, c7, c10, 2 /* Data cache clean by set/way */
  170 #if __ARM_ARCH == 6
  171 /* Only ARMv6: */
  172 #define CP15_CP15DSB            p15, 0, r0, c7, c10, 4 /* DSB */
  173 #define CP15_CP15DMB            p15, 0, r0, c7, c10, 5 /* DMB */
  174 #define CP15_CP15WFI            p15, 0, r0, c7, c0,  4 /* WFI */
  175 #endif
  176 
  177 #if __ARM_ARCH >= 7
  178 /* From ARMv7: */
  179 #define CP15_DCCMVAU(rr)        p15, 0, rr, c7, c11, 1 /* Data cache clean by MVA PoU */
  180 #endif
  181 
  182 #if __ARM_ARCH == 6
  183 /* Only ARMv6: */
  184 #define CP15_DCCIALL            p15, 0, r0, c7, c14, 0 /* Data cache clean and invalidate all */
  185 #endif
  186 #define CP15_DCCIMVAC(rr)       p15, 0, rr, c7, c14, 1 /* Data cache clean and invalidate by MVA PoC */
  187 #define CP15_DCCISW(rr)         p15, 0, rr, c7, c14, 2 /* Data cache clean and invalidate by set/way */
  188 
  189 /*
  190  * CP15 C8 registers
  191  */
  192 #if __ARM_ARCH >= 7 && defined(SMP)
  193 /* From ARMv7: */
  194 #define CP15_TLBIALLIS          p15, 0, r0, c8, c3, 0 /* Invalidate entire unified TLB IS */
  195 #define CP15_TLBIMVAIS(rr)      p15, 0, rr, c8, c3, 1 /* Invalidate unified TLB by MVA IS */
  196 #define CP15_TLBIASIDIS(rr)     p15, 0, rr, c8, c3, 2 /* Invalidate unified TLB by ASID IS */
  197 #define CP15_TLBIMVAAIS(rr)     p15, 0, rr, c8, c3, 3 /* Invalidate unified TLB by MVA, all ASID IS */
  198 #endif
  199 
  200 #define CP15_TLBIALL            p15, 0, r0, c8, c7, 0 /* Invalidate entire unified TLB */
  201 #define CP15_TLBIMVA(rr)        p15, 0, rr, c8, c7, 1 /* Invalidate unified TLB by MVA */
  202 #define CP15_TLBIASID(rr)       p15, 0, rr, c8, c7, 2 /* Invalidate unified TLB by ASID */
  203 
  204 #if __ARM_ARCH >= 6
  205 /* From ARMv6: */
  206 #define CP15_TLBIMVAA(rr)       p15, 0, rr, c8, c7, 3 /* Invalidate unified TLB by MVA, all ASID */
  207 #endif
  208 
  209 /*
  210  * CP15 C9 registers
  211  */
  212 #if __ARM_ARCH == 6 && defined(CPU_ARM1176)
  213 #define CP15_PMCCNTR(rr)        p15, 0, rr, c15, c12, 1 /* PM Cycle Count Register */
  214 #elif __ARM_ARCH > 6
  215 #define CP15_PMCR(rr)           p15, 0, rr,  c9, c12, 0 /* Performance Monitor Control Register */
  216 #define CP15_PMCNTENSET(rr)     p15, 0, rr,  c9, c12, 1 /* PM Count Enable Set Register */
  217 #define CP15_PMCNTENCLR(rr)     p15, 0, rr,  c9, c12, 2 /* PM Count Enable Clear Register */
  218 #define CP15_PMOVSR(rr)         p15, 0, rr,  c9, c12, 3 /* PM Overflow Flag Status Register */
  219 #define CP15_PMSWINC(rr)        p15, 0, rr,  c9, c12, 4 /* PM Software Increment Register */
  220 #define CP15_PMSELR(rr)         p15, 0, rr,  c9, c12, 5 /* PM Event Counter Selection Register */
  221 #define CP15_PMCCNTR(rr)        p15, 0, rr,  c9, c13, 0 /* PM Cycle Count Register */
  222 #define CP15_PMXEVTYPER(rr)     p15, 0, rr,  c9, c13, 1 /* PM Event Type Select Register */
  223 #define CP15_PMXEVCNTRR(rr)     p15, 0, rr,  c9, c13, 2 /* PM Event Count Register */
  224 #define CP15_PMUSERENR(rr)      p15, 0, rr,  c9, c14, 0 /* PM User Enable Register */
  225 #define CP15_PMINTENSET(rr)     p15, 0, rr,  c9, c14, 1 /* PM Interrupt Enable Set Register */
  226 #define CP15_PMINTENCLR(rr)     p15, 0, rr,  c9, c14, 2 /* PM Interrupt Enable Clear Register */
  227 #endif
  228 
  229 /*
  230  * CP15 C10 registers
  231  */
  232 /* Without LPAE this is PRRR, with LPAE it's MAIR0 */
  233 #define CP15_PRRR(rr)           p15, 0, rr, c10, c2, 0 /* Primary Region Remap Register */
  234 #define CP15_MAIR0(rr)          p15, 0, rr, c10, c2, 0 /* Memory Attribute Indirection Register 0 */
  235 /* Without LPAE this is NMRR, with LPAE it's MAIR1 */
  236 #define CP15_NMRR(rr)           p15, 0, rr, c10, c2, 1 /* Normal Memory Remap Register */
  237 #define CP15_MAIR1(rr)          p15, 0, rr, c10, c2, 1 /* Memory Attribute Indirection Register 1 */
  238 
  239 #define CP15_AMAIR0(rr)         p15, 0, rr, c10, c3, 0 /* Auxiliary Memory Attribute Indirection Register 0 */
  240 #define CP15_AMAIR1(rr)         p15, 0, rr, c10, c3, 1 /* Auxiliary Memory Attribute Indirection Register 1 */
  241 
  242 /*
  243  * CP15 C12 registers
  244  */
  245 #define CP15_VBAR(rr)           p15, 0, rr, c12, c0, 0 /* Vector Base Address Register */
  246 #define CP15_MVBAR(rr)          p15, 0, rr, c12, c0, 1 /* Monitor Vector Base Address Register */
  247 
  248 #define CP15_ISR(rr)            p15, 0, rr, c12, c1, 0 /* Interrupt Status Register */
  249 
  250 /*
  251  * CP15 C13 registers
  252  */
  253 #define CP15_FCSEIDR(rr)        p15, 0, rr, c13, c0, 0 /* FCSE Process ID Register */
  254 #define CP15_CONTEXTIDR(rr)     p15, 0, rr, c13, c0, 1 /* Context ID Register */
  255 #define CP15_TPIDRURW(rr)       p15, 0, rr, c13, c0, 2 /* User Read/Write Thread ID Register */
  256 #define CP15_TPIDRURO(rr)       p15, 0, rr, c13, c0, 3 /* User Read-Only Thread ID Register */
  257 #define CP15_TPIDRPRW(rr)       p15, 0, rr, c13, c0, 4 /* PL1 only Thread ID Register */
  258 
  259 /*
  260  * CP15 C15 registers
  261  */
  262 #define CP15_CBAR(rr)           p15, 4, rr, c15, c0, 0 /* Configuration Base Address Register */
  263 
  264 #endif /* !MACHINE_SYSREG_H */

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