The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/include/sysreg.h

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    1 /*-
    2  * Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
    3  * Copyright 2014 Michal Meloun <meloun@miracle.cz>
    4  * All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  *
   15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   18  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   25  * SUCH DAMAGE.
   26  *
   27  * $FreeBSD: releng/11.2/sys/arm/include/sysreg.h 300694 2016-05-25 19:44:26Z ian $
   28  */
   29 
   30 /*
   31  * Macros to make working with the System Control Registers simpler.
   32  *
   33  * Note that when register r0 is hard-coded in these definitions it means the
   34  * cp15 operation neither reads nor writes the register, and r0 is used only
   35  * because some syntatically-valid register name has to appear at that point to
   36  * keep the asm parser happy.
   37  */
   38 
   39 #ifndef MACHINE_SYSREG_H
   40 #define MACHINE_SYSREG_H
   41 
   42 /*
   43  * CP14 registers
   44  */
   45 #if __ARM_ARCH >= 6
   46 
   47 #define CP14_DBGDIDR(rr)        p14, 0, rr, c0, c0, 0 /* Debug ID Register */
   48 #define CP14_DBGDSCRext_V6(rr)  p14, 0, rr, c0, c1, 0 /* Debug Status and Ctrl Register v6 */
   49 #define CP14_DBGDSCRext_V7(rr)  p14, 0, rr, c0, c2, 2 /* Debug Status and Ctrl Register v7 */
   50 #define CP14_DBGVCR(rr)         p14, 0, rr, c0, c7, 0 /* Vector Catch Register */
   51 #define CP14_DBGOSLAR(rr)       p14, 0, rr, c1, c0, 4 /* OS Lock Access Register */
   52 #define CP14_DBGOSLSR(rr)       p14, 0, rr, c1, c1, 4 /* OS Lock Status Register */
   53 #define CP14_DBGOSDLR(rr)       p14, 0, rr, c1, c3, 4 /* OS Double Lock Register */
   54 #define CP14_DBGPRSR(rr)        p14, 0, rr, c1, c5, 4 /* Device Powerdown and Reset Status */
   55 
   56 #define CP14_DBGDSCRint(rr)     CP14_DBGDSCRext_V6(rr) /* Debug Status and Ctrl internal view */
   57 
   58 #endif
   59 
   60 /*
   61  * CP15 C0 registers
   62  */
   63 #define CP15_MIDR(rr)           p15, 0, rr, c0, c0,  0 /* Main ID Register */
   64 #define CP15_CTR(rr)            p15, 0, rr, c0, c0,  1 /* Cache Type Register */
   65 #define CP15_TCMTR(rr)          p15, 0, rr, c0, c0,  2 /* TCM Type Register */
   66 #define CP15_TLBTR(rr)          p15, 0, rr, c0, c0,  3 /* TLB Type Register */
   67 #define CP15_MPIDR(rr)          p15, 0, rr, c0, c0,  5 /* Multiprocessor Affinity Register */
   68 #define CP15_REVIDR(rr)         p15, 0, rr, c0, c0,  6 /* Revision ID Register */
   69 
   70 #define CP15_ID_PFR0(rr)        p15, 0, rr, c0, c1,  0 /* Processor Feature Register 0 */
   71 #define CP15_ID_PFR1(rr)        p15, 0, rr, c0, c1,  1 /* Processor Feature Register 1 */
   72 #define CP15_ID_DFR0(rr)        p15, 0, rr, c0, c1,  2 /* Debug Feature Register 0 */
   73 #define CP15_ID_AFR0(rr)        p15, 0, rr, c0, c1,  3 /* Auxiliary Feature Register  0 */
   74 #define CP15_ID_MMFR0(rr)       p15, 0, rr, c0, c1,  4 /* Memory Model Feature Register 0 */
   75 #define CP15_ID_MMFR1(rr)       p15, 0, rr, c0, c1,  5 /* Memory Model Feature Register 1 */
   76 #define CP15_ID_MMFR2(rr)       p15, 0, rr, c0, c1,  6 /* Memory Model Feature Register 2 */
   77 #define CP15_ID_MMFR3(rr)       p15, 0, rr, c0, c1,  7 /* Memory Model Feature Register 3 */
   78 
   79 #define CP15_ID_ISAR0(rr)       p15, 0, rr, c0, c2,  0 /* Instruction Set Attribute Register 0 */
   80 #define CP15_ID_ISAR1(rr)       p15, 0, rr, c0, c2,  1 /* Instruction Set Attribute Register 1 */
   81 #define CP15_ID_ISAR2(rr)       p15, 0, rr, c0, c2,  2 /* Instruction Set Attribute Register 2 */
   82 #define CP15_ID_ISAR3(rr)       p15, 0, rr, c0, c2,  3 /* Instruction Set Attribute Register 3 */
   83 #define CP15_ID_ISAR4(rr)       p15, 0, rr, c0, c2,  4 /* Instruction Set Attribute Register 4 */
   84 #define CP15_ID_ISAR5(rr)       p15, 0, rr, c0, c2,  5 /* Instruction Set Attribute Register 5 */
   85 
   86 #define CP15_CCSIDR(rr)         p15, 1, rr, c0, c0,  0 /* Cache Size ID Registers */
   87 #define CP15_CLIDR(rr)          p15, 1, rr, c0, c0,  1 /* Cache Level ID Register */
   88 #define CP15_AIDR(rr)           p15, 1, rr, c0, c0,  7 /* Auxiliary ID Register */
   89 
   90 #define CP15_CSSELR(rr)         p15, 2, rr, c0, c0,  0 /* Cache Size Selection Register */
   91 
   92 /*
   93  * CP15 C1 registers
   94  */
   95 #define CP15_SCTLR(rr)          p15, 0, rr, c1, c0,  0 /* System Control Register */
   96 #define CP15_ACTLR(rr)          p15, 0, rr, c1, c0,  1 /* IMPLEMENTATION DEFINED Auxiliary Control Register */
   97 #define CP15_CPACR(rr)          p15, 0, rr, c1, c0,  2 /* Coprocessor Access Control Register */
   98 
   99 #define CP15_SCR(rr)            p15, 0, rr, c1, c1,  0 /* Secure Configuration Register */
  100 #define CP15_SDER(rr)           p15, 0, rr, c1, c1,  1 /* Secure Debug Enable Register */
  101 #define CP15_NSACR(rr)          p15, 0, rr, c1, c1,  2 /* Non-Secure Access Control Register */
  102 
  103 /*
  104  * CP15 C2 registers
  105  */
  106 #define CP15_TTBR0(rr)          p15, 0, rr, c2, c0,  0 /* Translation Table Base Register 0 */
  107 #define CP15_TTBR1(rr)          p15, 0, rr, c2, c0,  1 /* Translation Table Base Register 1 */
  108 #define CP15_TTBCR(rr)          p15, 0, rr, c2, c0,  2 /* Translation Table Base Control Register */
  109 
  110 /*
  111  * CP15 C3 registers
  112  */
  113 #define CP15_DACR(rr)           p15, 0, rr, c3, c0,  0 /* Domain Access Control Register */
  114 
  115 /*
  116  * CP15 C5 registers
  117  */
  118 #define CP15_DFSR(rr)           p15, 0, rr, c5, c0,  0 /* Data Fault Status Register */
  119 
  120 #if __ARM_ARCH >= 6
  121 /* From ARMv6: */
  122 #define CP15_IFSR(rr)           p15, 0, rr, c5, c0,  1 /* Instruction Fault Status Register */
  123 #endif
  124 #if __ARM_ARCH >= 7
  125 /* From ARMv7: */
  126 #define CP15_ADFSR(rr)          p15, 0, rr, c5, c1,  0 /* Auxiliary Data Fault Status Register */
  127 #define CP15_AIFSR(rr)          p15, 0, rr, c5, c1,  1 /* Auxiliary Instruction Fault Status Register */
  128 #endif
  129 
  130 /*
  131  * CP15 C6 registers
  132  */
  133 #define CP15_DFAR(rr)           p15, 0, rr, c6, c0,  0 /* Data Fault Address Register */
  134 
  135 #if __ARM_ARCH >= 6
  136 /* From ARMv6k: */
  137 #define CP15_IFAR(rr)           p15, 0, rr, c6, c0,  2 /* Instruction Fault Address Register */
  138 #endif
  139 
  140 /*
  141  * CP15 C7 registers
  142  */
  143 #if __ARM_ARCH >= 7 && defined(SMP)
  144 /* From ARMv7: */
  145 #define CP15_ICIALLUIS          p15, 0, r0, c7, c1,  0 /* Instruction cache invalidate all PoU, IS */
  146 #define CP15_BPIALLIS           p15, 0, r0, c7, c1,  6 /* Branch predictor invalidate all IS */
  147 #endif
  148 
  149 #define CP15_PAR(rr)            p15, 0, rr, c7, c4,  0 /* Physical Address Register */
  150 
  151 #define CP15_ICIALLU            p15, 0, r0, c7, c5,  0 /* Instruction cache invalidate all PoU */
  152 #define CP15_ICIMVAU(rr)        p15, 0, rr, c7, c5,  1 /* Instruction cache invalidate */
  153 #if __ARM_ARCH == 6
  154 /* Deprecated in ARMv7 */
  155 #define CP15_CP15ISB            p15, 0, r0, c7, c5,  4 /* ISB */
  156 #endif
  157 #define CP15_BPIALL             p15, 0, r0, c7, c5,  6 /* Branch predictor invalidate all */
  158 #define CP15_BPIMVA             p15, 0, rr, c7, c5,  7 /* Branch predictor invalidate by MVA */
  159 
  160 #if __ARM_ARCH == 6
  161 /* Only ARMv6: */
  162 #define CP15_DCIALL             p15, 0, r0, c7, c6,  0 /* Data cache invalidate all */
  163 #endif
  164 #define CP15_DCIMVAC(rr)        p15, 0, rr, c7, c6,  1 /* Data cache invalidate by MVA PoC */
  165 #define CP15_DCISW(rr)          p15, 0, rr, c7, c6,  2 /* Data cache invalidate by set/way */
  166 
  167 #define CP15_ATS1CPR(rr)        p15, 0, rr, c7, c8,  0 /* Stage 1 Current state PL1 read */
  168 #define CP15_ATS1CPW(rr)        p15, 0, rr, c7, c8,  1 /* Stage 1 Current state PL1 write */
  169 #define CP15_ATS1CUR(rr)        p15, 0, rr, c7, c8,  2 /* Stage 1 Current state unprivileged read */
  170 #define CP15_ATS1CUW(rr)        p15, 0, rr, c7, c8,  3 /* Stage 1 Current state unprivileged write */
  171 
  172 #if __ARM_ARCH >= 7
  173 /* From ARMv7: */
  174 #define CP15_ATS12NSOPR(rr)     p15, 0, rr, c7, c8,  4 /* Stages 1 and 2 Non-secure only PL1 read */
  175 #define CP15_ATS12NSOPW(rr)     p15, 0, rr, c7, c8,  5 /* Stages 1 and 2 Non-secure only PL1 write */
  176 #define CP15_ATS12NSOUR(rr)     p15, 0, rr, c7, c8,  6 /* Stages 1 and 2 Non-secure only unprivileged read */
  177 #define CP15_ATS12NSOUW(rr)     p15, 0, rr, c7, c8,  7 /* Stages 1 and 2 Non-secure only unprivileged write */
  178 #endif
  179 
  180 #if __ARM_ARCH == 6
  181 /* Only ARMv6: */
  182 #define CP15_DCCALL             p15, 0, r0, c7, c10, 0 /* Data cache clean all */
  183 #endif
  184 #define CP15_DCCMVAC(rr)        p15, 0, rr, c7, c10, 1 /* Data cache clean by MVA PoC */
  185 #define CP15_DCCSW(rr)          p15, 0, rr, c7, c10, 2 /* Data cache clean by set/way */
  186 #if __ARM_ARCH == 6
  187 /* Only ARMv6: */
  188 #define CP15_CP15DSB            p15, 0, r0, c7, c10, 4 /* DSB */
  189 #define CP15_CP15DMB            p15, 0, r0, c7, c10, 5 /* DMB */
  190 #define CP15_CP15WFI            p15, 0, r0, c7, c0,  4 /* WFI */
  191 #endif
  192 
  193 #if __ARM_ARCH >= 7
  194 /* From ARMv7: */
  195 #define CP15_DCCMVAU(rr)        p15, 0, rr, c7, c11, 1 /* Data cache clean by MVA PoU */
  196 #endif
  197 
  198 #if __ARM_ARCH == 6
  199 /* Only ARMv6: */
  200 #define CP15_DCCIALL            p15, 0, r0, c7, c14, 0 /* Data cache clean and invalidate all */
  201 #endif
  202 #define CP15_DCCIMVAC(rr)       p15, 0, rr, c7, c14, 1 /* Data cache clean and invalidate by MVA PoC */
  203 #define CP15_DCCISW(rr)         p15, 0, rr, c7, c14, 2 /* Data cache clean and invalidate by set/way */
  204 
  205 /*
  206  * CP15 C8 registers
  207  */
  208 #if __ARM_ARCH >= 7 && defined(SMP)
  209 /* From ARMv7: */
  210 #define CP15_TLBIALLIS          p15, 0, r0, c8, c3, 0 /* Invalidate entire unified TLB IS */
  211 #define CP15_TLBIMVAIS(rr)      p15, 0, rr, c8, c3, 1 /* Invalidate unified TLB by MVA IS */
  212 #define CP15_TLBIASIDIS(rr)     p15, 0, rr, c8, c3, 2 /* Invalidate unified TLB by ASID IS */
  213 #define CP15_TLBIMVAAIS(rr)     p15, 0, rr, c8, c3, 3 /* Invalidate unified TLB by MVA, all ASID IS */
  214 #endif
  215 
  216 #define CP15_TLBIALL            p15, 0, r0, c8, c7, 0 /* Invalidate entire unified TLB */
  217 #define CP15_TLBIMVA(rr)        p15, 0, rr, c8, c7, 1 /* Invalidate unified TLB by MVA */
  218 #define CP15_TLBIASID(rr)       p15, 0, rr, c8, c7, 2 /* Invalidate unified TLB by ASID */
  219 
  220 #if __ARM_ARCH >= 6
  221 /* From ARMv6: */
  222 #define CP15_TLBIMVAA(rr)       p15, 0, rr, c8, c7, 3 /* Invalidate unified TLB by MVA, all ASID */
  223 #endif
  224 
  225 /*
  226  * CP15 C9 registers
  227  */
  228 #if __ARM_ARCH == 6 && defined(CPU_ARM1176)
  229 #define CP15_PMUSERENR(rr)      p15, 0, rr, c15,  c9, 0 /* Access Validation Control Register */
  230 #define CP15_PMCR(rr)           p15, 0, rr, c15, c12, 0 /* Performance Monitor Control Register */
  231 #define CP15_PMCCNTR(rr)        p15, 0, rr, c15, c12, 1 /* PM Cycle Count Register */
  232 #elif __ARM_ARCH > 6
  233 #define CP15_L2CTLR(rr)         p15, 1, rr,  c9, c0,  2 /* L2 Control Register */
  234 #define CP15_PMCR(rr)           p15, 0, rr,  c9, c12, 0 /* Performance Monitor Control Register */
  235 #define CP15_PMCNTENSET(rr)     p15, 0, rr,  c9, c12, 1 /* PM Count Enable Set Register */
  236 #define CP15_PMCNTENCLR(rr)     p15, 0, rr,  c9, c12, 2 /* PM Count Enable Clear Register */
  237 #define CP15_PMOVSR(rr)         p15, 0, rr,  c9, c12, 3 /* PM Overflow Flag Status Register */
  238 #define CP15_PMSWINC(rr)        p15, 0, rr,  c9, c12, 4 /* PM Software Increment Register */
  239 #define CP15_PMSELR(rr)         p15, 0, rr,  c9, c12, 5 /* PM Event Counter Selection Register */
  240 #define CP15_PMCCNTR(rr)        p15, 0, rr,  c9, c13, 0 /* PM Cycle Count Register */
  241 #define CP15_PMXEVTYPER(rr)     p15, 0, rr,  c9, c13, 1 /* PM Event Type Select Register */
  242 #define CP15_PMXEVCNTRR(rr)     p15, 0, rr,  c9, c13, 2 /* PM Event Count Register */
  243 #define CP15_PMUSERENR(rr)      p15, 0, rr,  c9, c14, 0 /* PM User Enable Register */
  244 #define CP15_PMINTENSET(rr)     p15, 0, rr,  c9, c14, 1 /* PM Interrupt Enable Set Register */
  245 #define CP15_PMINTENCLR(rr)     p15, 0, rr,  c9, c14, 2 /* PM Interrupt Enable Clear Register */
  246 #endif
  247 
  248 /*
  249  * CP15 C10 registers
  250  */
  251 /* Without LPAE this is PRRR, with LPAE it's MAIR0 */
  252 #define CP15_PRRR(rr)           p15, 0, rr, c10, c2, 0 /* Primary Region Remap Register */
  253 #define CP15_MAIR0(rr)          p15, 0, rr, c10, c2, 0 /* Memory Attribute Indirection Register 0 */
  254 /* Without LPAE this is NMRR, with LPAE it's MAIR1 */
  255 #define CP15_NMRR(rr)           p15, 0, rr, c10, c2, 1 /* Normal Memory Remap Register */
  256 #define CP15_MAIR1(rr)          p15, 0, rr, c10, c2, 1 /* Memory Attribute Indirection Register 1 */
  257 
  258 #define CP15_AMAIR0(rr)         p15, 0, rr, c10, c3, 0 /* Auxiliary Memory Attribute Indirection Register 0 */
  259 #define CP15_AMAIR1(rr)         p15, 0, rr, c10, c3, 1 /* Auxiliary Memory Attribute Indirection Register 1 */
  260 
  261 /*
  262  * CP15 C12 registers
  263  */
  264 #define CP15_VBAR(rr)           p15, 0, rr, c12, c0, 0 /* Vector Base Address Register */
  265 #define CP15_MVBAR(rr)          p15, 0, rr, c12, c0, 1 /* Monitor Vector Base Address Register */
  266 
  267 #define CP15_ISR(rr)            p15, 0, rr, c12, c1, 0 /* Interrupt Status Register */
  268 
  269 /*
  270  * CP15 C13 registers
  271  */
  272 #define CP15_FCSEIDR(rr)        p15, 0, rr, c13, c0, 0 /* FCSE Process ID Register */
  273 #define CP15_CONTEXTIDR(rr)     p15, 0, rr, c13, c0, 1 /* Context ID Register */
  274 #define CP15_TPIDRURW(rr)       p15, 0, rr, c13, c0, 2 /* User Read/Write Thread ID Register */
  275 #define CP15_TPIDRURO(rr)       p15, 0, rr, c13, c0, 3 /* User Read-Only Thread ID Register */
  276 #define CP15_TPIDRPRW(rr)       p15, 0, rr, c13, c0, 4 /* PL1 only Thread ID Register */
  277 
  278 /*
  279  * CP15 C14 registers
  280  * These are the Generic Timer registers and may be unallocated on some SoCs.
  281  * Only use these when you know the Generic Timer is available.
  282  */
  283 #define CP15_CNTFRQ(rr)         p15, 0, rr, c14, c0, 0 /* Counter Frequency Register */
  284 #define CP15_CNTKCTL(rr)        p15, 0, rr, c14, c1, 0 /* Timer PL1 Control Register */
  285 #define CP15_CNTP_TVAL(rr)      p15, 0, rr, c14, c2, 0 /* PL1 Physical Timer Value Register */
  286 #define CP15_CNTP_CTL(rr)       p15, 0, rr, c14, c2, 1 /* PL1 Physical Timer Control Register */
  287 #define CP15_CNTV_TVAL(rr)      p15, 0, rr, c14, c3, 0 /* Virtual Timer Value Register */
  288 #define CP15_CNTV_CTL(rr)       p15, 0, rr, c14, c3, 1 /* Virtual Timer Control Register */
  289 #define CP15_CNTHCTL(rr)        p15, 4, rr, c14, c1, 0 /* Timer PL2 Control Register */
  290 #define CP15_CNTHP_TVAL(rr)     p15, 4, rr, c14, c2, 0 /* PL2 Physical Timer Value Register */
  291 #define CP15_CNTHP_CTL(rr)      p15, 4, rr, c14, c2, 1 /* PL2 Physical Timer Control Register */
  292 /* 64-bit registers for use with mcrr/mrrc */
  293 #define CP15_CNTPCT(rq, rr)     p15, 0, rq, rr, c14     /* Physical Count Register */
  294 #define CP15_CNTVCT(rq, rr)     p15, 1, rq, rr, c14     /* Virtual Count Register */
  295 #define CP15_CNTP_CVAL(rq, rr)  p15, 2, rq, rr, c14     /* PL1 Physical Timer Compare Value Register */
  296 #define CP15_CNTV_CVAL(rq, rr)  p15, 3, rq, rr, c14     /* Virtual Timer Compare Value Register */
  297 #define CP15_CNTVOFF(rq, rr)    p15, 4, rq, rr, c14     /* Virtual Offset Register */
  298 #define CP15_CNTHP_CVAL(rq, rr) p15, 6, rq, rr, c14     /* PL2 Physical Timer Compare Value Register */
  299 
  300 /*
  301  * CP15 C15 registers
  302  */
  303 #define CP15_CBAR(rr)           p15, 4, rr, c15, c0, 0 /* Configuration Base Address Register */
  304 
  305 #endif /* !MACHINE_SYSREG_H */

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