FreeBSD/Linux Kernel Cross Reference
sys/arm/include/vfp.h
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2012 Mark Tinguely
5 *
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 * $FreeBSD$
29 */
30
31 #ifndef _MACHINE__VFP_H_
32 #define _MACHINE__VFP_H_
33
34 /* fpsid, fpscr, fpexc are defined in the newer gas */
35 #define VFPSID cr0
36 #define VFPSCR cr1
37 #define VMVFR1 cr6
38 #define VMVFR0 cr7
39 #define VFPEXC cr8
40 #define VFPINST cr9 /* vfp 1 and 2 except instruction */
41 #define VFPINST2 cr10 /* vfp 2? */
42
43 /* VFPSID */
44 #define VFPSID_IMPLEMENTOR_OFF 24
45 #define VFPSID_IMPLEMENTOR_MASK (0xff000000)
46 #define VFPSID_HARDSOFT_IMP (0x00800000)
47 #define VFPSID_SINGLE_PREC 20 /* version 1 and 2 */
48 #define VFPSID_SUBVERSION_OFF 16
49 #define VFPSID_SUBVERSION2_MASK (0x000f0000) /* version 1 and 2 */
50 #define VFPSID_SUBVERSION3_MASK (0x007f0000) /* version 3 */
51 #define VFP_ARCH1 0x0
52 #define VFP_ARCH2 0x1
53 #define VFP_ARCH3 0x2
54 #define VFPSID_PARTNUMBER_OFF 8
55 #define VFPSID_PARTNUMBER_MASK (0x0000ff00)
56 #define VFPSID_VARIANT_OFF 4
57 #define VFPSID_VARIANT_MASK (0x000000f0)
58 #define VFPSID_REVISION_MASK 0x0f
59
60 /* VFPSCR */
61 #define VFPSCR_CC_N (0x80000000) /* comparison less than */
62 #define VFPSCR_CC_Z (0x40000000) /* comparison equal */
63 #define VFPSCR_CC_C (0x20000000) /* comparison = > unordered */
64 #define VFPSCR_CC_V (0x10000000) /* comparison unordered */
65 #define VFPSCR_QC (0x08000000) /* saturation cululative */
66 #define VFPSCR_DN (0x02000000) /* default NaN enable */
67 #define VFPSCR_FZ (0x01000000) /* flush to zero enabled */
68
69 #define VFPSCR_RMODE_OFF 22 /* rounding mode offset */
70 #define VFPSCR_RMODE_MASK (0x00c00000) /* rounding mode mask */
71 #define VFPSCR_RMODE_RN (0x00000000) /* round nearest */
72 #define VFPSCR_RMODE_RPI (0x00400000) /* round to plus infinity */
73 #define VFPSCR_RMODE_RNI (0x00800000) /* round to neg infinity */
74 #define VFPSCR_RMODE_RM (0x00c00000) /* round to zero */
75
76 #define VFPSCR_STRIDE_OFF 20 /* vector stride -1 */
77 #define VFPSCR_STRIDE_MASK (0x00300000)
78 #define VFPSCR_LEN_OFF 16 /* vector length -1 */
79 #define VFPSCR_LEN_MASK (0x00070000)
80 #define VFPSCR_IDE (0x00008000) /* input subnormal exc enable */
81 #define VFPSCR_IXE (0x00001000) /* inexact exception enable */
82 #define VFPSCR_UFE (0x00000800) /* underflow exception enable */
83 #define VFPSCR_OFE (0x00000400) /* overflow exception enable */
84 #define VFPSCR_DNZ (0x00000200) /* div by zero exception en */
85 #define VFPSCR_IOE (0x00000100) /* invalid op exec enable */
86 #define VFPSCR_IDC (0x00000080) /* input subnormal cumul */
87 #define VFPSCR_IXC (0x00000010) /* Inexact cumulative flag */
88 #define VFPSCR_UFC (0x00000008) /* underflow cumulative flag */
89 #define VFPSCR_OFC (0x00000004) /* overflow cumulative flag */
90 #define VFPSCR_DZC (0x00000002) /* division by zero flag */
91 #define VFPSCR_IOC (0x00000001) /* invalid operation cumul */
92
93 /* VFPEXC */
94 #define VFPEXC_EX (0x80000000) /* exception v1 v2 */
95 #define VFPEXC_EN (0x40000000) /* vfp enable */
96 #define VFPEXC_DEX (0x20000000) /* Synchronous exception */
97 #define VFPEXC_FP2V (0x10000000) /* FPINST2 valid */
98 #define VFPEXC_INV (0x00000080) /* Input exception */
99 #define VFPEXC_UFC (0x00000008) /* Underflow exception */
100 #define VFPEXC_OFC (0x00000004) /* Overflow exception */
101 #define VFPEXC_IOC (0x00000001) /* Invlaid operation */
102
103 /* version 3 registers */
104 /* VMVFR0 */
105 #define VMVFR0_RM_OFF 28
106 #define VMVFR0_RM_MASK (0xf0000000) /* VFP rounding modes */
107
108 #define VMVFR0_SV_OFF 24
109 #define VMVFR0_SV_MASK (0x0f000000) /* VFP short vector supp */
110 #define VMVFR0_SR_OFF 20
111 #define VMVFR0_SR (0x00f00000) /* VFP hw sqrt supp */
112 #define VMVFR0_D_OFF 16
113 #define VMVFR0_D_MASK (0x000f0000) /* VFP divide supp */
114 #define VMVFR0_TE_OFF 12
115 #define VMVFR0_TE_MASK (0x0000f000) /* VFP trap exception supp */
116 #define VMVFR0_DP_OFF 8
117 #define VMVFR0_DP_MASK (0x00000f00) /* VFP double prec support */
118 #define VMVFR0_SP_OFF 4
119 #define VMVFR0_SP_MASK (0x000000f0) /* VFP single prec support */
120 #define VMVFR0_RB_MASK (0x0000000f) /* VFP 64 bit media support */
121
122 /* VMVFR1 */
123 #define VMVFR1_FMAC_OFF 28
124 #define VMVFR1_FMAC_MASK (0xf0000000) /* Neon FMAC support */
125 #define VMVFR1_VFP_HP_OFF 24
126 #define VMVFR1_VFP_HP_MASK (0x0f000000) /* VFP half prec support */
127 #define VMVFR1_HP_OFF 20
128 #define VMVFR1_HP_MASK (0x00f00000) /* Neon half prec support */
129 #define VMVFR1_SP_OFF 16
130 #define VMVFR1_SP_MASK (0x000f0000) /* Neon single prec support */
131 #define VMVFR1_I_OFF 12
132 #define VMVFR1_I_MASK (0x0000f000) /* Neon integer support */
133 #define VMVFR1_LS_OFF 8
134 #define VMVFR1_LS_MASK (0x00000f00) /* Neon ld/st instr support */
135 #define VMVFR1_DN_OFF 4
136 #define VMVFR1_DN_MASK (0x000000f0) /* Neon prop NaN support */
137 #define VMVFR1_FZ_MASK (0x0000000f) /* Neon denormal arith supp */
138
139 #define COPROC10 (0x3 << 20)
140 #define COPROC11 (0x3 << 22)
141
142 #ifndef LOCORE
143 struct vfp_state {
144 uint64_t reg[32];
145 uint32_t fpscr;
146 uint32_t fpexec;
147 uint32_t fpinst;
148 uint32_t fpinst2;
149 };
150
151 #ifdef _KERNEL
152 void get_vfpcontext(struct thread *, mcontext_vfp_t *);
153 void set_vfpcontext(struct thread *, mcontext_vfp_t *);
154 void vfp_init(void);
155 void vfp_store(struct vfp_state *, boolean_t);
156 void vfp_discard(struct thread *);
157 #endif /* _KERNEL */
158 #endif /* LOCORE */
159
160 #endif
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