The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/mv/a37x0_gpio.c

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (c) 2018-2019, Rubicon Communications, LLC (Netgate)
    5  * All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  *
   16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   21  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   22  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   23  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   25  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   26  *
   27  */
   28 
   29 #include <sys/cdefs.h>
   30 __FBSDID("$FreeBSD$");
   31 
   32 #include <sys/param.h>
   33 #include <sys/systm.h>
   34 #include <sys/bus.h>
   35 
   36 #include <sys/gpio.h>
   37 #include <sys/kernel.h>
   38 #include <sys/module.h>
   39 #include <sys/rman.h>
   40 
   41 #include <machine/bus.h>
   42 #include <machine/resource.h>
   43 
   44 #include <dev/gpio/gpiobusvar.h>
   45 #include <dev/ofw/ofw_bus.h>
   46 #include <dev/ofw/ofw_bus_subr.h>
   47 
   48 #include "gpio_if.h"
   49 #include "syscon_if.h"
   50 
   51 struct a37x0_gpio_softc {
   52         device_t                sc_busdev;
   53         int                     sc_type;
   54         uint32_t                sc_max_pins;
   55         uint32_t                sc_npins;
   56         struct syscon           *syscon;
   57 };
   58 
   59 /* Memory regions. */
   60 #define A37X0_GPIO                      0
   61 #define A37X0_INTR                      1
   62 
   63 /* North Bridge / South Bridge. */
   64 #define A37X0_NB_GPIO                   1
   65 #define A37X0_SB_GPIO                   2
   66 
   67 #define A37X0_GPIO_WRITE(_sc, _off, _val)               \
   68     SYSCON_WRITE_4((_sc)->syscon, (_off), (_val))
   69 #define A37X0_GPIO_READ(_sc, _off)                      \
   70     SYSCON_READ_4((_sc)->syscon, (_off))
   71 
   72 #define A37X0_GPIO_BIT(_p)              (1U << ((_p) % 32))
   73 #define A37X0_GPIO_OUT_EN(_p)           (0x0 + ((_p) / 32) * 4)
   74 #define A37X0_GPIO_LATCH(_p)            (0x8 + ((_p) / 32) * 4)
   75 #define A37X0_GPIO_INPUT(_p)            (0x10 + ((_p) / 32) * 4)
   76 #define A37X0_GPIO_OUTPUT(_p)           (0x18 + ((_p) / 32) * 4)
   77 #define A37X0_GPIO_SEL                  0x30
   78 
   79 
   80 static struct ofw_compat_data compat_data[] = {
   81         { "marvell,armada3710-nb-pinctrl",      A37X0_NB_GPIO },
   82         { "marvell,armada3710-sb-pinctrl",      A37X0_SB_GPIO },
   83         { NULL, 0 }
   84 };
   85 
   86 static phandle_t
   87 a37x0_gpio_get_node(device_t bus, device_t dev)
   88 {
   89 
   90         return (ofw_bus_get_node(bus));
   91 }
   92 
   93 static device_t
   94 a37x0_gpio_get_bus(device_t dev)
   95 {
   96         struct a37x0_gpio_softc *sc;
   97 
   98         sc = device_get_softc(dev);
   99 
  100         return (sc->sc_busdev);
  101 }
  102 
  103 static int
  104 a37x0_gpio_pin_max(device_t dev, int *maxpin)
  105 {
  106         struct a37x0_gpio_softc *sc;
  107 
  108         sc = device_get_softc(dev);
  109         *maxpin = sc->sc_npins - 1;
  110 
  111         return (0);
  112 }
  113 
  114 static int
  115 a37x0_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
  116 {
  117         struct a37x0_gpio_softc *sc;
  118 
  119         sc = device_get_softc(dev);
  120         if (pin >= sc->sc_npins)
  121                 return (EINVAL);
  122         snprintf(name, GPIOMAXNAME, "pin %d", pin);
  123 
  124         return (0);
  125 }
  126 
  127 static int
  128 a37x0_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
  129 {
  130         struct a37x0_gpio_softc *sc;
  131 
  132         sc = device_get_softc(dev);
  133         if (pin >= sc->sc_npins)
  134                 return (EINVAL);
  135         *caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT;
  136 
  137         return (0);
  138 }
  139 
  140 static int
  141 a37x0_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
  142 {
  143         struct a37x0_gpio_softc *sc;
  144         uint32_t reg;
  145 
  146         sc = device_get_softc(dev);
  147         if (pin >= sc->sc_npins)
  148                 return (EINVAL);
  149         reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUT_EN(pin));
  150         if ((reg & A37X0_GPIO_BIT(pin)) != 0)
  151                 *flags = GPIO_PIN_OUTPUT;
  152         else
  153                 *flags = GPIO_PIN_INPUT;
  154 
  155         return (0);
  156 }
  157 
  158 static int
  159 a37x0_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
  160 {
  161         struct a37x0_gpio_softc *sc;
  162         uint32_t reg;
  163 
  164         sc = device_get_softc(dev);
  165         if (pin >= sc->sc_npins)
  166                 return (EINVAL);
  167 
  168         reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUT_EN(pin));
  169         if (flags & GPIO_PIN_OUTPUT)
  170                 reg |= A37X0_GPIO_BIT(pin);
  171         else
  172                 reg &= ~A37X0_GPIO_BIT(pin);
  173         A37X0_GPIO_WRITE(sc, A37X0_GPIO_OUT_EN(pin), reg);
  174 
  175         return (0);
  176 }
  177 
  178 static int
  179 a37x0_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
  180 {
  181         struct a37x0_gpio_softc *sc;
  182         uint32_t reg;
  183 
  184         sc = device_get_softc(dev);
  185         if (pin >= sc->sc_npins)
  186                 return (EINVAL);
  187 
  188         reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUT_EN(pin));
  189         if ((reg & A37X0_GPIO_BIT(pin)) != 0)
  190                 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUTPUT(pin));
  191         else
  192                 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_INPUT(pin));
  193         *val = ((reg & A37X0_GPIO_BIT(pin)) != 0) ? 1 : 0;
  194 
  195         return (0);
  196 }
  197 
  198 static int
  199 a37x0_gpio_pin_set(device_t dev, uint32_t pin, unsigned int val)
  200 {
  201         struct a37x0_gpio_softc *sc;
  202         uint32_t reg;
  203 
  204         sc = device_get_softc(dev);
  205         if (pin >= sc->sc_npins)
  206                 return (EINVAL);
  207 
  208         reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUTPUT(pin));
  209         if (val != 0)
  210                 reg |= A37X0_GPIO_BIT(pin);
  211         else
  212                 reg &= ~A37X0_GPIO_BIT(pin);
  213         A37X0_GPIO_WRITE(sc, A37X0_GPIO_OUTPUT(pin), reg);
  214 
  215         return (0);
  216 }
  217 
  218 static int
  219 a37x0_gpio_pin_toggle(device_t dev, uint32_t pin)
  220 {
  221         struct a37x0_gpio_softc *sc;
  222         uint32_t reg;
  223 
  224         sc = device_get_softc(dev);
  225         if (pin >= sc->sc_npins)
  226                 return (EINVAL);
  227 
  228         reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUT_EN(pin));
  229         if ((reg & A37X0_GPIO_BIT(pin)) == 0)
  230                 return (EINVAL);
  231         reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUTPUT(pin));
  232         reg ^= A37X0_GPIO_BIT(pin);
  233         A37X0_GPIO_WRITE(sc, A37X0_GPIO_OUTPUT(pin), reg);
  234 
  235         return (0);
  236 }
  237 
  238 static int
  239 a37x0_gpio_probe(device_t dev)
  240 {
  241         const char *desc;
  242         struct a37x0_gpio_softc *sc;
  243 
  244         if (!OF_hasprop(ofw_bus_get_node(dev), "gpio-controller"))
  245                 return (ENXIO);
  246 
  247         sc = device_get_softc(dev);
  248         sc->sc_type = ofw_bus_search_compatible(
  249             device_get_parent(dev), compat_data)->ocd_data;
  250         switch (sc->sc_type) {
  251         case A37X0_NB_GPIO:
  252                 sc->sc_max_pins = 36;
  253                 desc = "Armada 37x0 North Bridge GPIO Controller";
  254                 break;
  255         case A37X0_SB_GPIO:
  256                 sc->sc_max_pins = 30;
  257                 desc = "Armada 37x0 South Bridge GPIO Controller";
  258                 break;
  259         default:
  260                 return (ENXIO);
  261         }
  262         device_set_desc(dev, desc);
  263 
  264         return (BUS_PROBE_DEFAULT);
  265 }
  266 
  267 static int
  268 a37x0_gpio_attach(device_t dev)
  269 {
  270         int err, ncells;
  271         pcell_t *ranges;
  272         struct a37x0_gpio_softc *sc;
  273 
  274         sc = device_get_softc(dev);
  275 
  276         err = syscon_get_handle_default(dev, &sc->syscon);
  277         if (err != 0) {
  278                 device_printf(dev, "Cannot get syscon handle from parent\n");
  279                 return (ENXIO);
  280         }
  281 
  282         /* Read and verify the "gpio-ranges" property. */
  283         ncells = OF_getencprop_alloc(ofw_bus_get_node(dev), "gpio-ranges",
  284             (void **)&ranges);
  285         if (ncells == -1)
  286                 return (ENXIO);
  287         if (ncells != sizeof(*ranges) * 4 || ranges[1] != 0 || ranges[2] != 0) {
  288                 OF_prop_free(ranges);
  289                 return (ENXIO);
  290         }
  291         sc->sc_npins = ranges[3];
  292         OF_prop_free(ranges);
  293 
  294         /* Check the number of pins in the DTS vs HW capabilities. */
  295         if (sc->sc_npins > sc->sc_max_pins)
  296                 return (ENXIO);
  297 
  298         sc->sc_busdev = gpiobus_attach_bus(dev);
  299         if (sc->sc_busdev == NULL)
  300                 return (ENXIO);
  301 
  302         return (0);
  303 }
  304 
  305 static int
  306 a37x0_gpio_detach(device_t dev)
  307 {
  308 
  309         return (EBUSY);
  310 }
  311 
  312 static device_method_t a37x0_gpio_methods[] = {
  313         /* Device interface */
  314         DEVMETHOD(device_probe,         a37x0_gpio_probe),
  315         DEVMETHOD(device_attach,        a37x0_gpio_attach),
  316         DEVMETHOD(device_detach,        a37x0_gpio_detach),
  317 
  318         /* GPIO interface */
  319         DEVMETHOD(gpio_get_bus,         a37x0_gpio_get_bus),
  320         DEVMETHOD(gpio_pin_max,         a37x0_gpio_pin_max),
  321         DEVMETHOD(gpio_pin_getname,     a37x0_gpio_pin_getname),
  322         DEVMETHOD(gpio_pin_getcaps,     a37x0_gpio_pin_getcaps),
  323         DEVMETHOD(gpio_pin_getflags,    a37x0_gpio_pin_getflags),
  324         DEVMETHOD(gpio_pin_setflags,    a37x0_gpio_pin_setflags),
  325         DEVMETHOD(gpio_pin_get,         a37x0_gpio_pin_get),
  326         DEVMETHOD(gpio_pin_set,         a37x0_gpio_pin_set),
  327         DEVMETHOD(gpio_pin_toggle,      a37x0_gpio_pin_toggle),
  328 
  329         /* ofw_bus interface */
  330         DEVMETHOD(ofw_bus_get_node,     a37x0_gpio_get_node),
  331 
  332         DEVMETHOD_END
  333 };
  334 
  335 static devclass_t a37x0_gpio_devclass;
  336 static driver_t a37x0_gpio_driver = {
  337         "gpio",
  338         a37x0_gpio_methods,
  339         sizeof(struct a37x0_gpio_softc),
  340 };
  341 
  342 EARLY_DRIVER_MODULE(a37x0_gpio, simple_mfd, a37x0_gpio_driver,
  343     a37x0_gpio_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LAST);

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