Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/arm/mv/armada/wdt.c
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1 /*- 2 * Copyright (c) 2006 Benno Rice. 3 * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD. 4 * All rights reserved. 5 * 6 * Adapted to Marvell SoC by Semihalf. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_timer.c, rev 1 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/eventhandler.h> 38 #include <sys/kernel.h> 39 #include <sys/module.h> 40 #include <sys/malloc.h> 41 #include <sys/rman.h> 42 #include <sys/kdb.h> 43 #include <sys/timeet.h> 44 #include <sys/timetc.h> 45 #include <sys/watchdog.h> 46 #include <machine/bus.h> 47 #include <machine/cpu.h> 48 49 #include <arm/mv/mvreg.h> 50 #include <arm/mv/mvvar.h> 51 52 #include <dev/ofw/ofw_bus.h> 53 #include <dev/ofw/ofw_bus_subr.h> 54 55 #define INITIAL_TIMECOUNTER (0xffffffff) 56 #define MAX_WATCHDOG_TICKS (0xffffffff) 57 #define WD_RST_OUT_EN 0x00000002 58 59 #define MV_CLOCK_SRC_ARMV7 25000000 /* Timers' 25MHz mode */ 60 61 struct mv_wdt_config { 62 enum soc_family wdt_soc; 63 uint32_t wdt_timer; 64 void (*wdt_enable)(void); 65 void (*wdt_disable)(void); 66 unsigned int wdt_clock_src; 67 }; 68 69 static void mv_wdt_enable_armv5(void); 70 static void mv_wdt_enable_armada_38x(void); 71 static void mv_wdt_enable_armada_xp(void); 72 73 static void mv_wdt_disable_armv5(void); 74 static void mv_wdt_disable_armada_38x(void); 75 static void mv_wdt_disable_armada_xp(void); 76 77 static struct mv_wdt_config mv_wdt_armada_38x_config = { 78 .wdt_soc = MV_SOC_ARMADA_38X, 79 .wdt_timer = 4, 80 .wdt_enable = &mv_wdt_enable_armada_38x, 81 .wdt_disable = &mv_wdt_disable_armada_38x, 82 .wdt_clock_src = MV_CLOCK_SRC_ARMV7, 83 }; 84 85 static struct mv_wdt_config mv_wdt_armada_xp_config = { 86 .wdt_soc = MV_SOC_ARMADA_XP, 87 .wdt_timer = 2, 88 .wdt_enable = &mv_wdt_enable_armada_xp, 89 .wdt_disable = &mv_wdt_disable_armada_xp, 90 .wdt_clock_src = MV_CLOCK_SRC_ARMV7, 91 }; 92 93 static struct mv_wdt_config mv_wdt_armv5_config = { 94 .wdt_soc = MV_SOC_ARMV5, 95 .wdt_timer = 2, 96 .wdt_enable = &mv_wdt_enable_armv5, 97 .wdt_disable = &mv_wdt_disable_armv5, 98 .wdt_clock_src = 0, 99 }; 100 101 struct mv_wdt_softc { 102 struct resource * wdt_res; 103 struct mtx wdt_mtx; 104 struct mv_wdt_config * wdt_config; 105 }; 106 107 static struct resource_spec mv_wdt_spec[] = { 108 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 109 { -1, 0 } 110 }; 111 112 static struct ofw_compat_data mv_wdt_compat[] = { 113 {"marvell,armada-380-wdt", (uintptr_t)&mv_wdt_armada_38x_config}, 114 {"marvell,armada-xp-wdt", (uintptr_t)&mv_wdt_armada_xp_config}, 115 {"marvell,orion-wdt", (uintptr_t)&mv_wdt_armv5_config}, 116 {NULL, (uintptr_t)NULL} 117 }; 118 119 static struct mv_wdt_softc *wdt_softc = NULL; 120 int timers_initialized = 0; 121 122 static int mv_wdt_probe(device_t); 123 static int mv_wdt_attach(device_t); 124 125 static uint32_t mv_get_timer_control(void); 126 static void mv_set_timer_control(uint32_t); 127 static void mv_set_timer(uint32_t, uint32_t); 128 129 static void mv_watchdog_event(void *, unsigned int, int *); 130 131 static device_method_t mv_wdt_methods[] = { 132 DEVMETHOD(device_probe, mv_wdt_probe), 133 DEVMETHOD(device_attach, mv_wdt_attach), 134 { 0, 0 } 135 }; 136 137 static driver_t mv_wdt_driver = { 138 "wdt", 139 mv_wdt_methods, 140 sizeof(struct mv_wdt_softc), 141 }; 142 143 DRIVER_MODULE(wdt, simplebus, mv_wdt_driver, 0, 0); 144 145 static int 146 mv_wdt_probe(device_t dev) 147 { 148 149 if (!ofw_bus_status_okay(dev)) 150 return (ENXIO); 151 152 if (!ofw_bus_search_compatible(dev, mv_wdt_compat)->ocd_data) 153 return (ENXIO); 154 155 device_set_desc(dev, "Marvell Watchdog Timer"); 156 return (0); 157 } 158 159 static int 160 mv_wdt_attach(device_t dev) 161 { 162 struct mv_wdt_softc *sc; 163 int error; 164 165 if (wdt_softc != NULL) 166 return (ENXIO); 167 168 sc = device_get_softc(dev); 169 wdt_softc = sc; 170 171 error = bus_alloc_resources(dev, mv_wdt_spec, &sc->wdt_res); 172 if (error) { 173 device_printf(dev, "could not allocate resources\n"); 174 return (ENXIO); 175 } 176 177 mtx_init(&sc->wdt_mtx, "watchdog", NULL, MTX_DEF); 178 179 sc->wdt_config = (struct mv_wdt_config *) 180 ofw_bus_search_compatible(dev, mv_wdt_compat)->ocd_data; 181 182 if (sc->wdt_config->wdt_clock_src == 0) 183 sc->wdt_config->wdt_clock_src = get_tclk(); 184 185 if (wdt_softc->wdt_config->wdt_disable != NULL) 186 wdt_softc->wdt_config->wdt_disable(); 187 EVENTHANDLER_REGISTER(watchdog_list, mv_watchdog_event, sc, 0); 188 189 return (0); 190 } 191 192 static __inline uint32_t 193 mv_get_timer_control(void) 194 { 195 196 return (bus_read_4(wdt_softc->wdt_res, CPU_TIMER_CONTROL)); 197 } 198 199 static __inline void 200 mv_set_timer_control(uint32_t val) 201 { 202 203 bus_write_4(wdt_softc->wdt_res, CPU_TIMER_CONTROL, val); 204 } 205 206 static __inline void 207 mv_set_timer(uint32_t timer, uint32_t val) 208 { 209 210 bus_write_4(wdt_softc->wdt_res, CPU_TIMER0 + timer * 0x8, val); 211 } 212 static void 213 mv_wdt_enable_armv5(void) 214 { 215 uint32_t val, irq_cause, irq_mask; 216 217 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); 218 irq_cause &= IRQ_TIMER_WD_CLR; 219 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); 220 221 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK); 222 irq_mask |= IRQ_TIMER_WD_MASK; 223 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); 224 225 val = read_cpu_ctrl(RSTOUTn_MASK); 226 val |= WD_RST_OUT_EN; 227 write_cpu_ctrl(RSTOUTn_MASK, val); 228 229 val = mv_get_timer_control(); 230 val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO; 231 mv_set_timer_control(val); 232 } 233 234 static inline void 235 mv_wdt_enable_armada_38x_xp_helper() 236 { 237 uint32_t val, irq_cause; 238 239 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); 240 irq_cause &= IRQ_TIMER_WD_CLR; 241 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); 242 243 val = read_cpu_mp_clocks(WD_RSTOUTn_MASK); 244 val |= (WD_GLOBAL_MASK | WD_CPU0_MASK); 245 write_cpu_mp_clocks(WD_RSTOUTn_MASK, val); 246 247 val = read_cpu_misc(RSTOUTn_MASK_ARMV7); 248 val &= ~RSTOUTn_MASK_WD; 249 write_cpu_misc(RSTOUTn_MASK_ARMV7, val); 250 } 251 252 static void 253 mv_wdt_enable_armada_38x(void) 254 { 255 uint32_t val, irq_cause; 256 257 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); 258 irq_cause &= IRQ_TIMER_WD_CLR; 259 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); 260 261 mv_wdt_enable_armada_38x_xp_helper(); 262 263 val = mv_get_timer_control(); 264 val |= CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO | CPU_TIMER_WD_25MHZ_EN; 265 mv_set_timer_control(val); 266 } 267 268 static void 269 mv_wdt_enable_armada_xp(void) 270 { 271 uint32_t val, irq_cause; 272 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE_ARMADAXP); 273 irq_cause &= IRQ_TIMER_WD_CLR_ARMADAXP; 274 write_cpu_ctrl(BRIDGE_IRQ_CAUSE_ARMADAXP, irq_cause); 275 276 mv_wdt_enable_armada_38x_xp_helper(); 277 278 val = mv_get_timer_control(); 279 val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO | CPU_TIMER_WD_25MHZ_EN; 280 mv_set_timer_control(val); 281 } 282 283 static void 284 mv_wdt_disable_armv5(void) 285 { 286 uint32_t val, irq_cause, irq_mask; 287 288 val = mv_get_timer_control(); 289 val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO); 290 mv_set_timer_control(val); 291 292 val = read_cpu_ctrl(RSTOUTn_MASK); 293 val &= ~WD_RST_OUT_EN; 294 write_cpu_ctrl(RSTOUTn_MASK, val); 295 296 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK); 297 irq_mask &= ~(IRQ_TIMER_WD_MASK); 298 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); 299 300 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); 301 irq_cause &= IRQ_TIMER_WD_CLR; 302 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); 303 } 304 305 static __inline void 306 mv_wdt_disable_armada_38x_xp_helper(void) 307 { 308 uint32_t val; 309 310 val = read_cpu_mp_clocks(WD_RSTOUTn_MASK); 311 val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK); 312 write_cpu_mp_clocks(WD_RSTOUTn_MASK, val); 313 314 val = read_cpu_misc(RSTOUTn_MASK_ARMV7); 315 val |= RSTOUTn_MASK_WD; 316 write_cpu_misc(RSTOUTn_MASK_ARMV7, RSTOUTn_MASK_WD); 317 } 318 319 static void 320 mv_wdt_disable_armada_38x(void) 321 { 322 uint32_t val; 323 324 val = mv_get_timer_control(); 325 val &= ~(CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO); 326 mv_set_timer_control(val); 327 328 mv_wdt_disable_armada_38x_xp_helper(); 329 } 330 331 static void 332 mv_wdt_disable_armada_xp(void) 333 { 334 uint32_t val; 335 336 val = mv_get_timer_control(); 337 val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO); 338 mv_set_timer_control(val); 339 340 mv_wdt_disable_armada_38x_xp_helper(); 341 } 342 343 /* 344 * Watchdog event handler. 345 */ 346 static void 347 mv_watchdog_event(void *arg, unsigned int cmd, int *error) 348 { 349 struct mv_wdt_softc *sc; 350 uint64_t ns; 351 uint64_t ticks; 352 353 sc = arg; 354 mtx_lock(&sc->wdt_mtx); 355 if (cmd == 0) { 356 if (wdt_softc->wdt_config->wdt_disable != NULL) 357 wdt_softc->wdt_config->wdt_disable(); 358 } else { 359 /* 360 * Watchdog timeout is in nanosecs, calculation according to 361 * watchdog(9) 362 */ 363 ns = (uint64_t)1 << (cmd & WD_INTERVAL); 364 ticks = (uint64_t)(ns * sc->wdt_config->wdt_clock_src) / 1000000000; 365 if (ticks > MAX_WATCHDOG_TICKS) { 366 if (wdt_softc->wdt_config->wdt_disable != NULL) 367 wdt_softc->wdt_config->wdt_disable(); 368 } 369 else { 370 mv_set_timer(wdt_softc->wdt_config->wdt_timer, ticks); 371 if (wdt_softc->wdt_config->wdt_enable != NULL) 372 wdt_softc->wdt_config->wdt_enable(); 373 *error = 0; 374 } 375 } 376 mtx_unlock(&sc->wdt_mtx); 377 }
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