1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 1994-1998 Mark Brinicombe.
5 * Copyright (c) 1994 Brini.
6 * All rights reserved.
7 *
8 * This code is derived from software written for Brini by Mark Brinicombe
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by Brini.
21 * 4. The name of the company nor the name of the author may be used to
22 * endorse or promote products derived from this software without specific
23 * prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
26 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
27 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * SUCH DAMAGE.
36 *
37 * from: FreeBSD: //depot/projects/arm/src/sys/arm/at91/kb920x_machdep.c, rev 45
38 */
39
40 #include "opt_ddb.h"
41 #include "opt_platform.h"
42
43 #include <sys/cdefs.h>
44 __FBSDID("$FreeBSD: releng/12.0/sys/arm/mv/armv5_machdep.c 332274 2018-04-08 12:20:06Z andrew $");
45
46 #define _ARM32_BUS_DMA_PRIVATE
47 #include <sys/param.h>
48 #include <sys/systm.h>
49 #include <sys/bus.h>
50 #include <sys/devmap.h>
51 #include <sys/kernel.h>
52
53 #include <vm/vm.h>
54 #include <vm/pmap.h>
55
56 #include <arm/arm/mpcore_timervar.h>
57 #include <arm/arm/nexusvar.h>
58
59 #include <machine/bus.h>
60 #include <machine/fdt.h>
61 #include <machine/machdep.h>
62 #include <machine/platform.h>
63
64 #include <machine/cpu-v4.h>
65
66 #include <arm/mv/mvreg.h> /* XXX */
67 #include <arm/mv/mvvar.h> /* XXX eventually this should be eliminated */
68 #include <arm/mv/mvwin.h>
69
70 #include <dev/fdt/fdt_common.h>
71 #include <dev/ofw/ofw_bus_subr.h>
72
73 static int platform_mpp_init(void);
74 void cpu_reset(void);
75
76 #define MPP_PIN_MAX 68
77 #define MPP_PIN_CELLS 2
78 #define MPP_PINS_PER_REG 8
79 #define MPP_SEL(pin,func) (((func) & 0xf) << \
80 (((pin) % MPP_PINS_PER_REG) * 4))
81
82 static void
83 mv_busdma_tag_init(void *arg __unused)
84 {
85 phandle_t node;
86 bus_dma_tag_t dmat;
87
88 /*
89 * If this platform has coherent DMA, create the parent DMA tag to pass
90 * down the coherent flag to all busses and devices on the platform,
91 * otherwise return without doing anything. By default create tag
92 * for all A38x-based platforms only.
93 */
94 if ((node = OF_finddevice("/")) == -1)
95 return;
96 if (ofw_bus_node_is_compatible(node, "marvell,armada380") == 0)
97 return;
98
99 bus_dma_tag_create(NULL, /* No parent tag */
100 1, 0, /* alignment, bounds */
101 BUS_SPACE_MAXADDR, /* lowaddr */
102 BUS_SPACE_MAXADDR, /* highaddr */
103 NULL, NULL, /* filter, filterarg */
104 BUS_SPACE_MAXSIZE, /* maxsize */
105 BUS_SPACE_UNRESTRICTED, /* nsegments */
106 BUS_SPACE_MAXSIZE, /* maxsegsize */
107 BUS_DMA_COHERENT, /* flags */
108 NULL, NULL, /* lockfunc, lockarg */
109 &dmat);
110
111 nexus_set_dma_tag(dmat);
112 }
113 SYSINIT(mv_busdma_tag, SI_SUB_DRIVERS, SI_ORDER_ANY, mv_busdma_tag_init, NULL);
114
115 static int
116 platform_mpp_init(void)
117 {
118 pcell_t pinmap[MPP_PIN_MAX * MPP_PIN_CELLS];
119 int mpp[MPP_PIN_MAX];
120 uint32_t ctrl_val, ctrl_offset;
121 pcell_t reg[4];
122 u_long start, size;
123 phandle_t node;
124 pcell_t pin_cells, *pinmap_ptr, pin_count;
125 ssize_t len;
126 int par_addr_cells, par_size_cells;
127 int tuple_size, tuples, rv, pins, i, j;
128 int mpp_pin, mpp_function;
129
130 /*
131 * Try to access the MPP node directly i.e. through /aliases/mpp.
132 */
133 if ((node = OF_finddevice("mpp")) != -1)
134 if (ofw_bus_node_is_compatible(node, "mrvl,mpp"))
135 goto moveon;
136 /*
137 * Find the node the long way.
138 */
139 if ((node = OF_finddevice("/")) == -1)
140 return (ENXIO);
141
142 if ((node = fdt_find_compatible(node, "simple-bus", 0)) == 0)
143 return (ENXIO);
144
145 if ((node = fdt_find_compatible(node, "mrvl,mpp", 0)) == 0)
146 /*
147 * No MPP node. Fall back to how MPP got set by the
148 * first-stage loader and try to continue booting.
149 */
150 return (0);
151 moveon:
152 /*
153 * Process 'reg' prop.
154 */
155 if ((rv = fdt_addrsize_cells(OF_parent(node), &par_addr_cells,
156 &par_size_cells)) != 0)
157 return(ENXIO);
158
159 tuple_size = sizeof(pcell_t) * (par_addr_cells + par_size_cells);
160 len = OF_getprop(node, "reg", reg, sizeof(reg));
161 tuples = len / tuple_size;
162 if (tuple_size <= 0)
163 return (EINVAL);
164
165 /*
166 * Get address/size. XXX we assume only the first 'reg' tuple is used.
167 */
168 rv = fdt_data_to_res(reg, par_addr_cells, par_size_cells,
169 &start, &size);
170 if (rv != 0)
171 return (rv);
172 start += fdt_immr_va;
173
174 /*
175 * Process 'pin-count' and 'pin-map' props.
176 */
177 if (OF_getencprop(node, "pin-count", &pin_count, sizeof(pin_count)) <= 0)
178 return (ENXIO);
179 if (pin_count > MPP_PIN_MAX)
180 return (ERANGE);
181
182 if (OF_getencprop(node, "#pin-cells", &pin_cells, sizeof(pin_cells)) <= 0)
183 pin_cells = MPP_PIN_CELLS;
184 if (pin_cells > MPP_PIN_CELLS)
185 return (ERANGE);
186 tuple_size = sizeof(pcell_t) * pin_cells;
187
188 bzero(pinmap, sizeof(pinmap));
189 len = OF_getencprop(node, "pin-map", pinmap, sizeof(pinmap));
190 if (len <= 0)
191 return (ERANGE);
192 if (len % tuple_size)
193 return (ERANGE);
194 pins = len / tuple_size;
195 if (pins > pin_count)
196 return (ERANGE);
197 /*
198 * Fill out a "mpp[pin] => function" table. All pins unspecified in
199 * the 'pin-map' property are defaulted to 0 function i.e. GPIO.
200 */
201 bzero(mpp, sizeof(mpp));
202 pinmap_ptr = pinmap;
203 for (i = 0; i < pins; i++) {
204 mpp_pin = *pinmap_ptr;
205 mpp_function = *(pinmap_ptr + 1);
206 mpp[mpp_pin] = mpp_function;
207 pinmap_ptr += pin_cells;
208 }
209
210 /*
211 * Prepare and program MPP control register values.
212 */
213 ctrl_offset = 0;
214 for (i = 0; i < pin_count;) {
215 ctrl_val = 0;
216
217 for (j = 0; j < MPP_PINS_PER_REG; j++) {
218 if (i + j == pin_count - 1)
219 break;
220 ctrl_val |= MPP_SEL(i + j, mpp[i + j]);
221 }
222 i += MPP_PINS_PER_REG;
223 bus_space_write_4(fdtbus_bs_tag, start, ctrl_offset,
224 ctrl_val);
225
226 #if defined(SOC_MV_ORION)
227 /*
228 * Third MPP reg on Orion SoC is placed
229 * non-linearly (with different offset).
230 */
231 if (i == (2 * MPP_PINS_PER_REG))
232 ctrl_offset = 0x50;
233 else
234 #endif
235 ctrl_offset += 4;
236 }
237
238 return (0);
239 }
240
241 vm_offset_t
242 platform_lastaddr(void)
243 {
244
245 return (fdt_immr_va);
246 }
247
248 void
249 platform_probe_and_attach(void)
250 {
251
252 if (fdt_immr_addr(MV_BASE) != 0)
253 while (1);
254 }
255
256 void
257 platform_gpio_init(void)
258 {
259
260 /*
261 * Re-initialise MPP. It is important to call this prior to using
262 * console as the physical connection can be routed via MPP.
263 */
264 if (platform_mpp_init() != 0)
265 while (1);
266 }
267
268 void
269 platform_late_init(void)
270 {
271 /*
272 * Re-initialise decode windows
273 */
274 if (mv_check_soc_family() == MV_SOC_UNSUPPORTED)
275 panic("Unsupported SoC family\n");
276
277 if (soc_decode_win() != 0)
278 printf("WARNING: could not re-initialise decode windows! "
279 "Running with existing settings...\n");
280 }
281 #define FDT_DEVMAP_MAX (MV_WIN_CPU_MAX + 2)
282 static struct devmap_entry fdt_devmap[FDT_DEVMAP_MAX] = {
283 { 0, 0, 0, }
284 };
285
286 static int
287 platform_sram_devmap(struct devmap_entry *map)
288 {
289 phandle_t child, root;
290 u_long base, size;
291 /*
292 * SRAM range.
293 */
294 if ((root = OF_finddevice("/")) == 0)
295 return (ENXIO);
296
297 if ((child = OF_finddevice("/sram")) != 0)
298 if (ofw_bus_node_is_compatible(child, "mrvl,cesa-sram") ||
299 ofw_bus_node_is_compatible(child, "mrvl,scratchpad"))
300 goto moveon;
301
302 if ((child = fdt_find_compatible(root, "mrvl,cesa-sram", 0)) == 0 &&
303 (child = fdt_find_compatible(root, "mrvl,scratchpad", 0)) == 0)
304 goto out;
305
306 moveon:
307 if (fdt_regsize(child, &base, &size) != 0)
308 return (EINVAL);
309
310 map->pd_va = MV_CESA_SRAM_BASE; /* XXX */
311 map->pd_pa = base;
312 map->pd_size = size;
313
314 return (0);
315 out:
316 return (ENOENT);
317
318 }
319
320 /*
321 * Supply a default do-nothing implementation of mv_pci_devmap() via a weak
322 * alias. Many Marvell platforms don't support a PCI interface, but to support
323 * those that do, we end up with a reference to this function below, in
324 * platform_devmap_init(). If "device pci" appears in the kernel config, the
325 * real implementation of this function in arm/mv/mv_pci.c overrides the weak
326 * alias defined here.
327 */
328 int mv_default_fdt_pci_devmap(phandle_t node, struct devmap_entry *devmap,
329 vm_offset_t io_va, vm_offset_t mem_va);
330 int
331 mv_default_fdt_pci_devmap(phandle_t node, struct devmap_entry *devmap,
332 vm_offset_t io_va, vm_offset_t mem_va)
333 {
334
335 return (0);
336 }
337 __weak_reference(mv_default_fdt_pci_devmap, mv_pci_devmap);
338
339 /*
340 * XXX: When device entry in devmap has pd_size smaller than section size,
341 * system will freeze during initialization
342 */
343
344 /*
345 * Construct devmap table with DT-derived config data.
346 */
347 int
348 platform_devmap_init(void)
349 {
350 phandle_t root, child;
351 pcell_t bank_count;
352 int i, num_mapped;
353
354 i = 0;
355 devmap_register_table(&fdt_devmap[0]);
356
357 if ((root = OF_finddevice("/")) == -1)
358 return (ENXIO);
359
360 /*
361 * IMMR range.
362 */
363 fdt_devmap[i].pd_va = fdt_immr_va;
364 fdt_devmap[i].pd_pa = fdt_immr_pa;
365 fdt_devmap[i].pd_size = fdt_immr_size;
366 i++;
367
368 /*
369 * SRAM range.
370 */
371 if (i < FDT_DEVMAP_MAX)
372 if (platform_sram_devmap(&fdt_devmap[i]) == 0)
373 i++;
374
375 /*
376 * PCI range(s).
377 * PCI range(s) and localbus.
378 */
379 for (child = OF_child(root); child != 0; child = OF_peer(child)) {
380 if (mv_fdt_is_type(child, "pci") ||
381 mv_fdt_is_type(child, "pciep")) {
382 /*
383 * Check space: each PCI node will consume 2 devmap
384 * entries.
385 */
386 if (i + 1 >= FDT_DEVMAP_MAX)
387 return (ENOMEM);
388
389 /*
390 * XXX this should account for PCI and multiple ranges
391 * of a given kind.
392 */
393 if (mv_pci_devmap(child, &fdt_devmap[i], MV_PCI_VA_IO_BASE,
394 MV_PCI_VA_MEM_BASE) != 0)
395 return (ENXIO);
396 i += 2;
397 }
398
399 if (ofw_bus_node_is_compatible(child, "mrvl,lbc")) {
400 /* Check available space */
401 if (OF_getencprop(child, "bank-count", &bank_count,
402 sizeof(bank_count)) <= 0)
403 /* If no property, use default value */
404 bank_count = 1;
405
406 if ((i + bank_count) >= FDT_DEVMAP_MAX)
407 return (ENOMEM);
408
409 /* Add all localbus ranges to device map */
410 num_mapped = 0;
411
412 if (fdt_localbus_devmap(child, &fdt_devmap[i],
413 (int)bank_count, &num_mapped) != 0)
414 return (ENXIO);
415
416 i += num_mapped;
417 }
418 }
419
420 return (0);
421 }
422
423 struct arm32_dma_range *
424 bus_dma_get_range(void)
425 {
426
427 return (NULL);
428 }
429
430 int
431 bus_dma_get_range_nb(void)
432 {
433
434 return (0);
435 }
436
437 void
438 cpu_reset(void)
439 {
440
441 write_cpu_ctrl(RSTOUTn_MASK, SOFT_RST_OUT_EN);
442 write_cpu_ctrl(SYSTEM_SOFT_RESET, SYS_SOFT_RST);
443 while(1);
444 }
445
446 #ifdef DDB
447 #include <ddb/ddb.h>
448
449 DB_SHOW_COMMAND(cp15, db_show_cp15)
450 {
451 u_int reg;
452
453 __asm __volatile("mrc p15, 0, %0, c0, c0, 0" : "=r" (reg));
454 db_printf("Cpu ID: 0x%08x\n", reg);
455 __asm __volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (reg));
456 db_printf("Current Cache Lvl ID: 0x%08x\n",reg);
457
458 reg = cp15_sctlr_get();
459 db_printf("Ctrl: 0x%08x\n",reg);
460 reg = cp15_actlr_get();
461 db_printf("Aux Ctrl: 0x%08x\n",reg);
462
463 __asm __volatile("mrc p15, 0, %0, c0, c1, 0" : "=r" (reg));
464 db_printf("Processor Feat 0: 0x%08x\n", reg);
465 __asm __volatile("mrc p15, 0, %0, c0, c1, 1" : "=r" (reg));
466 db_printf("Processor Feat 1: 0x%08x\n", reg);
467 __asm __volatile("mrc p15, 0, %0, c0, c1, 2" : "=r" (reg));
468 db_printf("Debug Feat 0: 0x%08x\n", reg);
469 __asm __volatile("mrc p15, 0, %0, c0, c1, 3" : "=r" (reg));
470 db_printf("Auxiliary Feat 0: 0x%08x\n", reg);
471 __asm __volatile("mrc p15, 0, %0, c0, c1, 4" : "=r" (reg));
472 db_printf("Memory Model Feat 0: 0x%08x\n", reg);
473 __asm __volatile("mrc p15, 0, %0, c0, c1, 5" : "=r" (reg));
474 db_printf("Memory Model Feat 1: 0x%08x\n", reg);
475 __asm __volatile("mrc p15, 0, %0, c0, c1, 6" : "=r" (reg));
476 db_printf("Memory Model Feat 2: 0x%08x\n", reg);
477 __asm __volatile("mrc p15, 0, %0, c0, c1, 7" : "=r" (reg));
478 db_printf("Memory Model Feat 3: 0x%08x\n", reg);
479
480 __asm __volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (reg));
481 db_printf("Aux Func Modes Ctrl 0: 0x%08x\n",reg);
482 __asm __volatile("mrc p15, 1, %0, c15, c2, 1" : "=r" (reg));
483 db_printf("Aux Func Modes Ctrl 1: 0x%08x\n",reg);
484
485 __asm __volatile("mrc p15, 1, %0, c15, c12, 0" : "=r" (reg));
486 db_printf("CPU ID code extension: 0x%08x\n",reg);
487 }
488
489 DB_SHOW_COMMAND(vtop, db_show_vtop)
490 {
491 u_int reg;
492
493 if (have_addr) {
494 __asm __volatile("mcr p15, 0, %0, c7, c8, 0" : : "r" (addr));
495 __asm __volatile("mrc p15, 0, %0, c7, c4, 0" : "=r" (reg));
496 db_printf("Physical address reg: 0x%08x\n",reg);
497 } else
498 db_printf("show vtop <virt_addr>\n");
499 }
500 #endif /* DDB */
Cache object: a4f65516c37fa979ae1d432f498c535b
|