The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/arm/mv/common.c

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    1 /*-
    2  * Copyright (C) 2008-2011 MARVELL INTERNATIONAL LTD.
    3  * All rights reserved.
    4  *
    5  * Developed by Semihalf.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  * 3. Neither the name of MARVELL nor the names of contributors
   16  *    may be used to endorse or promote products derived from this software
   17  *    without specific prior written permission.
   18  *
   19  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   22  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
   23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   29  * SUCH DAMAGE.
   30  */
   31 
   32 #include "opt_global.h"
   33 
   34 #include <sys/cdefs.h>
   35 __FBSDID("$FreeBSD: releng/10.0/sys/arm/mv/common.c 250324 2013-05-07 06:42:07Z gber $");
   36 
   37 #include <sys/param.h>
   38 #include <sys/systm.h>
   39 #include <sys/bus.h>
   40 #include <sys/kernel.h>
   41 #include <sys/malloc.h>
   42 #include <sys/kdb.h>
   43 #include <sys/reboot.h>
   44 
   45 #include <dev/fdt/fdt_common.h>
   46 #include <dev/ofw/openfirm.h>
   47 
   48 #include <machine/bus.h>
   49 #include <machine/fdt.h>
   50 #include <machine/vmparam.h>
   51 
   52 #include <arm/mv/mvreg.h>
   53 #include <arm/mv/mvvar.h>
   54 #include <arm/mv/mvwin.h>
   55 
   56 
   57 MALLOC_DEFINE(M_IDMA, "idma", "idma dma test memory");
   58 
   59 #define IDMA_DEBUG
   60 #undef IDMA_DEBUG
   61 
   62 #define MAX_CPU_WIN     5
   63 
   64 #ifdef DEBUG
   65 #define debugf(fmt, args...) do { printf("%s(): ", __func__);   \
   66     printf(fmt,##args); } while (0)
   67 #else
   68 #define debugf(fmt, args...)
   69 #endif
   70 
   71 #ifdef DEBUG
   72 #define MV_DUMP_WIN     1
   73 #else
   74 #define MV_DUMP_WIN     0
   75 #endif
   76 
   77 static int win_eth_can_remap(int i);
   78 
   79 #ifndef SOC_MV_FREY
   80 static int decode_win_cpu_valid(void);
   81 #endif
   82 static int decode_win_usb_valid(void);
   83 static int decode_win_eth_valid(void);
   84 static int decode_win_pcie_valid(void);
   85 static int decode_win_sata_valid(void);
   86 
   87 static int decode_win_idma_valid(void);
   88 static int decode_win_xor_valid(void);
   89 
   90 #ifndef SOC_MV_FREY
   91 static void decode_win_cpu_setup(void);
   92 #endif
   93 #ifdef SOC_MV_ARMADAXP
   94 static int decode_win_sdram_fixup(void);
   95 #endif
   96 static void decode_win_usb_setup(u_long);
   97 static void decode_win_eth_setup(u_long);
   98 static void decode_win_sata_setup(u_long);
   99 
  100 static void decode_win_idma_setup(u_long);
  101 static void decode_win_xor_setup(u_long);
  102 
  103 static void decode_win_usb_dump(u_long);
  104 static void decode_win_eth_dump(u_long base);
  105 static void decode_win_idma_dump(u_long base);
  106 static void decode_win_xor_dump(u_long base);
  107 
  108 static int fdt_get_ranges(const char *, void *, int, int *, int *);
  109 
  110 static int win_cpu_from_dt(void);
  111 static int fdt_win_setup(void);
  112 
  113 static uint32_t dev_mask = 0;
  114 static int cpu_wins_no = 0;
  115 static int eth_port = 0;
  116 static int usb_port = 0;
  117 
  118 static struct decode_win cpu_win_tbl[MAX_CPU_WIN];
  119 
  120 const struct decode_win *cpu_wins = cpu_win_tbl;
  121 
  122 typedef void (*decode_win_setup_t)(u_long);
  123 typedef void (*dump_win_t)(u_long);
  124 
  125 struct soc_node_spec {
  126         const char              *compat;
  127         decode_win_setup_t      decode_handler;
  128         dump_win_t              dump_handler;
  129 };
  130 
  131 static struct soc_node_spec soc_nodes[] = {
  132         { "mrvl,ge", &decode_win_eth_setup, &decode_win_eth_dump },
  133         { "mrvl,usb-ehci", &decode_win_usb_setup, &decode_win_usb_dump },
  134         { "mrvl,sata", &decode_win_sata_setup, NULL },
  135         { "mrvl,xor", &decode_win_xor_setup, &decode_win_xor_dump },
  136         { "mrvl,idma", &decode_win_idma_setup, &decode_win_idma_dump },
  137         { "mrvl,pcie", &decode_win_pcie_setup, NULL },
  138         { NULL, NULL, NULL },
  139 };
  140 
  141 struct fdt_pm_mask_entry fdt_pm_mask_table[] = {
  142         { "mrvl,ge",            CPU_PM_CTRL_GE(0) },
  143         { "mrvl,ge",            CPU_PM_CTRL_GE(1) },
  144         { "mrvl,usb-ehci",      CPU_PM_CTRL_USB(0) },
  145         { "mrvl,usb-ehci",      CPU_PM_CTRL_USB(1) },
  146         { "mrvl,usb-ehci",      CPU_PM_CTRL_USB(2) },
  147         { "mrvl,xor",           CPU_PM_CTRL_XOR },
  148         { "mrvl,sata",          CPU_PM_CTRL_SATA },
  149 
  150         { NULL, 0 }
  151 };
  152 
  153 static __inline int
  154 pm_is_disabled(uint32_t mask)
  155 {
  156 
  157         return (soc_power_ctrl_get(mask) == mask ? 0 : 1);
  158 }
  159 
  160 /*
  161  * Disable device using power management register.
  162  * 1 - Device Power On
  163  * 0 - Device Power Off
  164  * Mask can be set in loader.
  165  * EXAMPLE:
  166  * loader> set hw.pm-disable-mask=0x2
  167  *
  168  * Common mask:
  169  * |-------------------------------|
  170  * | Device | Kirkwood | Discovery |
  171  * |-------------------------------|
  172  * | USB0   | 0x00008  | 0x020000  |
  173  * |-------------------------------|
  174  * | USB1   |     -    | 0x040000  |
  175  * |-------------------------------|
  176  * | USB2   |     -    | 0x080000  |
  177  * |-------------------------------|
  178  * | GE0    | 0x00001  | 0x000002  |
  179  * |-------------------------------|
  180  * | GE1    |     -    | 0x000004  |
  181  * |-------------------------------|
  182  * | IDMA   |     -    | 0x100000  |
  183  * |-------------------------------|
  184  * | XOR    | 0x10000  | 0x200000  |
  185  * |-------------------------------|
  186  * | CESA   | 0x20000  | 0x400000  |
  187  * |-------------------------------|
  188  * | SATA   | 0x04000  | 0x004000  |
  189  * --------------------------------|
  190  * This feature can be used only on Kirkwood and Discovery
  191  * machines.
  192  */
  193 static __inline void
  194 pm_disable_device(int mask)
  195 {
  196 #ifdef DIAGNOSTIC
  197         uint32_t reg;
  198 
  199         reg = soc_power_ctrl_get(CPU_PM_CTRL_ALL);
  200         printf("Power Management Register: 0%x\n", reg);
  201 
  202         reg &= ~mask;
  203         soc_power_ctrl_set(reg);
  204         printf("Device %x is disabled\n", mask);
  205 
  206         reg = soc_power_ctrl_get(CPU_PM_CTRL_ALL);
  207         printf("Power Management Register: 0%x\n", reg);
  208 #endif
  209 }
  210 
  211 int
  212 fdt_pm(phandle_t node)
  213 {
  214         uint32_t cpu_pm_ctrl;
  215         int i, ena, compat;
  216 
  217         ena = 1;
  218         cpu_pm_ctrl = read_cpu_ctrl(CPU_PM_CTRL);
  219         for (i = 0; fdt_pm_mask_table[i].compat != NULL; i++) {
  220                 if (dev_mask & (1 << i))
  221                         continue;
  222 
  223                 compat = fdt_is_compatible(node, fdt_pm_mask_table[i].compat);
  224 
  225                 if (compat && (~cpu_pm_ctrl & fdt_pm_mask_table[i].mask)) {
  226                         dev_mask |= (1 << i);
  227                         ena = 0;
  228                         break;
  229                 } else if (compat) {
  230                         dev_mask |= (1 << i);
  231                         break;
  232                 }
  233         }
  234 
  235         return (ena);
  236 }
  237 
  238 uint32_t
  239 read_cpu_ctrl(uint32_t reg)
  240 {
  241 
  242         return (bus_space_read_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg));
  243 }
  244 
  245 void
  246 write_cpu_ctrl(uint32_t reg, uint32_t val)
  247 {
  248 
  249         bus_space_write_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg, val);
  250 }
  251 
  252 #if defined(SOC_MV_ARMADAXP)
  253 uint32_t
  254 read_cpu_mp_clocks(uint32_t reg)
  255 {
  256 
  257         return (bus_space_read_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg));
  258 }
  259 
  260 void
  261 write_cpu_mp_clocks(uint32_t reg, uint32_t val)
  262 {
  263 
  264         bus_space_write_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg, val);
  265 }
  266 
  267 uint32_t
  268 read_cpu_misc(uint32_t reg)
  269 {
  270 
  271         return (bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, reg));
  272 }
  273 
  274 void
  275 write_cpu_misc(uint32_t reg, uint32_t val)
  276 {
  277 
  278         bus_space_write_4(fdtbus_bs_tag, MV_MISC_BASE, reg, val);
  279 }
  280 #endif
  281 
  282 void
  283 cpu_reset(void)
  284 {
  285 
  286 #if defined(SOC_MV_ARMADAXP)
  287         write_cpu_misc(RSTOUTn_MASK, SOFT_RST_OUT_EN);
  288         write_cpu_misc(SYSTEM_SOFT_RESET, SYS_SOFT_RST);
  289 #else
  290         write_cpu_ctrl(RSTOUTn_MASK, SOFT_RST_OUT_EN);
  291         write_cpu_ctrl(SYSTEM_SOFT_RESET, SYS_SOFT_RST);
  292 #endif
  293         while (1);
  294 }
  295 
  296 uint32_t
  297 cpu_extra_feat(void)
  298 {
  299         uint32_t dev, rev;
  300         uint32_t ef = 0;
  301 
  302         soc_id(&dev, &rev);
  303 
  304         switch (dev) {
  305         case MV_DEV_88F6281:
  306         case MV_DEV_88F6282:
  307         case MV_DEV_88RC8180:
  308         case MV_DEV_MV78100_Z0:
  309         case MV_DEV_MV78100:
  310                 __asm __volatile("mrc p15, 1, %0, c15, c1, 0" : "=r" (ef));
  311                 break;
  312         case MV_DEV_88F5182:
  313         case MV_DEV_88F5281:
  314                 __asm __volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (ef));
  315                 break;
  316         default:
  317                 if (bootverbose)
  318                         printf("This ARM Core does not support any extra features\n");
  319         }
  320 
  321         return (ef);
  322 }
  323 
  324 /*
  325  * Get the power status of device. This feature is only supported on
  326  * Kirkwood and Discovery SoCs.
  327  */
  328 uint32_t
  329 soc_power_ctrl_get(uint32_t mask)
  330 {
  331 
  332 #if !defined(SOC_MV_ORION) && !defined(SOC_MV_LOKIPLUS) && !defined(SOC_MV_FREY)
  333         if (mask != CPU_PM_CTRL_NONE)
  334                 mask &= read_cpu_ctrl(CPU_PM_CTRL);
  335 
  336         return (mask);
  337 #else
  338         return (mask);
  339 #endif
  340 }
  341 
  342 /*
  343  * Set the power status of device. This feature is only supported on
  344  * Kirkwood and Discovery SoCs.
  345  */
  346 void
  347 soc_power_ctrl_set(uint32_t mask)
  348 {
  349 
  350 #if !defined(SOC_MV_ORION) && !defined(SOC_MV_LOKIPLUS)
  351         if (mask != CPU_PM_CTRL_NONE)
  352                 write_cpu_ctrl(CPU_PM_CTRL, mask);
  353 #endif
  354 }
  355 
  356 void
  357 soc_id(uint32_t *dev, uint32_t *rev)
  358 {
  359 
  360         /*
  361          * Notice: system identifiers are available in the registers range of
  362          * PCIE controller, so using this function is only allowed (and
  363          * possible) after the internal registers range has been mapped in via
  364          * pmap_devmap_bootstrap().
  365          */
  366         *dev = bus_space_read_4(fdtbus_bs_tag, MV_PCIE_BASE, 0) >> 16;
  367         *rev = bus_space_read_4(fdtbus_bs_tag, MV_PCIE_BASE, 8) & 0xff;
  368 }
  369 
  370 static void
  371 soc_identify(void)
  372 {
  373         uint32_t d, r, size, mode;
  374         const char *dev;
  375         const char *rev;
  376 
  377         soc_id(&d, &r);
  378 
  379         printf("SOC: ");
  380         if (bootverbose)
  381                 printf("(0x%4x:0x%02x) ", d, r);
  382 
  383         rev = "";
  384         switch (d) {
  385         case MV_DEV_88F5181:
  386                 dev = "Marvell 88F5181";
  387                 if (r == 3)
  388                         rev = "B1";
  389                 break;
  390         case MV_DEV_88F5182:
  391                 dev = "Marvell 88F5182";
  392                 if (r == 2)
  393                         rev = "A2";
  394                 break;
  395         case MV_DEV_88F5281:
  396                 dev = "Marvell 88F5281";
  397                 if (r == 4)
  398                         rev = "D0";
  399                 else if (r == 5)
  400                         rev = "D1";
  401                 else if (r == 6)
  402                         rev = "D2";
  403                 break;
  404         case MV_DEV_88F6281:
  405                 dev = "Marvell 88F6281";
  406                 if (r == 0)
  407                         rev = "Z0";
  408                 else if (r == 2)
  409                         rev = "A0";
  410                 else if (r == 3)
  411                         rev = "A1";
  412                 break;
  413         case MV_DEV_88RC8180:
  414                 dev = "Marvell 88RC8180";
  415                 break;
  416         case MV_DEV_88RC9480:
  417                 dev = "Marvell 88RC9480";
  418                 break;
  419         case MV_DEV_88RC9580:
  420                 dev = "Marvell 88RC9580";
  421                 break;
  422         case MV_DEV_88F6781:
  423                 dev = "Marvell 88F6781";
  424                 if (r == 2)
  425                         rev = "Y0";
  426                 break;
  427         case MV_DEV_88F6282:
  428                 dev = "Marvell 88F6282";
  429                 if (r == 0)
  430                         rev = "A0";
  431                 else if (r == 1)
  432                         rev = "A1";
  433                 break;
  434         case MV_DEV_MV78100_Z0:
  435                 dev = "Marvell MV78100 Z0";
  436                 break;
  437         case MV_DEV_MV78100:
  438                 dev = "Marvell MV78100";
  439                 break;
  440         case MV_DEV_MV78160:
  441                 dev = "Marvell MV78160";
  442                 break;
  443         case MV_DEV_MV78260:
  444                 dev = "Marvell MV78260";
  445                 break;
  446         case MV_DEV_MV78460:
  447                 dev = "Marvell MV78460";
  448                 break;
  449         default:
  450                 dev = "UNKNOWN";
  451                 break;
  452         }
  453 
  454         printf("%s", dev);
  455         if (*rev != '\0')
  456                 printf(" rev %s", rev);
  457         printf(", TClock %dMHz\n", get_tclk() / 1000 / 1000);
  458 
  459         mode = read_cpu_ctrl(CPU_CONFIG);
  460         printf("  Instruction cache prefetch %s, data cache prefetch %s\n",
  461             (mode & CPU_CONFIG_IC_PREF) ? "enabled" : "disabled",
  462             (mode & CPU_CONFIG_DC_PREF) ? "enabled" : "disabled");
  463 
  464         switch (d) {
  465         case MV_DEV_88F6281:
  466         case MV_DEV_88F6282:
  467                 mode = read_cpu_ctrl(CPU_L2_CONFIG) & CPU_L2_CONFIG_MODE;
  468                 printf("  256KB 4-way set-associative %s unified L2 cache\n",
  469                     mode ? "write-through" : "write-back");
  470                 break;
  471         case MV_DEV_MV78100:
  472                 mode = read_cpu_ctrl(CPU_CONTROL);
  473                 size = mode & CPU_CONTROL_L2_SIZE;
  474                 mode = mode & CPU_CONTROL_L2_MODE;
  475                 printf("  %s set-associative %s unified L2 cache\n",
  476                     size ? "256KB 4-way" : "512KB 8-way",
  477                     mode ? "write-through" : "write-back");
  478                 break;
  479         default:
  480                 break;
  481         }
  482 }
  483 
  484 static void
  485 platform_identify(void *dummy)
  486 {
  487 
  488         soc_identify();
  489 
  490         /*
  491          * XXX Board identification e.g. read out from FPGA or similar should
  492          * go here
  493          */
  494 }
  495 SYSINIT(platform_identify, SI_SUB_CPU, SI_ORDER_SECOND, platform_identify,
  496     NULL);
  497 
  498 #ifdef KDB
  499 static void
  500 mv_enter_debugger(void *dummy)
  501 {
  502 
  503         if (boothowto & RB_KDB)
  504                 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
  505 }
  506 SYSINIT(mv_enter_debugger, SI_SUB_CPU, SI_ORDER_ANY, mv_enter_debugger, NULL);
  507 #endif
  508 
  509 int
  510 soc_decode_win(void)
  511 {
  512         uint32_t dev, rev;
  513         int mask, err;
  514 
  515         mask = 0;
  516         TUNABLE_INT_FETCH("hw.pm-disable-mask", &mask);
  517 
  518         if (mask != 0)
  519                 pm_disable_device(mask);
  520 
  521         /* Retrieve data about physical addresses from device tree. */
  522         if ((err = win_cpu_from_dt()) != 0)
  523                 return (err);
  524 
  525         /* Retrieve our ID: some windows facilities vary between SoC models */
  526         soc_id(&dev, &rev);
  527 
  528 #ifdef SOC_MV_ARMADAXP
  529         if ((err = decode_win_sdram_fixup()) != 0)
  530                 return(err);
  531 #endif
  532 
  533 #ifndef SOC_MV_FREY
  534         if (!decode_win_cpu_valid() || !decode_win_usb_valid() ||
  535             !decode_win_eth_valid() || !decode_win_idma_valid() ||
  536             !decode_win_pcie_valid() || !decode_win_sata_valid() ||
  537             !decode_win_xor_valid())
  538                 return (EINVAL);
  539 
  540         decode_win_cpu_setup();
  541 #else
  542         if (!decode_win_usb_valid() ||
  543             !decode_win_eth_valid() || !decode_win_idma_valid() ||
  544             !decode_win_pcie_valid() || !decode_win_sata_valid() ||
  545             !decode_win_xor_valid())
  546                 return (EINVAL);
  547 #endif
  548         if (MV_DUMP_WIN)
  549                 soc_dump_decode_win();
  550 
  551         eth_port = 0;
  552         usb_port = 0;
  553         if ((err = fdt_win_setup()) != 0)
  554                 return (err);
  555 
  556         return (0);
  557 }
  558 
  559 /**************************************************************************
  560  * Decode windows registers accessors
  561  **************************************************************************/
  562 #if !defined(SOC_MV_FREY)
  563 WIN_REG_IDX_RD(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE)
  564 WIN_REG_IDX_RD(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE)
  565 WIN_REG_IDX_RD(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE)
  566 WIN_REG_IDX_RD(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE)
  567 WIN_REG_IDX_WR(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE)
  568 WIN_REG_IDX_WR(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE)
  569 WIN_REG_IDX_WR(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE)
  570 WIN_REG_IDX_WR(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE)
  571 #endif
  572 
  573 WIN_REG_BASE_IDX_RD(win_usb, cr, MV_WIN_USB_CTRL)
  574 WIN_REG_BASE_IDX_RD(win_usb, br, MV_WIN_USB_BASE)
  575 WIN_REG_BASE_IDX_WR(win_usb, cr, MV_WIN_USB_CTRL)
  576 WIN_REG_BASE_IDX_WR(win_usb, br, MV_WIN_USB_BASE)
  577 
  578 WIN_REG_BASE_IDX_RD(win_eth, br, MV_WIN_ETH_BASE)
  579 WIN_REG_BASE_IDX_RD(win_eth, sz, MV_WIN_ETH_SIZE)
  580 WIN_REG_BASE_IDX_RD(win_eth, har, MV_WIN_ETH_REMAP)
  581 WIN_REG_BASE_IDX_WR(win_eth, br, MV_WIN_ETH_BASE)
  582 WIN_REG_BASE_IDX_WR(win_eth, sz, MV_WIN_ETH_SIZE)
  583 WIN_REG_BASE_IDX_WR(win_eth, har, MV_WIN_ETH_REMAP)
  584 
  585 WIN_REG_BASE_IDX_RD2(win_xor, br, MV_WIN_XOR_BASE)
  586 WIN_REG_BASE_IDX_RD2(win_xor, sz, MV_WIN_XOR_SIZE)
  587 WIN_REG_BASE_IDX_RD2(win_xor, har, MV_WIN_XOR_REMAP)
  588 WIN_REG_BASE_IDX_RD2(win_xor, ctrl, MV_WIN_XOR_CTRL)
  589 WIN_REG_BASE_IDX_WR2(win_xor, br, MV_WIN_XOR_BASE)
  590 WIN_REG_BASE_IDX_WR2(win_xor, sz, MV_WIN_XOR_SIZE)
  591 WIN_REG_BASE_IDX_WR2(win_xor, har, MV_WIN_XOR_REMAP)
  592 WIN_REG_BASE_IDX_WR2(win_xor, ctrl, MV_WIN_XOR_CTRL)
  593 
  594 WIN_REG_BASE_RD(win_eth, bare, 0x290)
  595 WIN_REG_BASE_RD(win_eth, epap, 0x294)
  596 WIN_REG_BASE_WR(win_eth, bare, 0x290)
  597 WIN_REG_BASE_WR(win_eth, epap, 0x294)
  598 
  599 WIN_REG_BASE_IDX_RD(win_pcie, cr, MV_WIN_PCIE_CTRL);
  600 WIN_REG_BASE_IDX_RD(win_pcie, br, MV_WIN_PCIE_BASE);
  601 WIN_REG_BASE_IDX_RD(win_pcie, remap, MV_WIN_PCIE_REMAP);
  602 WIN_REG_BASE_IDX_WR(win_pcie, cr, MV_WIN_PCIE_CTRL);
  603 WIN_REG_BASE_IDX_WR(win_pcie, br, MV_WIN_PCIE_BASE);
  604 WIN_REG_BASE_IDX_WR(win_pcie, remap, MV_WIN_PCIE_REMAP);
  605 WIN_REG_BASE_IDX_RD(pcie_bar, br, MV_PCIE_BAR_BASE);
  606 WIN_REG_BASE_IDX_WR(pcie_bar, br, MV_PCIE_BAR_BASE);
  607 WIN_REG_BASE_IDX_WR(pcie_bar, brh, MV_PCIE_BAR_BASE_H);
  608 WIN_REG_BASE_IDX_WR(pcie_bar, cr, MV_PCIE_BAR_CTRL);
  609 
  610 WIN_REG_BASE_IDX_RD(win_idma, br, MV_WIN_IDMA_BASE)
  611 WIN_REG_BASE_IDX_RD(win_idma, sz, MV_WIN_IDMA_SIZE)
  612 WIN_REG_BASE_IDX_RD(win_idma, har, MV_WIN_IDMA_REMAP)
  613 WIN_REG_BASE_IDX_RD(win_idma, cap, MV_WIN_IDMA_CAP)
  614 WIN_REG_BASE_IDX_WR(win_idma, br, MV_WIN_IDMA_BASE)
  615 WIN_REG_BASE_IDX_WR(win_idma, sz, MV_WIN_IDMA_SIZE)
  616 WIN_REG_BASE_IDX_WR(win_idma, har, MV_WIN_IDMA_REMAP)
  617 WIN_REG_BASE_IDX_WR(win_idma, cap, MV_WIN_IDMA_CAP)
  618 WIN_REG_BASE_RD(win_idma, bare, 0xa80)
  619 WIN_REG_BASE_WR(win_idma, bare, 0xa80)
  620 
  621 WIN_REG_BASE_IDX_RD(win_sata, cr, MV_WIN_SATA_CTRL);
  622 WIN_REG_BASE_IDX_RD(win_sata, br, MV_WIN_SATA_BASE);
  623 WIN_REG_BASE_IDX_WR(win_sata, cr, MV_WIN_SATA_CTRL);
  624 WIN_REG_BASE_IDX_WR(win_sata, br, MV_WIN_SATA_BASE);
  625 #ifndef SOC_MV_DOVE
  626 WIN_REG_IDX_RD(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE)
  627 WIN_REG_IDX_RD(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE)
  628 WIN_REG_IDX_WR(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE)
  629 WIN_REG_IDX_WR(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE)
  630 #else
  631 /*
  632  * On 88F6781 (Dove) SoC DDR Controller is accessed through
  633  * single MBUS <-> AXI bridge. In this case we provide emulated
  634  * ddr_br_read() and ddr_sz_read() functions to keep compatibility
  635  * with common decoding windows setup code.
  636  */
  637 
  638 static inline uint32_t ddr_br_read(int i)
  639 {
  640         uint32_t mmap;
  641 
  642         /* Read Memory Address Map Register for CS i */
  643         mmap = bus_space_read_4(fdtbus_bs_tag, MV_DDR_CADR_BASE + (i * 0x10), 0);
  644 
  645         /* Return CS i base address */
  646         return (mmap & 0xFF000000);
  647 }
  648 
  649 static inline uint32_t ddr_sz_read(int i)
  650 {
  651         uint32_t mmap, size;
  652 
  653         /* Read Memory Address Map Register for CS i */
  654         mmap = bus_space_read_4(fdtbus_bs_tag, MV_DDR_CADR_BASE + (i * 0x10), 0);
  655 
  656         /* Extract size of CS space in 64kB units */
  657         size = (1 << ((mmap >> 16) & 0x0F));
  658 
  659         /* Return CS size and enable/disable status */
  660         return (((size - 1) << 16) | (mmap & 0x01));
  661 }
  662 #endif
  663 
  664 #if !defined(SOC_MV_FREY)
  665 /**************************************************************************
  666  * Decode windows helper routines
  667  **************************************************************************/
  668 void
  669 soc_dump_decode_win(void)
  670 {
  671         uint32_t dev, rev;
  672         int i;
  673 
  674         soc_id(&dev, &rev);
  675 
  676         for (i = 0; i < MV_WIN_CPU_MAX; i++) {
  677                 printf("CPU window#%d: c 0x%08x, b 0x%08x", i,
  678                     win_cpu_cr_read(i),
  679                     win_cpu_br_read(i));
  680 
  681                 if (win_cpu_can_remap(i))
  682                         printf(", rl 0x%08x, rh 0x%08x",
  683                             win_cpu_remap_l_read(i),
  684                             win_cpu_remap_h_read(i));
  685 
  686                 printf("\n");
  687         }
  688         printf("Internal regs base: 0x%08x\n",
  689             bus_space_read_4(fdtbus_bs_tag, MV_INTREGS_BASE, 0));
  690 
  691         for (i = 0; i < MV_WIN_DDR_MAX; i++)
  692                 printf("DDR CS#%d: b 0x%08x, s 0x%08x\n", i,
  693                     ddr_br_read(i), ddr_sz_read(i));
  694 }
  695 
  696 /**************************************************************************
  697  * CPU windows routines
  698  **************************************************************************/
  699 int
  700 win_cpu_can_remap(int i)
  701 {
  702         uint32_t dev, rev;
  703 
  704         soc_id(&dev, &rev);
  705 
  706         /* Depending on the SoC certain windows have remap capability */
  707         if ((dev == MV_DEV_88F5182 && i < 2) ||
  708             (dev == MV_DEV_88F5281 && i < 4) ||
  709             (dev == MV_DEV_88F6281 && i < 4) ||
  710             (dev == MV_DEV_88F6282 && i < 4) ||
  711             (dev == MV_DEV_88RC8180 && i < 2) ||
  712             (dev == MV_DEV_88F6781 && i < 4) ||
  713             (dev == MV_DEV_MV78100_Z0 && i < 8) ||
  714             ((dev & MV_DEV_FAMILY_MASK) == MV_DEV_DISCOVERY && i < 8))
  715                 return (1);
  716 
  717         return (0);
  718 }
  719 
  720 /* XXX This should check for overlapping remap fields too.. */
  721 int
  722 decode_win_overlap(int win, int win_no, const struct decode_win *wintab)
  723 {
  724         const struct decode_win *tab;
  725         int i;
  726 
  727         tab = wintab;
  728 
  729         for (i = 0; i < win_no; i++, tab++) {
  730                 if (i == win)
  731                         /* Skip self */
  732                         continue;
  733 
  734                 if ((tab->base + tab->size - 1) < (wintab + win)->base)
  735                         continue;
  736 
  737                 else if (((wintab + win)->base + (wintab + win)->size - 1) <
  738                     tab->base)
  739                         continue;
  740                 else
  741                         return (i);
  742         }
  743 
  744         return (-1);
  745 }
  746 
  747 static int
  748 decode_win_cpu_valid(void)
  749 {
  750         int i, j, rv;
  751         uint32_t b, e, s;
  752 
  753         if (cpu_wins_no > MV_WIN_CPU_MAX) {
  754                 printf("CPU windows: too many entries: %d\n", cpu_wins_no);
  755                 return (0);
  756         }
  757 
  758         rv = 1;
  759         for (i = 0; i < cpu_wins_no; i++) {
  760 
  761                 if (cpu_wins[i].target == 0) {
  762                         printf("CPU window#%d: DDR target window is not "
  763                             "supposed to be reprogrammed!\n", i);
  764                         rv = 0;
  765                 }
  766 
  767                 if (cpu_wins[i].remap != ~0 && win_cpu_can_remap(i) != 1) {
  768                         printf("CPU window#%d: not capable of remapping, but "
  769                             "val 0x%08x defined\n", i, cpu_wins[i].remap);
  770                         rv = 0;
  771                 }
  772 
  773                 s = cpu_wins[i].size;
  774                 b = cpu_wins[i].base;
  775                 e = b + s - 1;
  776                 if (s > (0xFFFFFFFF - b + 1)) {
  777                         /*
  778                          * XXX this boundary check should account for 64bit
  779                          * and remapping..
  780                          */
  781                         printf("CPU window#%d: no space for size 0x%08x at "
  782                             "0x%08x\n", i, s, b);
  783                         rv = 0;
  784                         continue;
  785                 }
  786 
  787                 if (b != (b & ~(s - 1))) {
  788                         printf("CPU window#%d: address 0x%08x is not aligned "
  789                             "to 0x%08x\n", i, b, s);
  790                         rv = 0;
  791                         continue;
  792                 }
  793 
  794                 j = decode_win_overlap(i, cpu_wins_no, &cpu_wins[0]);
  795                 if (j >= 0) {
  796                         printf("CPU window#%d: (0x%08x - 0x%08x) overlaps "
  797                             "with #%d (0x%08x - 0x%08x)\n", i, b, e, j,
  798                             cpu_wins[j].base,
  799                             cpu_wins[j].base + cpu_wins[j].size - 1);
  800                         rv = 0;
  801                 }
  802         }
  803 
  804         return (rv);
  805 }
  806 
  807 int
  808 decode_win_cpu_set(int target, int attr, vm_paddr_t base, uint32_t size,
  809     vm_paddr_t remap)
  810 {
  811         uint32_t br, cr;
  812         int win, i;
  813 
  814         if (remap == ~0) {
  815                 win = MV_WIN_CPU_MAX - 1;
  816                 i = -1;
  817         } else {
  818                 win = 0;
  819                 i = 1;
  820         }
  821 
  822         while ((win >= 0) && (win < MV_WIN_CPU_MAX)) {
  823                 cr = win_cpu_cr_read(win);
  824                 if ((cr & MV_WIN_CPU_ENABLE_BIT) == 0)
  825                         break;
  826                 if ((cr & ((0xff << MV_WIN_CPU_ATTR_SHIFT) |
  827                     (0x1f << MV_WIN_CPU_TARGET_SHIFT))) ==
  828                     ((attr << MV_WIN_CPU_ATTR_SHIFT) |
  829                     (target << MV_WIN_CPU_TARGET_SHIFT)))
  830                         break;
  831                 win += i;
  832         }
  833         if ((win < 0) || (win >= MV_WIN_CPU_MAX) ||
  834             ((remap != ~0) && (win_cpu_can_remap(win) == 0)))
  835                 return (-1);
  836 
  837         br = base & 0xffff0000;
  838         win_cpu_br_write(win, br);
  839 
  840         if (win_cpu_can_remap(win)) {
  841                 if (remap != ~0) {
  842                         win_cpu_remap_l_write(win, remap & 0xffff0000);
  843                         win_cpu_remap_h_write(win, 0);
  844                 } else {
  845                         /*
  846                          * Remap function is not used for a given window
  847                          * (capable of remapping) - set remap field with the
  848                          * same value as base.
  849                          */
  850                         win_cpu_remap_l_write(win, base & 0xffff0000);
  851                         win_cpu_remap_h_write(win, 0);
  852                 }
  853         }
  854 
  855         cr = ((size - 1) & 0xffff0000) | (attr << MV_WIN_CPU_ATTR_SHIFT) |
  856             (target << MV_WIN_CPU_TARGET_SHIFT) | MV_WIN_CPU_ENABLE_BIT;
  857         win_cpu_cr_write(win, cr);
  858 
  859         return (0);
  860 }
  861 
  862 static void
  863 decode_win_cpu_setup(void)
  864 {
  865         int i;
  866 
  867         /* Disable all CPU windows */
  868         for (i = 0; i < MV_WIN_CPU_MAX; i++) {
  869                 win_cpu_cr_write(i, 0);
  870                 win_cpu_br_write(i, 0);
  871                 if (win_cpu_can_remap(i)) {
  872                         win_cpu_remap_l_write(i, 0);
  873                         win_cpu_remap_h_write(i, 0);
  874                 }
  875         }
  876 
  877         for (i = 0; i < cpu_wins_no; i++)
  878                 if (cpu_wins[i].target > 0)
  879                         decode_win_cpu_set(cpu_wins[i].target,
  880                             cpu_wins[i].attr, cpu_wins[i].base,
  881                             cpu_wins[i].size, cpu_wins[i].remap);
  882 
  883 }
  884 #endif
  885 
  886 #ifdef SOC_MV_ARMADAXP
  887 static int
  888 decode_win_sdram_fixup(void)
  889 {
  890         struct mem_region mr[FDT_MEM_REGIONS];
  891         uint8_t window_valid[MV_WIN_DDR_MAX];
  892         int mr_cnt, memsize, err, i, j;
  893         uint32_t valid_win_num = 0;
  894 
  895         /* Grab physical memory regions information from device tree. */
  896         err = fdt_get_mem_regions(mr, &mr_cnt, &memsize);
  897         if (err != 0)
  898                 return (err);
  899 
  900         for (i = 0; i < MV_WIN_DDR_MAX; i++)
  901                 window_valid[i] = 0;
  902 
  903         /* Try to match entries from device tree with settings from u-boot */
  904         for (i = 0; i < mr_cnt; i++) {
  905                 for (j = 0; j < MV_WIN_DDR_MAX; j++) {
  906                         if (ddr_is_active(j) &&
  907                             (ddr_base(j) == mr[i].mr_start) &&
  908                             (ddr_size(j) == mr[i].mr_size)) {
  909                                 window_valid[j] = 1;
  910                                 valid_win_num++;
  911                         }
  912                 }
  913         }
  914 
  915         if (mr_cnt != valid_win_num)
  916                 return (EINVAL);
  917 
  918         /* Destroy windows without corresponding device tree entry */
  919         for (j = 0; j < MV_WIN_DDR_MAX; j++) {
  920                 if (ddr_is_active(j) && (window_valid[j] != 1)) {
  921                         printf("Disabling SDRAM decoding window: %d\n", j);
  922                         ddr_disable(j);
  923                 }
  924         }
  925 
  926         return (0);
  927 }
  928 #endif
  929 /*
  930  * Check if we're able to cover all active DDR banks.
  931  */
  932 static int
  933 decode_win_can_cover_ddr(int max)
  934 {
  935         int i, c;
  936 
  937         c = 0;
  938         for (i = 0; i < MV_WIN_DDR_MAX; i++)
  939                 if (ddr_is_active(i))
  940                         c++;
  941 
  942         if (c > max) {
  943                 printf("Unable to cover all active DDR banks: "
  944                     "%d, available windows: %d\n", c, max);
  945                 return (0);
  946         }
  947 
  948         return (1);
  949 }
  950 
  951 /**************************************************************************
  952  * DDR windows routines
  953  **************************************************************************/
  954 int
  955 ddr_is_active(int i)
  956 {
  957 
  958         if (ddr_sz_read(i) & 0x1)
  959                 return (1);
  960 
  961         return (0);
  962 }
  963 
  964 void
  965 ddr_disable(int i)
  966 {
  967 
  968         ddr_sz_write(i, 0);
  969         ddr_br_write(i, 0);
  970 }
  971 
  972 uint32_t
  973 ddr_base(int i)
  974 {
  975 
  976         return (ddr_br_read(i) & 0xff000000);
  977 }
  978 
  979 uint32_t
  980 ddr_size(int i)
  981 {
  982 
  983         return ((ddr_sz_read(i) | 0x00ffffff) + 1);
  984 }
  985 
  986 uint32_t
  987 ddr_attr(int i)
  988 {
  989         uint32_t dev, rev;
  990 
  991         soc_id(&dev, &rev);
  992         if (dev == MV_DEV_88RC8180)
  993                 return ((ddr_sz_read(i) & 0xf0) >> 4);
  994         if (dev == MV_DEV_88F6781)
  995                 return (0);
  996 
  997         return (i == 0 ? 0xe :
  998             (i == 1 ? 0xd :
  999             (i == 2 ? 0xb :
 1000             (i == 3 ? 0x7 : 0xff))));
 1001 }
 1002 
 1003 uint32_t
 1004 ddr_target(int i)
 1005 {
 1006         uint32_t dev, rev;
 1007 
 1008         soc_id(&dev, &rev);
 1009         if (dev == MV_DEV_88RC8180) {
 1010                 i = (ddr_sz_read(i) & 0xf0) >> 4;
 1011                 return (i == 0xe ? 0xc :
 1012                     (i == 0xd ? 0xd :
 1013                     (i == 0xb ? 0xe :
 1014                     (i == 0x7 ? 0xf : 0xc))));
 1015         }
 1016 
 1017         /*
 1018          * On SOCs other than 88RC8180 Mbus unit ID for
 1019          * DDR SDRAM controller is always 0x0.
 1020          */
 1021         return (0);
 1022 }
 1023 
 1024 /**************************************************************************
 1025  * USB windows routines
 1026  **************************************************************************/
 1027 static int
 1028 decode_win_usb_valid(void)
 1029 {
 1030 
 1031         return (decode_win_can_cover_ddr(MV_WIN_USB_MAX));
 1032 }
 1033 
 1034 static void
 1035 decode_win_usb_dump(u_long base)
 1036 {
 1037         int i;
 1038 
 1039         if (pm_is_disabled(CPU_PM_CTRL_USB(usb_port - 1)))
 1040                 return;
 1041 
 1042         for (i = 0; i < MV_WIN_USB_MAX; i++)
 1043                 printf("USB window#%d: c 0x%08x, b 0x%08x\n", i,
 1044                     win_usb_cr_read(base, i), win_usb_br_read(base, i));
 1045 }
 1046 
 1047 /*
 1048  * Set USB decode windows.
 1049  */
 1050 static void
 1051 decode_win_usb_setup(u_long base)
 1052 {
 1053         uint32_t br, cr;
 1054         int i, j;
 1055 
 1056 
 1057         if (pm_is_disabled(CPU_PM_CTRL_USB(usb_port)))
 1058                 return;
 1059 
 1060         usb_port++;
 1061 
 1062         for (i = 0; i < MV_WIN_USB_MAX; i++) {
 1063                 win_usb_cr_write(base, i, 0);
 1064                 win_usb_br_write(base, i, 0);
 1065         }
 1066 
 1067         /* Only access to active DRAM banks is required */
 1068         for (i = 0; i < MV_WIN_DDR_MAX; i++) {
 1069                 if (ddr_is_active(i)) {
 1070                         br = ddr_base(i);
 1071                         /*
 1072                          * XXX for 6281 we should handle Mbus write
 1073                          * burst limit field in the ctrl reg
 1074                          */
 1075                         cr = (((ddr_size(i) - 1) & 0xffff0000) |
 1076                             (ddr_attr(i) << 8) |
 1077                             (ddr_target(i) << 4) | 1);
 1078 
 1079                         /* Set the first free USB window */
 1080                         for (j = 0; j < MV_WIN_USB_MAX; j++) {
 1081                                 if (win_usb_cr_read(base, j) & 0x1)
 1082                                         continue;
 1083 
 1084                                 win_usb_br_write(base, j, br);
 1085                                 win_usb_cr_write(base, j, cr);
 1086                                 break;
 1087                         }
 1088                 }
 1089         }
 1090 }
 1091 
 1092 /**************************************************************************
 1093  * ETH windows routines
 1094  **************************************************************************/
 1095 
 1096 static int
 1097 win_eth_can_remap(int i)
 1098 {
 1099 
 1100         /* ETH encode windows 0-3 have remap capability */
 1101         if (i < 4)
 1102                 return (1);
 1103 
 1104         return (0);
 1105 }
 1106 
 1107 static int
 1108 eth_bare_read(uint32_t base, int i)
 1109 {
 1110         uint32_t v;
 1111 
 1112         v = win_eth_bare_read(base);
 1113         v &= (1 << i);
 1114 
 1115         return (v >> i);
 1116 }
 1117 
 1118 static void
 1119 eth_bare_write(uint32_t base, int i, int val)
 1120 {
 1121         uint32_t v;
 1122 
 1123         v = win_eth_bare_read(base);
 1124         v &= ~(1 << i);
 1125         v |= (val << i);
 1126         win_eth_bare_write(base, v);
 1127 }
 1128 
 1129 static void
 1130 eth_epap_write(uint32_t base, int i, int val)
 1131 {
 1132         uint32_t v;
 1133 
 1134         v = win_eth_epap_read(base);
 1135         v &= ~(0x3 << (i * 2));
 1136         v |= (val << (i * 2));
 1137         win_eth_epap_write(base, v);
 1138 }
 1139 
 1140 static void
 1141 decode_win_eth_dump(u_long base)
 1142 {
 1143         int i;
 1144 
 1145         if (pm_is_disabled(CPU_PM_CTRL_GE(eth_port - 1)))
 1146                 return;
 1147 
 1148         for (i = 0; i < MV_WIN_ETH_MAX; i++) {
 1149                 printf("ETH window#%d: b 0x%08x, s 0x%08x", i,
 1150                     win_eth_br_read(base, i),
 1151                     win_eth_sz_read(base, i));
 1152 
 1153                 if (win_eth_can_remap(i))
 1154                         printf(", ha 0x%08x",
 1155                             win_eth_har_read(base, i));
 1156 
 1157                 printf("\n");
 1158         }
 1159         printf("ETH windows: bare 0x%08x, epap 0x%08x\n",
 1160             win_eth_bare_read(base),
 1161             win_eth_epap_read(base));
 1162 }
 1163 
 1164 #if defined(SOC_MV_LOKIPLUS)
 1165 #define MV_WIN_ETH_DDR_TRGT(n)  0
 1166 #else
 1167 #define MV_WIN_ETH_DDR_TRGT(n)  ddr_target(n)
 1168 #endif
 1169 
 1170 static void
 1171 decode_win_eth_setup(u_long base)
 1172 {
 1173         uint32_t br, sz;
 1174         int i, j;
 1175 
 1176         if (pm_is_disabled(CPU_PM_CTRL_GE(eth_port)))
 1177                 return;
 1178 
 1179         eth_port++;
 1180 
 1181         /* Disable, clear and revoke protection for all ETH windows */
 1182         for (i = 0; i < MV_WIN_ETH_MAX; i++) {
 1183 
 1184                 eth_bare_write(base, i, 1);
 1185                 eth_epap_write(base, i, 0);
 1186                 win_eth_br_write(base, i, 0);
 1187                 win_eth_sz_write(base, i, 0);
 1188                 if (win_eth_can_remap(i))
 1189                         win_eth_har_write(base, i, 0);
 1190         }
 1191 
 1192         /* Only access to active DRAM banks is required */
 1193         for (i = 0; i < MV_WIN_DDR_MAX; i++)
 1194                 if (ddr_is_active(i)) {
 1195 
 1196                         br = ddr_base(i) | (ddr_attr(i) << 8) | MV_WIN_ETH_DDR_TRGT(i);
 1197                         sz = ((ddr_size(i) - 1) & 0xffff0000);
 1198 
 1199                         /* Set the first free ETH window */
 1200                         for (j = 0; j < MV_WIN_ETH_MAX; j++) {
 1201                                 if (eth_bare_read(base, j) == 0)
 1202                                         continue;
 1203 
 1204                                 win_eth_br_write(base, j, br);
 1205                                 win_eth_sz_write(base, j, sz);
 1206 
 1207                                 /* XXX remapping ETH windows not supported */
 1208 
 1209                                 /* Set protection RW */
 1210                                 eth_epap_write(base, j, 0x3);
 1211 
 1212                                 /* Enable window */
 1213                                 eth_bare_write(base, j, 0);
 1214                                 break;
 1215                         }
 1216                 }
 1217 }
 1218 
 1219 static int
 1220 decode_win_eth_valid(void)
 1221 {
 1222 
 1223         return (decode_win_can_cover_ddr(MV_WIN_ETH_MAX));
 1224 }
 1225 
 1226 /**************************************************************************
 1227  * PCIE windows routines
 1228  **************************************************************************/
 1229 
 1230 void
 1231 decode_win_pcie_setup(u_long base)
 1232 {
 1233         uint32_t size = 0, ddrbase = ~0;
 1234         uint32_t cr, br;
 1235         int i, j;
 1236 
 1237         for (i = 0; i < MV_PCIE_BAR_MAX; i++) {
 1238                 pcie_bar_br_write(base, i,
 1239                     MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN);
 1240                 if (i < 3)
 1241                         pcie_bar_brh_write(base, i, 0);
 1242                 if (i > 0)
 1243                         pcie_bar_cr_write(base, i, 0);
 1244         }
 1245 
 1246         for (i = 0; i < MV_WIN_PCIE_MAX; i++) {
 1247                 win_pcie_cr_write(base, i, 0);
 1248                 win_pcie_br_write(base, i, 0);
 1249                 win_pcie_remap_write(base, i, 0);
 1250         }
 1251 
 1252         /* On End-Point only set BAR size to 1MB regardless of DDR size */
 1253         if ((bus_space_read_4(fdtbus_bs_tag, base, MV_PCIE_CONTROL)
 1254             & MV_PCIE_ROOT_CMPLX) == 0) {
 1255                 pcie_bar_cr_write(base, 1, 0xf0000 | 1);
 1256                 return;
 1257         }
 1258 
 1259         for (i = 0; i < MV_WIN_DDR_MAX; i++) {
 1260                 if (ddr_is_active(i)) {
 1261                         /* Map DDR to BAR 1 */
 1262                         cr = (ddr_size(i) - 1) & 0xffff0000;
 1263                         size += ddr_size(i) & 0xffff0000;
 1264                         cr |= (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1;
 1265                         br = ddr_base(i);
 1266                         if (br < ddrbase)
 1267                                 ddrbase = br;
 1268 
 1269                         /* Use the first available PCIE window */
 1270                         for (j = 0; j < MV_WIN_PCIE_MAX; j++) {
 1271                                 if (win_pcie_cr_read(base, j) != 0)
 1272                                         continue;
 1273 
 1274                                 win_pcie_br_write(base, j, br);
 1275                                 win_pcie_cr_write(base, j, cr);
 1276                                 break;
 1277                         }
 1278                 }
 1279         }
 1280 
 1281         /*
 1282          * Upper 16 bits in BAR register is interpreted as BAR size
 1283          * (in 64 kB units) plus 64kB, so substract 0x10000
 1284          * form value passed to register to get correct value.
 1285          */
 1286         size -= 0x10000;
 1287         pcie_bar_cr_write(base, 1, size | 1);
 1288         pcie_bar_br_write(base, 1, ddrbase |
 1289             MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN);
 1290         pcie_bar_br_write(base, 0, fdt_immr_pa |
 1291             MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN);
 1292 }
 1293 
 1294 static int
 1295 decode_win_pcie_valid(void)
 1296 {
 1297 
 1298         return (decode_win_can_cover_ddr(MV_WIN_PCIE_MAX));
 1299 }
 1300 
 1301 /**************************************************************************
 1302  * IDMA windows routines
 1303  **************************************************************************/
 1304 #if defined(SOC_MV_ORION) || defined(SOC_MV_DISCOVERY)
 1305 static int
 1306 idma_bare_read(u_long base, int i)
 1307 {
 1308         uint32_t v;
 1309 
 1310         v = win_idma_bare_read(base);
 1311         v &= (1 << i);
 1312 
 1313         return (v >> i);
 1314 }
 1315 
 1316 static void
 1317 idma_bare_write(u_long base, int i, int val)
 1318 {
 1319         uint32_t v;
 1320 
 1321         v = win_idma_bare_read(base);
 1322         v &= ~(1 << i);
 1323         v |= (val << i);
 1324         win_idma_bare_write(base, v);
 1325 }
 1326 
 1327 /*
 1328  * Sets channel protection 'val' for window 'w' on channel 'c'
 1329  */
 1330 static void
 1331 idma_cap_write(u_long base, int c, int w, int val)
 1332 {
 1333         uint32_t v;
 1334 
 1335         v = win_idma_cap_read(base, c);
 1336         v &= ~(0x3 << (w * 2));
 1337         v |= (val << (w * 2));
 1338         win_idma_cap_write(base, c, v);
 1339 }
 1340 
 1341 /*
 1342  * Set protection 'val' on all channels for window 'w'
 1343  */
 1344 static void
 1345 idma_set_prot(u_long base, int w, int val)
 1346 {
 1347         int c;
 1348 
 1349         for (c = 0; c < MV_IDMA_CHAN_MAX; c++)
 1350                 idma_cap_write(base, c, w, val);
 1351 }
 1352 
 1353 static int
 1354 win_idma_can_remap(int i)
 1355 {
 1356 
 1357         /* IDMA decode windows 0-3 have remap capability */
 1358         if (i < 4)
 1359                 return (1);
 1360 
 1361         return (0);
 1362 }
 1363 
 1364 void
 1365 decode_win_idma_setup(u_long base)
 1366 {
 1367         uint32_t br, sz;
 1368         int i, j;
 1369 
 1370         if (pm_is_disabled(CPU_PM_CTRL_IDMA))
 1371                 return;
 1372         /*
 1373          * Disable and clear all IDMA windows, revoke protection for all channels
 1374          */
 1375         for (i = 0; i < MV_WIN_IDMA_MAX; i++) {
 1376 
 1377                 idma_bare_write(base, i, 1);
 1378                 win_idma_br_write(base, i, 0);
 1379                 win_idma_sz_write(base, i, 0);
 1380                 if (win_idma_can_remap(i) == 1)
 1381                         win_idma_har_write(base, i, 0);
 1382         }
 1383         for (i = 0; i < MV_IDMA_CHAN_MAX; i++)
 1384                 win_idma_cap_write(base, i, 0);
 1385 
 1386         /*
 1387          * Set up access to all active DRAM banks
 1388          */
 1389         for (i = 0; i < MV_WIN_DDR_MAX; i++)
 1390                 if (ddr_is_active(i)) {
 1391                         br = ddr_base(i) | (ddr_attr(i) << 8) | ddr_target(i);
 1392                         sz = ((ddr_size(i) - 1) & 0xffff0000);
 1393 
 1394                         /* Place DDR entries in non-remapped windows */
 1395                         for (j = 0; j < MV_WIN_IDMA_MAX; j++)
 1396                                 if (win_idma_can_remap(j) != 1 &&
 1397                                     idma_bare_read(base, j) == 1) {
 1398 
 1399                                         /* Configure window */
 1400                                         win_idma_br_write(base, j, br);
 1401                                         win_idma_sz_write(base, j, sz);
 1402 
 1403                                         /* Set protection RW on all channels */
 1404                                         idma_set_prot(base, j, 0x3);
 1405 
 1406                                         /* Enable window */
 1407                                         idma_bare_write(base, j, 0);
 1408                                         break;
 1409                                 }
 1410                 }
 1411 
 1412         /*
 1413          * Remaining targets -- from statically defined table
 1414          */
 1415         for (i = 0; i < idma_wins_no; i++)
 1416                 if (idma_wins[i].target > 0) {
 1417                         br = (idma_wins[i].base & 0xffff0000) |
 1418                             (idma_wins[i].attr << 8) | idma_wins[i].target;
 1419                         sz = ((idma_wins[i].size - 1) & 0xffff0000);
 1420 
 1421                         /* Set the first free IDMA window */
 1422                         for (j = 0; j < MV_WIN_IDMA_MAX; j++) {
 1423                                 if (idma_bare_read(base, j) == 0)
 1424                                         continue;
 1425 
 1426                                 /* Configure window */
 1427                                 win_idma_br_write(base, j, br);
 1428                                 win_idma_sz_write(base, j, sz);
 1429                                 if (win_idma_can_remap(j) &&
 1430                                     idma_wins[j].remap >= 0)
 1431                                         win_idma_har_write(base, j,
 1432                                             idma_wins[j].remap);
 1433 
 1434                                 /* Set protection RW on all channels */
 1435                                 idma_set_prot(base, j, 0x3);
 1436 
 1437                                 /* Enable window */
 1438                                 idma_bare_write(base, j, 0);
 1439                                 break;
 1440                         }
 1441                 }
 1442 }
 1443 
 1444 int
 1445 decode_win_idma_valid(void)
 1446 {
 1447         const struct decode_win *wintab;
 1448         int c, i, j, rv;
 1449         uint32_t b, e, s;
 1450 
 1451         if (idma_wins_no > MV_WIN_IDMA_MAX) {
 1452                 printf("IDMA windows: too many entries: %d\n", idma_wins_no);
 1453                 return (0);
 1454         }
 1455         for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++)
 1456                 if (ddr_is_active(i))
 1457                         c++;
 1458 
 1459         if (idma_wins_no > (MV_WIN_IDMA_MAX - c)) {
 1460                 printf("IDMA windows: too many entries: %d, available: %d\n",
 1461                     idma_wins_no, MV_WIN_IDMA_MAX - c);
 1462                 return (0);
 1463         }
 1464 
 1465         wintab = idma_wins;
 1466         rv = 1;
 1467         for (i = 0; i < idma_wins_no; i++, wintab++) {
 1468 
 1469                 if (wintab->target == 0) {
 1470                         printf("IDMA window#%d: DDR target window is not "
 1471                             "supposed to be reprogrammed!\n", i);
 1472                         rv = 0;
 1473                 }
 1474 
 1475                 if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) {
 1476                         printf("IDMA window#%d: not capable of remapping, but "
 1477                             "val 0x%08x defined\n", i, wintab->remap);
 1478                         rv = 0;
 1479                 }
 1480 
 1481                 s = wintab->size;
 1482                 b = wintab->base;
 1483                 e = b + s - 1;
 1484                 if (s > (0xFFFFFFFF - b + 1)) {
 1485                         /* XXX this boundary check should account for 64bit and
 1486                          * remapping.. */
 1487                         printf("IDMA window#%d: no space for size 0x%08x at "
 1488                             "0x%08x\n", i, s, b);
 1489                         rv = 0;
 1490                         continue;
 1491                 }
 1492 
 1493                 j = decode_win_overlap(i, idma_wins_no, &idma_wins[0]);
 1494                 if (j >= 0) {
 1495                         printf("IDMA window#%d: (0x%08x - 0x%08x) overlaps "
 1496                             "with #%d (0x%08x - 0x%08x)\n", i, b, e, j,
 1497                             idma_wins[j].base,
 1498                             idma_wins[j].base + idma_wins[j].size - 1);
 1499                         rv = 0;
 1500                 }
 1501         }
 1502 
 1503         return (rv);
 1504 }
 1505 
 1506 void
 1507 decode_win_idma_dump(u_long base)
 1508 {
 1509         int i;
 1510 
 1511         if (pm_is_disabled(CPU_PM_CTRL_IDMA))
 1512                 return;
 1513 
 1514         for (i = 0; i < MV_WIN_IDMA_MAX; i++) {
 1515                 printf("IDMA window#%d: b 0x%08x, s 0x%08x", i,
 1516                     win_idma_br_read(base, i), win_idma_sz_read(base, i));
 1517                 
 1518                 if (win_idma_can_remap(i))
 1519                         printf(", ha 0x%08x", win_idma_har_read(base, i));
 1520 
 1521                 printf("\n");
 1522         }
 1523         for (i = 0; i < MV_IDMA_CHAN_MAX; i++)
 1524                 printf("IDMA channel#%d: ap 0x%08x\n", i,
 1525                     win_idma_cap_read(base, i));
 1526         printf("IDMA windows: bare 0x%08x\n", win_idma_bare_read(base));
 1527 }
 1528 #else
 1529 
 1530 /* Provide dummy functions to satisfy the build for SoCs not equipped with IDMA */
 1531 int
 1532 decode_win_idma_valid(void)
 1533 {
 1534 
 1535         return (1);
 1536 }
 1537 
 1538 void
 1539 decode_win_idma_setup(u_long base)
 1540 {
 1541 }
 1542 
 1543 void
 1544 decode_win_idma_dump(u_long base)
 1545 {
 1546 }
 1547 #endif
 1548 
 1549 /**************************************************************************
 1550  * XOR windows routines
 1551  **************************************************************************/
 1552 #if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY)
 1553 static int
 1554 xor_ctrl_read(u_long base, int i, int c, int e)
 1555 {
 1556         uint32_t v;
 1557         v = win_xor_ctrl_read(base, c, e);
 1558         v &= (1 << i);
 1559 
 1560         return (v >> i);
 1561 }
 1562 
 1563 static void
 1564 xor_ctrl_write(u_long base, int i, int c, int e, int val)
 1565 {
 1566         uint32_t v;
 1567 
 1568         v = win_xor_ctrl_read(base, c, e);
 1569         v &= ~(1 << i);
 1570         v |= (val << i);
 1571         win_xor_ctrl_write(base, c, e, v);
 1572 }
 1573 
 1574 /*
 1575  * Set channel protection 'val' for window 'w' on channel 'c'
 1576  */
 1577 static void
 1578 xor_chan_write(u_long base, int c, int e, int w, int val)
 1579 {
 1580         uint32_t v;
 1581 
 1582         v = win_xor_ctrl_read(base, c, e);
 1583         v &= ~(0x3 << (w * 2 + 16));
 1584         v |= (val << (w * 2 + 16));
 1585         win_xor_ctrl_write(base, c, e, v);
 1586 }
 1587 
 1588 /*
 1589  * Set protection 'val' on all channels for window 'w' on engine 'e'
 1590  */
 1591 static void
 1592 xor_set_prot(u_long base, int w, int e, int val)
 1593 {
 1594         int c;
 1595 
 1596         for (c = 0; c < MV_XOR_CHAN_MAX; c++)
 1597                 xor_chan_write(base, c, e, w, val);
 1598 }
 1599 
 1600 static int
 1601 win_xor_can_remap(int i)
 1602 {
 1603 
 1604         /* XOR decode windows 0-3 have remap capability */
 1605         if (i < 4)
 1606                 return (1);
 1607 
 1608         return (0);
 1609 }
 1610 
 1611 static int
 1612 xor_max_eng(void)
 1613 {
 1614         uint32_t dev, rev;
 1615 
 1616         soc_id(&dev, &rev);
 1617         switch (dev) {
 1618         case MV_DEV_88F6281:
 1619         case MV_DEV_88F6282:
 1620         case MV_DEV_MV78130:
 1621         case MV_DEV_MV78160:
 1622         case MV_DEV_MV78230:
 1623         case MV_DEV_MV78260:
 1624         case MV_DEV_MV78460:
 1625                 return (2);
 1626         case MV_DEV_MV78100:
 1627         case MV_DEV_MV78100_Z0:
 1628                 return (1);
 1629         default:
 1630                 return (0);
 1631         }
 1632 }
 1633 
 1634 static void
 1635 xor_active_dram(u_long base, int c, int e, int *window)
 1636 {
 1637         uint32_t br, sz;
 1638         int i, m, w;
 1639 
 1640         /*
 1641          * Set up access to all active DRAM banks
 1642          */
 1643         m = xor_max_eng();
 1644         for (i = 0; i < m; i++)
 1645                 if (ddr_is_active(i)) {
 1646                         br = ddr_base(i) | (ddr_attr(i) << 8) |
 1647                             ddr_target(i);
 1648                         sz = ((ddr_size(i) - 1) & 0xffff0000);
 1649 
 1650                         /* Place DDR entries in non-remapped windows */
 1651                         for (w = 0; w < MV_WIN_XOR_MAX; w++)
 1652                                 if (win_xor_can_remap(w) != 1 &&
 1653                                     (xor_ctrl_read(base, w, c, e) == 0) &&
 1654                                     w > *window) {
 1655                                         /* Configure window */
 1656                                         win_xor_br_write(base, w, e, br);
 1657                                         win_xor_sz_write(base, w, e, sz);
 1658 
 1659                                         /* Set protection RW on all channels */
 1660                                         xor_set_prot(base, w, e, 0x3);
 1661 
 1662                                         /* Enable window */
 1663                                         xor_ctrl_write(base, w, c, e, 1);
 1664                                         (*window)++;
 1665                                         break;
 1666                                 }
 1667                 }
 1668 }
 1669 
 1670 void
 1671 decode_win_xor_setup(u_long base)
 1672 {
 1673         uint32_t br, sz;
 1674         int i, j, z, e = 1, m, window;
 1675 
 1676         if (pm_is_disabled(CPU_PM_CTRL_XOR))
 1677                 return;
 1678 
 1679         /*
 1680          * Disable and clear all XOR windows, revoke protection for all
 1681          * channels
 1682          */
 1683         m = xor_max_eng();
 1684         for (j = 0; j < m; j++, e--) {
 1685 
 1686                 /* Number of non-remaped windows */
 1687                 window = MV_XOR_NON_REMAP - 1;
 1688 
 1689                 for (i = 0; i < MV_WIN_XOR_MAX; i++) {
 1690                         win_xor_br_write(base, i, e, 0);
 1691                         win_xor_sz_write(base, i, e, 0);
 1692                 }
 1693 
 1694                 if (win_xor_can_remap(i) == 1)
 1695                         win_xor_har_write(base, i, e, 0);
 1696 
 1697                 for (i = 0; i < MV_XOR_CHAN_MAX; i++) {
 1698                         win_xor_ctrl_write(base, i, e, 0);
 1699                         xor_active_dram(base, i, e, &window);
 1700                 }
 1701 
 1702                 /*
 1703                  * Remaining targets -- from a statically defined table
 1704                  */
 1705                 for (i = 0; i < xor_wins_no; i++)
 1706                         if (xor_wins[i].target > 0) {
 1707                                 br = (xor_wins[i].base & 0xffff0000) |
 1708                                     (xor_wins[i].attr << 8) |
 1709                                     xor_wins[i].target;
 1710                                 sz = ((xor_wins[i].size - 1) & 0xffff0000);
 1711 
 1712                                 /* Set the first free XOR window */
 1713                                 for (z = 0; z < MV_WIN_XOR_MAX; z++) {
 1714                                         if (xor_ctrl_read(base, z, 0, e) &&
 1715                                             xor_ctrl_read(base, z, 1, e))
 1716                                                 continue;
 1717 
 1718                                         /* Configure window */
 1719                                         win_xor_br_write(base, z, e, br);
 1720                                         win_xor_sz_write(base, z, e, sz);
 1721                                         if (win_xor_can_remap(z) &&
 1722                                             xor_wins[z].remap >= 0)
 1723                                                 win_xor_har_write(base, z, e,
 1724                                                     xor_wins[z].remap);
 1725 
 1726                                         /* Set protection RW on all channels */
 1727                                         xor_set_prot(base, z, e, 0x3);
 1728 
 1729                                         /* Enable window */
 1730                                         xor_ctrl_write(base, z, 0, e, 1);
 1731                                         xor_ctrl_write(base, z, 1, e, 1);
 1732                                         break;
 1733                                 }
 1734                         }
 1735         }
 1736 }
 1737 
 1738 int
 1739 decode_win_xor_valid(void)
 1740 {
 1741         const struct decode_win *wintab;
 1742         int c, i, j, rv;
 1743         uint32_t b, e, s;
 1744 
 1745         if (xor_wins_no > MV_WIN_XOR_MAX) {
 1746                 printf("XOR windows: too many entries: %d\n", xor_wins_no);
 1747                 return (0);
 1748         }
 1749         for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++)
 1750                 if (ddr_is_active(i))
 1751                         c++;
 1752 
 1753         if (xor_wins_no > (MV_WIN_XOR_MAX - c)) {
 1754                 printf("XOR windows: too many entries: %d, available: %d\n",
 1755                     xor_wins_no, MV_WIN_IDMA_MAX - c);
 1756                 return (0);
 1757         }
 1758 
 1759         wintab = xor_wins;
 1760         rv = 1;
 1761         for (i = 0; i < xor_wins_no; i++, wintab++) {
 1762 
 1763                 if (wintab->target == 0) {
 1764                         printf("XOR window#%d: DDR target window is not "
 1765                             "supposed to be reprogrammed!\n", i);
 1766                         rv = 0;
 1767                 }
 1768 
 1769                 if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) {
 1770                         printf("XOR window#%d: not capable of remapping, but "
 1771                             "val 0x%08x defined\n", i, wintab->remap);
 1772                         rv = 0;
 1773                 }
 1774 
 1775                 s = wintab->size;
 1776                 b = wintab->base;
 1777                 e = b + s - 1;
 1778                 if (s > (0xFFFFFFFF - b + 1)) {
 1779                         /*
 1780                          * XXX this boundary check should account for 64bit
 1781                          * and remapping..
 1782                          */
 1783                         printf("XOR window#%d: no space for size 0x%08x at "
 1784                             "0x%08x\n", i, s, b);
 1785                         rv = 0;
 1786                         continue;
 1787                 }
 1788 
 1789                 j = decode_win_overlap(i, xor_wins_no, &xor_wins[0]);
 1790                 if (j >= 0) {
 1791                         printf("XOR window#%d: (0x%08x - 0x%08x) overlaps "
 1792                             "with #%d (0x%08x - 0x%08x)\n", i, b, e, j,
 1793                             xor_wins[j].base,
 1794                             xor_wins[j].base + xor_wins[j].size - 1);
 1795                         rv = 0;
 1796                 }
 1797         }
 1798 
 1799         return (rv);
 1800 }
 1801 
 1802 void
 1803 decode_win_xor_dump(u_long base)
 1804 {
 1805         int i, j;
 1806         int e = 1;
 1807 
 1808         if (pm_is_disabled(CPU_PM_CTRL_XOR))
 1809                 return;
 1810 
 1811         for (j = 0; j < xor_max_eng(); j++, e--) {
 1812                 for (i = 0; i < MV_WIN_XOR_MAX; i++) {
 1813                         printf("XOR window#%d: b 0x%08x, s 0x%08x", i,
 1814                             win_xor_br_read(base, i, e), win_xor_sz_read(base, i, e));
 1815 
 1816                         if (win_xor_can_remap(i))
 1817                                 printf(", ha 0x%08x", win_xor_har_read(base, i, e));
 1818 
 1819                         printf("\n");
 1820                 }
 1821                 for (i = 0; i < MV_XOR_CHAN_MAX; i++)
 1822                         printf("XOR control#%d: 0x%08x\n", i,
 1823                             win_xor_ctrl_read(base, i, e));
 1824         }
 1825 }
 1826 
 1827 #else
 1828 /* Provide dummy functions to satisfy the build for SoCs not equipped with XOR */
 1829 static int
 1830 decode_win_xor_valid(void)
 1831 {
 1832 
 1833         return (1);
 1834 }
 1835 
 1836 static void
 1837 decode_win_xor_setup(u_long base)
 1838 {
 1839 }
 1840 
 1841 static void
 1842 decode_win_xor_dump(u_long base)
 1843 {
 1844 }
 1845 #endif
 1846 
 1847 /**************************************************************************
 1848  * SATA windows routines
 1849  **************************************************************************/
 1850 static void
 1851 decode_win_sata_setup(u_long base)
 1852 {
 1853         uint32_t cr, br;
 1854         int i, j;
 1855 
 1856         if (pm_is_disabled(CPU_PM_CTRL_SATA))
 1857                 return;
 1858 
 1859         for (i = 0; i < MV_WIN_SATA_MAX; i++) {
 1860                 win_sata_cr_write(base, i, 0);
 1861                 win_sata_br_write(base, i, 0);
 1862         }
 1863 
 1864         for (i = 0; i < MV_WIN_DDR_MAX; i++)
 1865                 if (ddr_is_active(i)) {
 1866                         cr = ((ddr_size(i) - 1) & 0xffff0000) |
 1867                             (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1;
 1868                         br = ddr_base(i);
 1869 
 1870                         /* Use the first available SATA window */
 1871                         for (j = 0; j < MV_WIN_SATA_MAX; j++) {
 1872                                 if ((win_sata_cr_read(base, j) & 1) != 0)
 1873                                         continue;
 1874 
 1875                                 win_sata_br_write(base, j, br);
 1876                                 win_sata_cr_write(base, j, cr);
 1877                                 break;
 1878                         }
 1879                 }
 1880 }
 1881 
 1882 static int
 1883 decode_win_sata_valid(void)
 1884 {
 1885         uint32_t dev, rev;
 1886 
 1887         soc_id(&dev, &rev);
 1888         if (dev == MV_DEV_88F5281)
 1889                 return (1);
 1890 
 1891         return (decode_win_can_cover_ddr(MV_WIN_SATA_MAX));
 1892 }
 1893 
 1894 /**************************************************************************
 1895  * FDT parsing routines.
 1896  **************************************************************************/
 1897 
 1898 static int
 1899 fdt_get_ranges(const char *nodename, void *buf, int size, int *tuples,
 1900     int *tuplesize)
 1901 {
 1902         phandle_t node;
 1903         pcell_t addr_cells, par_addr_cells, size_cells;
 1904         int len, tuple_size, tuples_count;
 1905 
 1906         node = OF_finddevice(nodename);
 1907         if (node == -1)
 1908                 return (EINVAL);
 1909 
 1910         if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0)
 1911                 return (ENXIO);
 1912 
 1913         par_addr_cells = fdt_parent_addr_cells(node);
 1914         if (par_addr_cells > 2)
 1915                 return (ERANGE);
 1916 
 1917         tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells +
 1918             size_cells);
 1919 
 1920         /* Note the OF_getprop_alloc() cannot be used at this early stage. */
 1921         len = OF_getprop(node, "ranges", buf, size);
 1922 
 1923         /*
 1924          * XXX this does not handle the empty 'ranges;' case, which is
 1925          * legitimate and should be allowed.
 1926          */
 1927         tuples_count = len / tuple_size;
 1928         if (tuples_count <= 0)
 1929                 return (ERANGE);
 1930 
 1931         if (fdt_ranges_verify(buf, tuples_count, par_addr_cells,
 1932             addr_cells, size_cells) != 0)
 1933                 return (ERANGE);
 1934 
 1935         *tuples = tuples_count;
 1936         *tuplesize = tuple_size;
 1937         return (0);
 1938 }
 1939 
 1940 static int
 1941 win_cpu_from_dt(void)
 1942 {
 1943         pcell_t ranges[48];
 1944         phandle_t node;
 1945         int i, entry_size, err, t, tuple_size, tuples;
 1946         u_long sram_base, sram_size;
 1947 
 1948         t = 0;
 1949         /* Retrieve 'ranges' property of '/localbus' node. */
 1950         if ((err = fdt_get_ranges("/localbus", ranges, sizeof(ranges),
 1951             &tuples, &tuple_size)) == 0) {
 1952                 /*
 1953                  * Fill CPU decode windows table.
 1954                  */
 1955                 bzero((void *)&cpu_win_tbl, sizeof(cpu_win_tbl));
 1956 
 1957                 entry_size = tuple_size / sizeof(pcell_t);
 1958                 cpu_wins_no = tuples;
 1959 
 1960                 for (i = 0, t = 0; t < tuples; i += entry_size, t++) {
 1961                         cpu_win_tbl[t].target = 1;
 1962                         cpu_win_tbl[t].attr = fdt32_to_cpu(ranges[i + 1]);
 1963                         cpu_win_tbl[t].base = fdt32_to_cpu(ranges[i + 2]);
 1964                         cpu_win_tbl[t].size = fdt32_to_cpu(ranges[i + 3]);
 1965                         cpu_win_tbl[t].remap = ~0;
 1966                         debugf("target = 0x%0x attr = 0x%0x base = 0x%0x "
 1967                             "size = 0x%0x remap = 0x%0x\n",
 1968                             cpu_win_tbl[t].target,
 1969                             cpu_win_tbl[t].attr, cpu_win_tbl[t].base,
 1970                             cpu_win_tbl[t].size, cpu_win_tbl[t].remap);
 1971                 }
 1972         }
 1973 
 1974         /*
 1975          * Retrieve CESA SRAM data.
 1976          */
 1977         if ((node = OF_finddevice("sram")) != -1)
 1978                 if (fdt_is_compatible(node, "mrvl,cesa-sram"))
 1979                         goto moveon;
 1980 
 1981         if ((node = OF_finddevice("/")) == 0)
 1982                 return (ENXIO);
 1983 
 1984         if ((node = fdt_find_compatible(node, "mrvl,cesa-sram", 0)) == 0)
 1985                 /* SRAM block is not always present. */
 1986                 return (0);
 1987 moveon:
 1988         sram_base = sram_size = 0;
 1989         if (fdt_regsize(node, &sram_base, &sram_size) != 0)
 1990                 return (EINVAL);
 1991 
 1992         cpu_win_tbl[t].target = MV_WIN_CESA_TARGET;
 1993         cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(1);
 1994         cpu_win_tbl[t].base = sram_base;
 1995         cpu_win_tbl[t].size = sram_size;
 1996         cpu_win_tbl[t].remap = ~0;
 1997         cpu_wins_no++;
 1998         debugf("sram: base = 0x%0lx size = 0x%0lx\n", sram_base, sram_size);
 1999 
 2000         return (0);
 2001 }
 2002 
 2003 static int
 2004 fdt_win_setup(void)
 2005 {
 2006         phandle_t node, child;
 2007         struct soc_node_spec *soc_node;
 2008         u_long size, base;
 2009         int err, i;
 2010 
 2011         node = OF_finddevice("/");
 2012         if (node == -1)
 2013                 panic("fdt_win_setup: no root node");
 2014 
 2015         /*
 2016          * Traverse through all children of root and simple-bus nodes.
 2017          * For each found device retrieve decode windows data (if applicable).
 2018          */
 2019         child = OF_child(node);
 2020         while (child != 0) {
 2021                 for (i = 0; soc_nodes[i].compat != NULL; i++) {
 2022 
 2023                         soc_node = &soc_nodes[i];
 2024 
 2025                         if (!fdt_is_compatible(child, soc_node->compat))
 2026                                 continue;
 2027 
 2028                         err = fdt_regsize(child, &base, &size);
 2029                         if (err != 0)
 2030                                 return (err);
 2031 
 2032                         base = (base & 0x000fffff) | fdt_immr_va;
 2033                         if (soc_node->decode_handler != NULL)
 2034                                 soc_node->decode_handler(base);
 2035                         else
 2036                                 return (ENXIO);
 2037 
 2038                         if (MV_DUMP_WIN && (soc_node->dump_handler != NULL))
 2039                                 soc_node->dump_handler(base);
 2040                 }
 2041 
 2042                 /*
 2043                  * Once done with root-level children let's move down to
 2044                  * simple-bus and its children.
 2045                  */
 2046                 child = OF_peer(child);
 2047                 if ((child == 0) && (node == OF_finddevice("/"))) {
 2048                         node = fdt_find_compatible(node, "simple-bus", 1);
 2049                         if (node == 0)
 2050                                 return (ENXIO);
 2051                         child = OF_child(node);
 2052                 }
 2053         }
 2054 
 2055         return (0);
 2056 }
 2057 
 2058 static void
 2059 fdt_fixup_busfreq(phandle_t root)
 2060 {
 2061         phandle_t sb;
 2062         pcell_t freq;
 2063 
 2064         freq = cpu_to_fdt32(get_tclk());
 2065 
 2066         /*
 2067          * Fix bus speed in cpu node
 2068          */
 2069         if ((sb = OF_finddevice("cpu")) != 0)
 2070                 if (fdt_is_compatible_strict(sb, "ARM,88VS584"))
 2071                         OF_setprop(sb, "bus-frequency", (void *)&freq,
 2072                             sizeof(freq));
 2073 
 2074         /*
 2075          * This fixup sets the simple-bus bus-frequency property.
 2076          */
 2077         if ((sb = fdt_find_compatible(root, "simple-bus", 1)) != 0)
 2078                 OF_setprop(sb, "bus-frequency", (void *)&freq, sizeof(freq));
 2079 }
 2080 
 2081 struct fdt_fixup_entry fdt_fixup_table[] = {
 2082         { "mrvl,DB-88F6281", &fdt_fixup_busfreq },
 2083         { "mrvl,DB-78460", &fdt_fixup_busfreq },
 2084         { NULL, NULL }
 2085 };
 2086 
 2087 static int
 2088 fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig,
 2089     int *pol)
 2090 {
 2091 
 2092         if (!fdt_is_compatible(node, "mrvl,pic") &&
 2093             !fdt_is_compatible(node, "mrvl,mpic"))
 2094                 return (ENXIO);
 2095 
 2096         *interrupt = fdt32_to_cpu(intr[0]);
 2097         *trig = INTR_TRIGGER_CONFORM;
 2098         *pol = INTR_POLARITY_CONFORM;
 2099 
 2100         return (0);
 2101 }
 2102 
 2103 fdt_pic_decode_t fdt_pic_table[] = {
 2104         &fdt_pic_decode_ic,
 2105         NULL
 2106 };
 2107 
 2108 uint64_t
 2109 get_sar_value(void)
 2110 {
 2111         uint32_t sar_low, sar_high;
 2112 
 2113 #if defined(SOC_MV_ARMADAXP)
 2114         sar_high = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE,
 2115             SAMPLE_AT_RESET_HI);
 2116         sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE,
 2117             SAMPLE_AT_RESET_LO);
 2118 #else
 2119         /*
 2120          * TODO: Add getting proper values for other SoC configurations
 2121          */
 2122         sar_high = 0;
 2123         sar_low = 0;
 2124 #endif
 2125 
 2126         return (((uint64_t)sar_high << 32) | sar_low);
 2127 }

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