1 /*-
2 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
3 * All rights reserved.
4 *
5 * Developed by Semihalf.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of MARVELL nor the names of contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
34
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/bus.h>
38 #include <sys/kernel.h>
39
40 #include <vm/vm.h>
41 #include <vm/pmap.h>
42
43 #include <machine/bus.h>
44 #include <machine/pte.h>
45 #include <machine/pmap.h>
46 #include <machine/vmparam.h>
47
48 #include <arm/mv/mvreg.h>
49 #include <arm/mv/mvvar.h>
50 #include <arm/mv/mvwin.h>
51
52 /*
53 * Virtual address space layout:
54 * -----------------------------
55 * 0x0000_0000 - 0xbfff_ffff : user process
56 *
57 * 0xc040_0000 - virtual_avail : kernel reserved (text, data, page tables
58 * : structures, ARM stacks etc.)
59 * virtual_avail - 0xefff_ffff : KVA (virtual_avail is typically < 0xc0a0_0000)
60 * 0xf000_0000 - 0xf0ff_ffff : no-cache allocation area (16MB)
61 * 0xf100_0000 - 0xf10f_ffff : SoC integrated devices registers range (1MB)
62 * 0xf110_0000 - 0xf11f_ffff : PCI-Express I/O space (1MB)
63 * 0xf120_0000 - 0xf12f_ffff : unused (1MB)
64 * 0xf130_0000 - 0xf52f_ffff : PCI-Express memory space (64MB)
65 * 0xf930_0000 - 0xfffe_ffff : unused (~172MB)
66 * 0xffff_0000 - 0xffff_0fff : 'high' vectors page (4KB)
67 * 0xffff_1000 - 0xffff_1fff : ARM_TP_ADDRESS/RAS page (4KB)
68 * 0xffff_2000 - 0xffff_ffff : unused (~55KB)
69 */
70
71 /* Static device mappings. */
72 const struct pmap_devmap pmap_devmap[] = {
73 /*
74 * Map the on-board devices VA == PA so that we can access them
75 * with the MMU on or off.
76 */
77 { /* SoC integrated peripherals registers range */
78 MV_BASE,
79 MV_PHYS_BASE,
80 MV_SIZE,
81 VM_PROT_READ | VM_PROT_WRITE,
82 PTE_NOCACHE,
83 },
84 { /* PCIE I/O */
85 MV_PCIE_IO_BASE,
86 MV_PCIE_IO_PHYS_BASE,
87 MV_PCIE_IO_SIZE,
88 VM_PROT_READ | VM_PROT_WRITE,
89 PTE_NOCACHE,
90 },
91 { /* PCIE Memory */
92 MV_PCIE_MEM_BASE,
93 MV_PCIE_MEM_PHYS_BASE,
94 MV_PCIE_MEM_SIZE,
95 VM_PROT_READ | VM_PROT_WRITE,
96 PTE_NOCACHE,
97 },
98 { 0, 0, 0, 0, 0, }
99 };
100
101 const struct gpio_config mv_gpio_config[] = {
102 { -1, -1, -1 }
103 };
104
105 void
106 platform_mpp_init(void)
107 {
108
109 /*
110 * MPP Configuration for DB-78100-BP
111 *
112 * MPP[0]: GE1_TXCLK
113 * MPP[1]: GE1_TXCTL
114 * MPP[2]: GE1_RXCTL
115 * MPP[3]: GE1_RXCLK
116 * MPP[4]: GE1_TXD[0]
117 * MPP[5]: GE1_TXD[1]
118 * MPP[6]: GE1_TXD[2]
119 * MPP[7]: GE1_TXD[3]
120 * MPP[8]: GE1_RXD[0]
121 * MPP[9]: GE1_RXD[1]
122 * MPP[10]: GE1_RXD[2]
123 * MPP[11]: GE1_RXD[3]
124 * MPP[13]: SYSRST_OUTn
125 * MPP[14]: SATA1_ACT
126 * MPP[15]: SATA0_ACT
127 * MPP[16]: UA2_TXD
128 * MPP[17]: UA2_RXD
129 * MPP[18]: <UNKNOWN>
130 * MPP[19]: <UNKNOWN>
131 * MPP[20]: <UNKNOWN>
132 * MPP[21]: <UNKNOWN>
133 * MPP[22]: UA3_TXD
134 * MPP[23]: UA3_RXD
135 * MPP[48]: <UNKNOWN>
136 * MPP[49]: <UNKNOWN>
137 *
138 * Others: GPIO
139 *
140 * <UNKNOWN> entries are not documented, not on the schematics etc.
141 */
142 bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL0, 0x22222222);
143 bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL1, 0x33302222);
144 bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL2, 0x44333344);
145 bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL3, 0x00000000);
146 bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL4, 0x00000000);
147 bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL5, 0x00000000);
148 bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL6, 0x0000FFFF);
149 }
150
151 static void
152 platform_identify(void *dummy)
153 {
154
155 soc_identify();
156
157 /*
158 * XXX Board identification e.g. read out from FPGA or similar should
159 * go here
160 */
161 }
162 SYSINIT(platform_identify, SI_SUB_CPU, SI_ORDER_SECOND, platform_identify, NULL);
Cache object: 0d86ad368756cab63aa24e8b187de162
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