The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/mv/files.mv

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    1 # $FreeBSD: stable/8/sys/arm/mv/files.mv 208299 2010-05-19 14:50:07Z mav $
    2 #
    3 # The Marvell CPU cores
    4 # - Compliant with V5TE architecture
    5 # - Super scalar dual issue CPU
    6 # - Big/Little Endian
    7 # - MMU/MPU
    8 # - L1 Cache: Supports streaming and write allocate
    9 # - Variable pipeline stages
   10 # - Out-of-order execution
   11 # - Branch Prediction
   12 # - JTAG/ICE
   13 # - Vector Floating Point (VFP) unit
   14 #
   15 arm/arm/bus_space_generic.c     standard
   16 arm/arm/cpufunc_asm_arm10.S     standard
   17 arm/arm/cpufunc_asm_armv5_ec.S  standard
   18 arm/arm/cpufunc_asm_sheeva.S    standard
   19 arm/arm/irq_dispatch.S          standard
   20 
   21 arm/mv/bus_space.c              standard
   22 arm/mv/common.c                 standard
   23 arm/mv/gpio.c                   standard
   24 arm/mv/ic.c                     standard
   25 arm/mv/mv_machdep.c             standard
   26 arm/mv/mv_pci.c                 optional        pci
   27 arm/mv/mv_sata.c                optional        ata | atamvsata
   28 arm/mv/obio.c                   standard
   29 arm/mv/timer.c                  standard
   30 arm/mv/twsi.c                   optional        iicbus
   31 
   32 dev/mge/if_mge.c                optional        mge
   33 dev/mvs/mvs_soc.c               optional        mvs
   34 dev/uart/uart_bus_mbus.c        optional        uart
   35 dev/uart/uart_cpu_mv.c          optional        uart
   36 dev/uart/uart_dev_ns8250.c      optional        uart
   37 dev/usb/controller/ehci_mbus.c  optional        ehci

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