The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/mv/gpio.c

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    1 /*-
    2  * Copyright (c) 2006 Benno Rice.
    3  * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
    4  * All rights reserved.
    5  *
    6  * Adapted and extended for Marvell SoCs by Semihalf.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   27  *
   28  * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_gpio.c, rev 1
   29  */
   30 
   31 #include <sys/cdefs.h>
   32 __FBSDID("$FreeBSD: releng/9.1/sys/arm/mv/gpio.c 224051 2011-07-15 02:29:10Z marcel $");
   33 
   34 #include <sys/param.h>
   35 #include <sys/systm.h>
   36 #include <sys/bus.h>
   37 #include <sys/kernel.h>
   38 #include <sys/lock.h>
   39 #include <sys/interrupt.h>
   40 #include <sys/module.h>
   41 #include <sys/malloc.h>
   42 #include <sys/mutex.h>
   43 #include <sys/rman.h>
   44 #include <sys/queue.h>
   45 #include <sys/timetc.h>
   46 #include <machine/bus.h>
   47 #include <machine/fdt.h>
   48 #include <machine/intr.h>
   49 
   50 #include <dev/fdt/fdt_common.h>
   51 #include <dev/ofw/ofw_bus.h>
   52 #include <dev/ofw/ofw_bus_subr.h>
   53 
   54 #include <arm/mv/mvvar.h>
   55 #include <arm/mv/mvreg.h>
   56 
   57 #define GPIO_MAX_INTR_COUNT     8
   58 #define GPIO_PINS_PER_REG       32
   59 
   60 struct mv_gpio_softc {
   61         struct resource *       res[GPIO_MAX_INTR_COUNT + 1];
   62         void                    *ih_cookie[GPIO_MAX_INTR_COUNT];
   63         bus_space_tag_t         bst;
   64         bus_space_handle_t      bsh;
   65         uint8_t                 pin_num;        /* number of GPIO pins */
   66         uint8_t                 irq_num;        /* number of real IRQs occupied by GPIO controller */
   67 };
   68 
   69 extern struct resource_spec mv_gpio_res[];
   70 
   71 static struct mv_gpio_softc *mv_gpio_softc = NULL;
   72 static uint32_t gpio_setup[MV_GPIO_MAX_NPINS];
   73 
   74 static int      mv_gpio_probe(device_t);
   75 static int      mv_gpio_attach(device_t);
   76 static int      mv_gpio_intr(void *);
   77 
   78 static void     mv_gpio_intr_handler(int pin);
   79 static uint32_t mv_gpio_reg_read(uint32_t reg);
   80 static void     mv_gpio_reg_write(uint32_t reg, uint32_t val);
   81 static void     mv_gpio_reg_set(uint32_t reg, uint32_t val);
   82 static void     mv_gpio_reg_clear(uint32_t reg, uint32_t val);
   83 
   84 static void     mv_gpio_blink(uint32_t pin, uint8_t enable);
   85 static void     mv_gpio_polarity(uint32_t pin, uint8_t enable);
   86 static void     mv_gpio_level(uint32_t pin, uint8_t enable);
   87 static void     mv_gpio_edge(uint32_t pin, uint8_t enable);
   88 static void     mv_gpio_out_en(uint32_t pin, uint8_t enable);
   89 static void     mv_gpio_int_ack(uint32_t pin);
   90 static void     mv_gpio_value_set(uint32_t pin, uint8_t val);
   91 static uint32_t mv_gpio_value_get(uint32_t pin);
   92 
   93 static device_method_t mv_gpio_methods[] = {
   94         DEVMETHOD(device_probe,         mv_gpio_probe),
   95         DEVMETHOD(device_attach,        mv_gpio_attach),
   96         { 0, 0 }
   97 };
   98 
   99 static driver_t mv_gpio_driver = {
  100         "gpio",
  101         mv_gpio_methods,
  102         sizeof(struct mv_gpio_softc),
  103 };
  104 
  105 static devclass_t mv_gpio_devclass;
  106 
  107 DRIVER_MODULE(gpio, simplebus, mv_gpio_driver, mv_gpio_devclass, 0, 0);
  108 
  109 typedef int (*gpios_phandler_t)(phandle_t, pcell_t *, int);
  110 
  111 struct gpio_ctrl_entry {
  112         const char              *compat;
  113         gpios_phandler_t        handler;
  114 };
  115 
  116 int mv_handle_gpios_prop(phandle_t ctrl, pcell_t *gpios, int len);
  117 int gpio_get_config_from_dt(void);
  118 
  119 struct gpio_ctrl_entry gpio_controllers[] = {
  120         { "mrvl,gpio", &mv_handle_gpios_prop },
  121         { NULL, NULL }
  122 };
  123 
  124 static int
  125 mv_gpio_probe(device_t dev)
  126 {
  127 
  128         if (!ofw_bus_is_compatible(dev, "mrvl,gpio"))
  129                 return (ENXIO);
  130 
  131         device_set_desc(dev, "Marvell Integrated GPIO Controller");
  132         return (0);
  133 }
  134 
  135 static int
  136 mv_gpio_attach(device_t dev)
  137 {
  138         int error, i;
  139         struct mv_gpio_softc *sc;
  140         uint32_t dev_id, rev_id;
  141 
  142         sc = (struct mv_gpio_softc *)device_get_softc(dev);
  143         if (sc == NULL)
  144                 return (ENXIO);
  145 
  146         mv_gpio_softc = sc;
  147 
  148         /* Get chip id and revision */
  149         soc_id(&dev_id, &rev_id);
  150 
  151         if (dev_id == MV_DEV_88F5182 ||
  152             dev_id == MV_DEV_88F5281 ||
  153             dev_id == MV_DEV_MV78100 ||
  154             dev_id == MV_DEV_MV78100_Z0 ) {
  155                 sc->pin_num = 32;
  156                 sc->irq_num = 4;
  157 
  158         } else if (dev_id == MV_DEV_88F6281) {
  159                 sc->pin_num = 50;
  160                 sc->irq_num = 7;
  161 
  162         } else {
  163                 device_printf(dev, "unknown chip id=0x%x\n", dev_id);
  164                 return (ENXIO);
  165         }
  166 
  167         error = bus_alloc_resources(dev, mv_gpio_res, sc->res);
  168         if (error) {
  169                 device_printf(dev, "could not allocate resources\n");
  170                 return (ENXIO);
  171         }
  172 
  173         sc->bst = rman_get_bustag(sc->res[0]);
  174         sc->bsh = rman_get_bushandle(sc->res[0]);
  175 
  176         /* Disable and clear all interrupts */
  177         bus_space_write_4(sc->bst, sc->bsh, GPIO_INT_EDGE_MASK, 0);
  178         bus_space_write_4(sc->bst, sc->bsh, GPIO_INT_LEV_MASK, 0);
  179         bus_space_write_4(sc->bst, sc->bsh, GPIO_INT_CAUSE, 0);
  180 
  181         if (sc->pin_num > GPIO_PINS_PER_REG) {
  182                 bus_space_write_4(sc->bst, sc->bsh,
  183                     GPIO_HI_INT_EDGE_MASK, 0);
  184                 bus_space_write_4(sc->bst, sc->bsh,
  185                     GPIO_HI_INT_LEV_MASK, 0);
  186                 bus_space_write_4(sc->bst, sc->bsh,
  187                     GPIO_HI_INT_CAUSE, 0);
  188         }
  189 
  190         for (i = 0; i < sc->irq_num; i++) {
  191                 if (bus_setup_intr(dev, sc->res[1 + i],
  192                     INTR_TYPE_MISC, mv_gpio_intr, NULL,
  193                     sc, &sc->ih_cookie[i]) != 0) {
  194                         bus_release_resources(dev, mv_gpio_res, sc->res);
  195                         device_printf(dev, "could not set up intr %d\n", i);
  196                         return (ENXIO);
  197                 }
  198         }
  199 
  200         return (platform_gpio_init());
  201 }
  202 
  203 static int
  204 mv_gpio_intr(void *arg)
  205 {
  206         uint32_t int_cause, gpio_val;
  207         uint32_t int_cause_hi, gpio_val_hi = 0;
  208         int i;
  209 
  210         int_cause = mv_gpio_reg_read(GPIO_INT_CAUSE);
  211         gpio_val = mv_gpio_reg_read(GPIO_DATA_IN);
  212         gpio_val &= int_cause;
  213         if (mv_gpio_softc->pin_num > GPIO_PINS_PER_REG) {
  214                 int_cause_hi = mv_gpio_reg_read(GPIO_HI_INT_CAUSE);
  215                 gpio_val_hi = mv_gpio_reg_read(GPIO_HI_DATA_IN);
  216                 gpio_val_hi &= int_cause_hi;
  217         }
  218 
  219         i = 0;
  220         while (gpio_val != 0) {
  221                 if (gpio_val & 1)
  222                         mv_gpio_intr_handler(i);
  223                 gpio_val >>= 1;
  224                 i++;
  225         }
  226 
  227         if (mv_gpio_softc->pin_num > GPIO_PINS_PER_REG) {
  228                 i = 0;
  229                 while (gpio_val_hi != 0) {
  230                         if (gpio_val_hi & 1)
  231                                 mv_gpio_intr_handler(i + GPIO_PINS_PER_REG);
  232                         gpio_val_hi >>= 1;
  233                         i++;
  234                 }
  235         }
  236 
  237         return (FILTER_HANDLED);
  238 }
  239 
  240 /*
  241  * GPIO interrupt handling
  242  */
  243 
  244 static struct intr_event *gpio_events[MV_GPIO_MAX_NPINS];
  245 
  246 int
  247 mv_gpio_setup_intrhandler(const char *name, driver_filter_t *filt,
  248     void (*hand)(void *), void *arg, int pin, int flags, void **cookiep)
  249 {
  250         struct  intr_event *event;
  251         int     error;
  252 
  253         if (pin < 0 || pin >= mv_gpio_softc->pin_num)
  254                 return (ENXIO);
  255         event = gpio_events[pin];
  256         if (event == NULL) {
  257                 error = intr_event_create(&event, (void *)pin, 0, pin,
  258                     (void (*)(void *))mv_gpio_intr_mask,
  259                     (void (*)(void *))mv_gpio_intr_unmask,
  260                     (void (*)(void *))mv_gpio_int_ack,
  261                     NULL,
  262                     "gpio%d:", pin);
  263                 if (error != 0)
  264                         return (error);
  265                 gpio_events[pin] = event;
  266         }
  267 
  268         intr_event_add_handler(event, name, filt, hand, arg,
  269             intr_priority(flags), flags, cookiep);
  270         return (0);
  271 }
  272 
  273 void
  274 mv_gpio_intr_mask(int pin)
  275 {
  276 
  277         if (pin >= mv_gpio_softc->pin_num)
  278                 return;
  279 
  280         if (gpio_setup[pin] & MV_GPIO_IN_IRQ_EDGE)
  281                 mv_gpio_edge(pin, 0);
  282         else
  283                 mv_gpio_level(pin, 0);
  284 }
  285 
  286 void
  287 mv_gpio_intr_unmask(int pin)
  288 {
  289 
  290         if (pin >= mv_gpio_softc->pin_num)
  291                 return;
  292 
  293         if (gpio_setup[pin] & MV_GPIO_IN_IRQ_EDGE)
  294                 mv_gpio_edge(pin, 1);
  295         else
  296                 mv_gpio_level(pin, 1);
  297 }
  298 
  299 static void
  300 mv_gpio_intr_handler(int pin)
  301 {
  302         struct intr_event *event;
  303 
  304         event = gpio_events[pin];
  305         if (event == NULL || TAILQ_EMPTY(&event->ie_handlers))
  306                 return;
  307 
  308         intr_event_handle(event, NULL);
  309 }
  310 
  311 static int
  312 mv_gpio_configure(uint32_t pin, uint32_t flags)
  313 {
  314 
  315         if (pin >= mv_gpio_softc->pin_num)
  316                 return (EINVAL);
  317 
  318         if (flags & MV_GPIO_OUT_BLINK)
  319                 mv_gpio_blink(pin, 1);
  320         if (flags & MV_GPIO_IN_POL_LOW)
  321                 mv_gpio_polarity(pin, 1);
  322         if (flags & MV_GPIO_IN_IRQ_EDGE)
  323                 mv_gpio_edge(pin, 1);
  324         if (flags & MV_GPIO_IN_IRQ_LEVEL)
  325                 mv_gpio_level(pin, 1);
  326 
  327         gpio_setup[pin] = flags;
  328 
  329         return (0);
  330 }
  331 
  332 void
  333 mv_gpio_out(uint32_t pin, uint8_t val, uint8_t enable)
  334 {
  335 
  336         mv_gpio_value_set(pin, val);
  337         mv_gpio_out_en(pin, enable);
  338 }
  339 
  340 uint8_t
  341 mv_gpio_in(uint32_t pin)
  342 {
  343 
  344         return (mv_gpio_value_get(pin) ? 1 : 0);
  345 }
  346 
  347 static uint32_t
  348 mv_gpio_reg_read(uint32_t reg)
  349 {
  350 
  351         return (bus_space_read_4(mv_gpio_softc->bst,
  352             mv_gpio_softc->bsh, reg));
  353 }
  354 
  355 static void
  356 mv_gpio_reg_write(uint32_t reg, uint32_t val)
  357 {
  358 
  359         bus_space_write_4(mv_gpio_softc->bst,
  360             mv_gpio_softc->bsh, reg, val);
  361 }
  362 
  363 static void
  364 mv_gpio_reg_set(uint32_t reg, uint32_t pin)
  365 {
  366         uint32_t reg_val;
  367 
  368         reg_val = mv_gpio_reg_read(reg);
  369         reg_val |= GPIO(pin);
  370         mv_gpio_reg_write(reg, reg_val);
  371 }
  372 
  373 static void
  374 mv_gpio_reg_clear(uint32_t reg, uint32_t pin)
  375 {
  376         uint32_t reg_val;
  377 
  378         reg_val = mv_gpio_reg_read(reg);
  379         reg_val &= ~(GPIO(pin));
  380         mv_gpio_reg_write(reg, reg_val);
  381 }
  382 
  383 static void
  384 mv_gpio_out_en(uint32_t pin, uint8_t enable)
  385 {
  386         uint32_t reg;
  387 
  388         if (pin >= mv_gpio_softc->pin_num)
  389                 return;
  390 
  391         if (pin >= GPIO_PINS_PER_REG) {
  392                 reg = GPIO_HI_DATA_OUT_EN_CTRL;
  393                 pin -= GPIO_PINS_PER_REG;
  394         } else
  395                 reg = GPIO_DATA_OUT_EN_CTRL;
  396 
  397         if (enable)
  398                 mv_gpio_reg_clear(reg, pin);
  399         else
  400                 mv_gpio_reg_set(reg, pin);
  401 }
  402 
  403 static void
  404 mv_gpio_blink(uint32_t pin, uint8_t enable)
  405 {
  406         uint32_t reg;
  407 
  408         if (pin >= mv_gpio_softc->pin_num)
  409                 return;
  410 
  411         if (pin >= GPIO_PINS_PER_REG) {
  412                 reg = GPIO_HI_BLINK_EN;
  413                 pin -= GPIO_PINS_PER_REG;
  414         } else
  415                 reg = GPIO_BLINK_EN;
  416 
  417         if (enable)
  418                 mv_gpio_reg_set(reg, pin);
  419         else
  420                 mv_gpio_reg_clear(reg, pin);
  421 }
  422 
  423 static void
  424 mv_gpio_polarity(uint32_t pin, uint8_t enable)
  425 {
  426         uint32_t reg;
  427 
  428         if (pin >= mv_gpio_softc->pin_num)
  429                 return;
  430 
  431         if (pin >= GPIO_PINS_PER_REG) {
  432                 reg = GPIO_HI_DATA_IN_POLAR;
  433                 pin -= GPIO_PINS_PER_REG;
  434         } else
  435                 reg = GPIO_DATA_IN_POLAR;
  436 
  437         if (enable)
  438                 mv_gpio_reg_set(reg, pin);
  439         else
  440                 mv_gpio_reg_clear(reg, pin);
  441 }
  442 
  443 static void
  444 mv_gpio_level(uint32_t pin, uint8_t enable)
  445 {
  446         uint32_t reg;
  447 
  448         if (pin >= mv_gpio_softc->pin_num)
  449                 return;
  450 
  451         if (pin >= GPIO_PINS_PER_REG) {
  452                 reg = GPIO_HI_INT_LEV_MASK;
  453                 pin -= GPIO_PINS_PER_REG;
  454         } else
  455                 reg = GPIO_INT_LEV_MASK;
  456 
  457         if (enable)
  458                 mv_gpio_reg_set(reg, pin);
  459         else
  460                 mv_gpio_reg_clear(reg, pin);
  461 }
  462 
  463 static void
  464 mv_gpio_edge(uint32_t pin, uint8_t enable)
  465 {
  466         uint32_t reg;
  467 
  468         if (pin >= mv_gpio_softc->pin_num)
  469                 return;
  470 
  471         if (pin >= GPIO_PINS_PER_REG) {
  472                 reg = GPIO_HI_INT_EDGE_MASK;
  473                 pin -= GPIO_PINS_PER_REG;
  474         } else
  475                 reg = GPIO_INT_EDGE_MASK;
  476 
  477         if (enable)
  478                 mv_gpio_reg_set(reg, pin);
  479         else
  480                 mv_gpio_reg_clear(reg, pin);
  481 }
  482 
  483 static void
  484 mv_gpio_int_ack(uint32_t pin)
  485 {
  486         uint32_t reg;
  487 
  488         if (pin >= mv_gpio_softc->pin_num)
  489                 return;
  490 
  491         if (pin >= GPIO_PINS_PER_REG) {
  492                 reg = GPIO_HI_INT_CAUSE;
  493                 pin -= GPIO_PINS_PER_REG;
  494         } else
  495                 reg = GPIO_INT_CAUSE;
  496 
  497         mv_gpio_reg_clear(reg, pin);
  498 }
  499 
  500 static uint32_t
  501 mv_gpio_value_get(uint32_t pin)
  502 {
  503         uint32_t reg, reg_val;
  504 
  505         if (pin >= mv_gpio_softc->pin_num)
  506                 return (0);
  507 
  508         if (pin >= GPIO_PINS_PER_REG) {
  509                 reg = GPIO_HI_DATA_IN;
  510                 pin -= GPIO_PINS_PER_REG;
  511         } else
  512                 reg = GPIO_DATA_IN;
  513 
  514         reg_val = mv_gpio_reg_read(reg);
  515 
  516         return (reg_val & GPIO(pin));
  517 }
  518 
  519 static void
  520 mv_gpio_value_set(uint32_t pin, uint8_t val)
  521 {
  522         uint32_t reg;
  523 
  524         if (pin >= mv_gpio_softc->pin_num)
  525                 return;
  526 
  527         if (pin >= GPIO_PINS_PER_REG) {
  528                 reg = GPIO_HI_DATA_OUT;
  529                 pin -= GPIO_PINS_PER_REG;
  530         } else
  531                 reg = GPIO_DATA_OUT;
  532 
  533         if (val)
  534                 mv_gpio_reg_set(reg, pin);
  535         else
  536                 mv_gpio_reg_clear(reg, pin);
  537 }
  538 
  539 int
  540 mv_handle_gpios_prop(phandle_t ctrl, pcell_t *gpios, int len)
  541 {
  542         pcell_t gpio_cells, pincnt;
  543         int inc, t, tuples, tuple_size;
  544         int dir, flags, pin;
  545         u_long gpio_ctrl, size;
  546         struct mv_gpio_softc sc;
  547 
  548         pincnt = 0;
  549         if (OF_getproplen(ctrl, "gpio-controller") <= 0)
  550                 /* Node is not a GPIO controller. */
  551                 return (ENXIO);
  552 
  553         if (OF_getprop(ctrl, "#gpio-cells", &gpio_cells, sizeof(pcell_t)) < 0)
  554                 return (ENXIO);
  555 
  556         gpio_cells = fdt32_to_cpu(gpio_cells);
  557         if (gpio_cells != 3)
  558                 return (ENXIO);
  559 
  560         tuple_size = gpio_cells * sizeof(pcell_t) + sizeof(phandle_t);
  561         tuples = len / tuple_size;
  562 
  563         if (fdt_regsize(ctrl, &gpio_ctrl, &size))
  564                 return (ENXIO);
  565 
  566         if (OF_getprop(ctrl, "pin-count", &pincnt, sizeof(pcell_t)) < 0)
  567                 return (ENXIO);
  568         sc.pin_num = fdt32_to_cpu(pincnt);
  569 
  570         /*
  571          * Skip controller reference, since controller's phandle is given
  572          * explicitly (in a function argument).
  573          */
  574         inc = sizeof(ihandle_t) / sizeof(pcell_t);
  575         gpios += inc;
  576 
  577         for (t = 0; t < tuples; t++) {
  578                 pin = fdt32_to_cpu(gpios[0]);
  579                 dir = fdt32_to_cpu(gpios[1]);
  580                 flags = fdt32_to_cpu(gpios[2]);
  581 
  582                 mv_gpio_configure(pin, flags);
  583 
  584                 if (dir == 1)
  585                         /* Input. */
  586                         mv_gpio_out_en(pin, 0);
  587                 else {
  588                         /* Output. */
  589                         if (flags & MV_GPIO_OUT_OPEN_DRAIN)
  590                                 mv_gpio_out(pin, 0, 1);
  591 
  592                         if (flags & MV_GPIO_OUT_OPEN_SRC)
  593                                 mv_gpio_out(pin, 1, 1);
  594                 }
  595                 gpios += gpio_cells + inc;
  596         }
  597 
  598         return (0);
  599 }
  600 
  601 #define MAX_PINS_PER_NODE       5
  602 #define GPIOS_PROP_CELLS        4
  603 int
  604 platform_gpio_init(void)
  605 {
  606         phandle_t child, parent, root, ctrl;
  607         ihandle_t ctrl_ihandle;
  608         pcell_t gpios[MAX_PINS_PER_NODE * GPIOS_PROP_CELLS];
  609         struct gpio_ctrl_entry *e;
  610         int len, rv;
  611 
  612         root = OF_finddevice("/");
  613         len = 0;
  614         parent = root;
  615 
  616         /* Traverse through entire tree to find nodes with 'gpios' prop */
  617         for (child = OF_child(parent); child != 0; child = OF_peer(child)) {
  618 
  619                 /* Find a 'leaf'. Start the search from this node. */
  620                 while (OF_child(child)) {
  621                         parent = child;
  622                         child = OF_child(child);
  623                 }
  624                 if ((len = OF_getproplen(child, "gpios")) > 0) {
  625 
  626                         if (len > sizeof(gpios))
  627                                 return (ENXIO);
  628 
  629                         /* Get 'gpios' property. */
  630                         OF_getprop(child, "gpios", &gpios, len);
  631 
  632                         e = (struct gpio_ctrl_entry *)&gpio_controllers;
  633 
  634                         /* Find and call a handler. */
  635                         for (; e->compat; e++) {
  636                                 /*
  637                                  * First cell of 'gpios' property should
  638                                  * contain a ref. to a node defining GPIO
  639                                  * controller.
  640                                  */
  641                                 ctrl_ihandle = (ihandle_t)gpios[0];
  642                                 ctrl_ihandle = fdt32_to_cpu(ctrl_ihandle);
  643                                 ctrl = OF_instance_to_package(ctrl_ihandle);
  644 
  645                                 if (fdt_is_compatible(ctrl, e->compat))
  646                                         /* Call a handler. */
  647                                         if ((rv = e->handler(ctrl,
  648                                             (pcell_t *)&gpios, len)))
  649                                                 return (rv);
  650                         }
  651                 }
  652 
  653                 if (OF_peer(child) == 0) {
  654                         /* No more siblings. */
  655                         child = parent;
  656                         parent = OF_parent(child);
  657                 }
  658         }
  659         return (0);
  660 }

Cache object: 1380a15a4abb5f930d6a08942465ab31


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