The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/mv/ic.c

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    1 /*-
    2  * Copyright (c) 2006 Benno Rice.
    3  * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD.
    4  * All rights reserved.
    5  *
    6  * Adapted and extended to Marvell SoCs by Semihalf.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   27  *
   28  * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_icu.c, rev 1
   29  */
   30 
   31 #include <sys/cdefs.h>
   32 __FBSDID("$FreeBSD: releng/11.1/sys/arm/mv/ic.c 261410 2014-02-02 19:17:28Z ian $");
   33 
   34 #include <sys/param.h>
   35 #include <sys/systm.h>
   36 #include <sys/bus.h>
   37 #include <sys/kernel.h>
   38 #include <sys/ktr.h>
   39 #include <sys/module.h>
   40 #include <sys/rman.h>
   41 #include <machine/bus.h>
   42 #include <machine/intr.h>
   43 
   44 #include <dev/ofw/ofw_bus.h>
   45 #include <dev/ofw/ofw_bus_subr.h>
   46 
   47 #include <arm/mv/mvreg.h>
   48 #include <arm/mv/mvvar.h>
   49 
   50 struct mv_ic_softc {
   51         struct resource *       ic_res[1];
   52         bus_space_tag_t         ic_bst;
   53         bus_space_handle_t      ic_bsh;
   54         int                     ic_high_regs;
   55         int                     ic_error_regs;
   56 };
   57 
   58 static struct resource_spec mv_ic_spec[] = {
   59         { SYS_RES_MEMORY,       0,      RF_ACTIVE },
   60         { -1, 0 }
   61 };
   62 
   63 static struct mv_ic_softc *mv_ic_sc = NULL;
   64 
   65 static int      mv_ic_probe(device_t);
   66 static int      mv_ic_attach(device_t);
   67 
   68 uint32_t        mv_ic_get_cause(void);
   69 uint32_t        mv_ic_get_mask(void);
   70 void            mv_ic_set_mask(uint32_t);
   71 uint32_t        mv_ic_get_cause_hi(void);
   72 uint32_t        mv_ic_get_mask_hi(void);
   73 void            mv_ic_set_mask_hi(uint32_t);
   74 uint32_t        mv_ic_get_cause_error(void);
   75 uint32_t        mv_ic_get_mask_error(void);
   76 void            mv_ic_set_mask_error(uint32_t);
   77 static void     arm_mask_irq_all(void);
   78 
   79 static int
   80 mv_ic_probe(device_t dev)
   81 {
   82 
   83         if (!ofw_bus_status_okay(dev))
   84                 return (ENXIO);
   85 
   86         if (!ofw_bus_is_compatible(dev, "mrvl,pic"))
   87                 return (ENXIO);
   88 
   89         device_set_desc(dev, "Marvell Integrated Interrupt Controller");
   90         return (0);
   91 }
   92 
   93 static int
   94 mv_ic_attach(device_t dev)
   95 {
   96         struct mv_ic_softc *sc;
   97         uint32_t dev_id, rev_id;
   98         int error;
   99 
  100         sc = (struct mv_ic_softc *)device_get_softc(dev);
  101 
  102         if (mv_ic_sc != NULL)
  103                 return (ENXIO);
  104         mv_ic_sc = sc;
  105 
  106         soc_id(&dev_id, &rev_id);
  107 
  108         sc->ic_high_regs = 0;
  109         sc->ic_error_regs = 0;
  110 
  111         if (dev_id == MV_DEV_88F6281 ||
  112             dev_id == MV_DEV_88F6282 ||
  113             dev_id == MV_DEV_MV78100 ||
  114             dev_id == MV_DEV_MV78100_Z0)
  115                 sc->ic_high_regs = 1;
  116 
  117         if (dev_id == MV_DEV_MV78100 || dev_id == MV_DEV_MV78100_Z0)
  118                 sc->ic_error_regs = 1;
  119 
  120         error = bus_alloc_resources(dev, mv_ic_spec, sc->ic_res);
  121         if (error) {
  122                 device_printf(dev, "could not allocate resources\n");
  123                 return (ENXIO);
  124         }
  125 
  126         sc->ic_bst = rman_get_bustag(sc->ic_res[0]);
  127         sc->ic_bsh = rman_get_bushandle(sc->ic_res[0]);
  128 
  129         /* Mask all interrupts */
  130         arm_mask_irq_all();
  131 
  132         return (0);
  133 }
  134 
  135 static device_method_t mv_ic_methods[] = {
  136         DEVMETHOD(device_probe,         mv_ic_probe),
  137         DEVMETHOD(device_attach,        mv_ic_attach),
  138         { 0, 0 }
  139 };
  140 
  141 static driver_t mv_ic_driver = {
  142         "ic",
  143         mv_ic_methods,
  144         sizeof(struct mv_ic_softc),
  145 };
  146 
  147 static devclass_t mv_ic_devclass;
  148 
  149 DRIVER_MODULE(ic, simplebus, mv_ic_driver, mv_ic_devclass, 0, 0);
  150 
  151 int
  152 arm_get_next_irq(int last)
  153 {
  154         u_int filt, irq;
  155         int next;
  156 
  157         filt = ~((last >= 0) ? (2 << last) - 1 : 0);
  158         irq = mv_ic_get_cause() & mv_ic_get_mask();
  159         if (irq & filt) {
  160                 next = ffs(irq & filt) - 1;
  161                 goto out;
  162         }
  163         if (mv_ic_sc->ic_high_regs) {
  164                 filt = ~((last >= 32) ? (2 << (last - 32)) - 1 : 0);
  165                 irq = mv_ic_get_cause_hi() & mv_ic_get_mask_hi();
  166                 if (irq & filt) {
  167                         next = ffs(irq & filt) + 31;
  168                         goto out;
  169                 }
  170         }
  171         if (mv_ic_sc->ic_error_regs) {
  172                 filt = ~((last >= 64) ? (2 << (last - 64)) - 1 : 0);
  173                 irq = mv_ic_get_cause_error() & mv_ic_get_mask_error();
  174                 if (irq & filt) {
  175                         next = ffs(irq & filt) + 63;
  176                         goto out;
  177                 }
  178         }
  179         next = -1;
  180 
  181  out:
  182         CTR3(KTR_INTR, "%s: last=%d, next=%d", __func__, last, next);
  183         return (next);
  184 }
  185 
  186 static void
  187 arm_mask_irq_all(void)
  188 {
  189 
  190         mv_ic_set_mask(0);
  191 
  192         if (mv_ic_sc->ic_high_regs)
  193                 mv_ic_set_mask_hi(0);
  194 
  195         if (mv_ic_sc->ic_error_regs)
  196                 mv_ic_set_mask_error(0);
  197 }
  198 
  199 void
  200 arm_mask_irq(uintptr_t nb)
  201 {
  202         uint32_t        mr;
  203 
  204         if (nb < 32) {
  205                 mr = mv_ic_get_mask();
  206                 mr &= ~(1 << nb);
  207                 mv_ic_set_mask(mr);
  208 
  209         } else if ((nb < 64) && mv_ic_sc->ic_high_regs) {
  210                 mr = mv_ic_get_mask_hi();
  211                 mr &= ~(1 << (nb - 32));
  212                 mv_ic_set_mask_hi(mr);
  213 
  214         } else if ((nb < 96) && mv_ic_sc->ic_error_regs) {
  215                 mr = mv_ic_get_mask_error();
  216                 mr &= ~(1 << (nb - 64));
  217                 mv_ic_set_mask_error(mr);
  218         }
  219 }
  220 
  221 void
  222 arm_unmask_irq(uintptr_t nb)
  223 {
  224         uint32_t        mr;
  225 
  226         if (nb < 32) {
  227                 mr = mv_ic_get_mask();
  228                 mr |= (1 << nb);
  229                 mv_ic_set_mask(mr);
  230 
  231         } else if ((nb < 64) && mv_ic_sc->ic_high_regs) {
  232                 mr = mv_ic_get_mask_hi();
  233                 mr |= (1 << (nb - 32));
  234                 mv_ic_set_mask_hi(mr);
  235 
  236         } else if ((nb < 96) && mv_ic_sc->ic_error_regs) {
  237                 mr = mv_ic_get_mask_error();
  238                 mr |= (1 << (nb - 64));
  239                 mv_ic_set_mask_error(mr);
  240         }
  241 }
  242 
  243 void
  244 mv_ic_set_mask(uint32_t val)
  245 {
  246 
  247         bus_space_write_4(mv_ic_sc->ic_bst, mv_ic_sc->ic_bsh,
  248             IRQ_MASK, val);
  249 }
  250 
  251 uint32_t
  252 mv_ic_get_mask(void)
  253 {
  254 
  255         return (bus_space_read_4(mv_ic_sc->ic_bst,
  256             mv_ic_sc->ic_bsh, IRQ_MASK));
  257 }
  258 
  259 uint32_t
  260 mv_ic_get_cause(void)
  261 {
  262 
  263         return (bus_space_read_4(mv_ic_sc->ic_bst,
  264             mv_ic_sc->ic_bsh, IRQ_CAUSE));
  265 }
  266 
  267 void
  268 mv_ic_set_mask_hi(uint32_t val)
  269 {
  270 
  271         bus_space_write_4(mv_ic_sc->ic_bst, mv_ic_sc->ic_bsh,
  272             IRQ_MASK_HI, val);
  273 }
  274 
  275 uint32_t
  276 mv_ic_get_mask_hi(void)
  277 {
  278 
  279         return (bus_space_read_4(mv_ic_sc->ic_bst,
  280             mv_ic_sc->ic_bsh, IRQ_MASK_HI));
  281 }
  282 
  283 uint32_t
  284 mv_ic_get_cause_hi(void)
  285 {
  286 
  287         return (bus_space_read_4(mv_ic_sc->ic_bst,
  288             mv_ic_sc->ic_bsh, IRQ_CAUSE_HI));
  289 }
  290 
  291 void
  292 mv_ic_set_mask_error(uint32_t val)
  293 {
  294 
  295         bus_space_write_4(mv_ic_sc->ic_bst, mv_ic_sc->ic_bsh,
  296             IRQ_MASK_ERROR, val);
  297 }
  298 
  299 uint32_t
  300 mv_ic_get_mask_error(void)
  301 {
  302 
  303         return (bus_space_read_4(mv_ic_sc->ic_bst,
  304             mv_ic_sc->ic_bsh, IRQ_MASK_ERROR));
  305 }
  306 
  307 uint32_t
  308 mv_ic_get_cause_error(void)
  309 {
  310 
  311         return (bus_space_read_4(mv_ic_sc->ic_bst,
  312             mv_ic_sc->ic_bsh, IRQ_CAUSE_ERROR));
  313 }

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