The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/mv/ic.c

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    1 /*-
    2  * Copyright (c) 2006 Benno Rice.
    3  * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD.
    4  * All rights reserved.
    5  *
    6  * Adapted and extended to Marvell SoCs by Semihalf.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   27  *
   28  * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_icu.c, rev 1
   29  */
   30 
   31 #include <sys/cdefs.h>
   32 __FBSDID("$FreeBSD: stable/9/sys/arm/mv/ic.c 218427 2011-02-08 01:49:30Z marcel $");
   33 
   34 #include <sys/param.h>
   35 #include <sys/systm.h>
   36 #include <sys/bus.h>
   37 #include <sys/kernel.h>
   38 #include <sys/ktr.h>
   39 #include <sys/module.h>
   40 #include <sys/rman.h>
   41 #include <machine/bus.h>
   42 #include <machine/intr.h>
   43 
   44 #include <dev/ofw/ofw_bus.h>
   45 #include <dev/ofw/ofw_bus_subr.h>
   46 
   47 #include <arm/mv/mvreg.h>
   48 #include <arm/mv/mvvar.h>
   49 
   50 struct mv_ic_softc {
   51         struct resource *       ic_res[1];
   52         bus_space_tag_t         ic_bst;
   53         bus_space_handle_t      ic_bsh;
   54         int                     ic_high_regs;
   55         int                     ic_error_regs;
   56 };
   57 
   58 static struct resource_spec mv_ic_spec[] = {
   59         { SYS_RES_MEMORY,       0,      RF_ACTIVE },
   60         { -1, 0 }
   61 };
   62 
   63 static struct mv_ic_softc *mv_ic_sc = NULL;
   64 
   65 static int      mv_ic_probe(device_t);
   66 static int      mv_ic_attach(device_t);
   67 
   68 uint32_t        mv_ic_get_cause(void);
   69 uint32_t        mv_ic_get_mask(void);
   70 void            mv_ic_set_mask(uint32_t);
   71 uint32_t        mv_ic_get_cause_hi(void);
   72 uint32_t        mv_ic_get_mask_hi(void);
   73 void            mv_ic_set_mask_hi(uint32_t);
   74 uint32_t        mv_ic_get_cause_error(void);
   75 uint32_t        mv_ic_get_mask_error(void);
   76 void            mv_ic_set_mask_error(uint32_t);
   77 static void     arm_mask_irq_all(void);
   78 
   79 static int
   80 mv_ic_probe(device_t dev)
   81 {
   82 
   83         if (!ofw_bus_is_compatible(dev, "mrvl,pic"))
   84                 return (ENXIO);
   85 
   86         device_set_desc(dev, "Marvell Integrated Interrupt Controller");
   87         return (0);
   88 }
   89 
   90 static int
   91 mv_ic_attach(device_t dev)
   92 {
   93         struct mv_ic_softc *sc;
   94         uint32_t dev_id, rev_id;
   95         int error;
   96 
   97         sc = (struct mv_ic_softc *)device_get_softc(dev);
   98 
   99         if (mv_ic_sc != NULL)
  100                 return (ENXIO);
  101         mv_ic_sc = sc;
  102 
  103         soc_id(&dev_id, &rev_id);
  104 
  105         sc->ic_high_regs = 0;
  106         sc->ic_error_regs = 0;
  107 
  108         if (dev_id == MV_DEV_88F6281 || dev_id == MV_DEV_MV78100 ||
  109             dev_id == MV_DEV_MV78100_Z0)
  110                 sc->ic_high_regs = 1;
  111 
  112         if (dev_id == MV_DEV_MV78100 || dev_id == MV_DEV_MV78100_Z0)
  113                 sc->ic_error_regs = 1;
  114 
  115         error = bus_alloc_resources(dev, mv_ic_spec, sc->ic_res);
  116         if (error) {
  117                 device_printf(dev, "could not allocate resources\n");
  118                 return (ENXIO);
  119         }
  120 
  121         sc->ic_bst = rman_get_bustag(sc->ic_res[0]);
  122         sc->ic_bsh = rman_get_bushandle(sc->ic_res[0]);
  123 
  124         /* Mask all interrupts */
  125         arm_mask_irq_all();
  126 
  127         return (0);
  128 }
  129 
  130 static device_method_t mv_ic_methods[] = {
  131         DEVMETHOD(device_probe,         mv_ic_probe),
  132         DEVMETHOD(device_attach,        mv_ic_attach),
  133         { 0, 0 }
  134 };
  135 
  136 static driver_t mv_ic_driver = {
  137         "ic",
  138         mv_ic_methods,
  139         sizeof(struct mv_ic_softc),
  140 };
  141 
  142 static devclass_t mv_ic_devclass;
  143 
  144 DRIVER_MODULE(ic, simplebus, mv_ic_driver, mv_ic_devclass, 0, 0);
  145 
  146 int
  147 arm_get_next_irq(int last)
  148 {
  149         u_int filt, irq;
  150         int next;
  151 
  152         filt = ~((last >= 0) ? (2 << last) - 1 : 0);
  153         irq = mv_ic_get_cause() & mv_ic_get_mask();
  154         if (irq & filt) {
  155                 next = ffs(irq & filt) - 1;
  156                 goto out;
  157         }
  158         if (mv_ic_sc->ic_high_regs) {
  159                 filt = ~((last >= 32) ? (2 << (last - 32)) - 1 : 0);
  160                 irq = mv_ic_get_cause_hi() & mv_ic_get_mask_hi();
  161                 if (irq & filt) {
  162                         next = ffs(irq & filt) + 31;
  163                         goto out;
  164                 }
  165         }
  166         if (mv_ic_sc->ic_error_regs) {
  167                 filt = ~((last >= 64) ? (2 << (last - 64)) - 1 : 0);
  168                 irq = mv_ic_get_cause_error() & mv_ic_get_mask_error();
  169                 if (irq & filt) {
  170                         next = ffs(irq & filt) + 63;
  171                         goto out;
  172                 }
  173         }
  174         next = -1;
  175 
  176  out:
  177         CTR3(KTR_INTR, "%s: last=%d, next=%d", __func__, last, next);
  178         return (next);
  179 }
  180 
  181 static void
  182 arm_mask_irq_all(void)
  183 {
  184 
  185         mv_ic_set_mask(0);
  186 
  187         if (mv_ic_sc->ic_high_regs)
  188                 mv_ic_set_mask_hi(0);
  189 
  190         if (mv_ic_sc->ic_error_regs)
  191                 mv_ic_set_mask_error(0);
  192 }
  193 
  194 void
  195 arm_mask_irq(uintptr_t nb)
  196 {
  197         uint32_t        mr;
  198 
  199         if (nb < 32) {
  200                 mr = mv_ic_get_mask();
  201                 mr &= ~(1 << nb);
  202                 mv_ic_set_mask(mr);
  203 
  204         } else if ((nb < 64) && mv_ic_sc->ic_high_regs) {
  205                 mr = mv_ic_get_mask_hi();
  206                 mr &= ~(1 << (nb - 32));
  207                 mv_ic_set_mask_hi(mr);
  208 
  209         } else if ((nb < 96) && mv_ic_sc->ic_error_regs) {
  210                 mr = mv_ic_get_mask_error();
  211                 mr &= ~(1 << (nb - 64));
  212                 mv_ic_set_mask_error(mr);
  213         }
  214 }
  215 
  216 void
  217 arm_unmask_irq(uintptr_t nb)
  218 {
  219         uint32_t        mr;
  220 
  221         if (nb < 32) {
  222                 mr = mv_ic_get_mask();
  223                 mr |= (1 << nb);
  224                 mv_ic_set_mask(mr);
  225 
  226         } else if ((nb < 64) && mv_ic_sc->ic_high_regs) {
  227                 mr = mv_ic_get_mask_hi();
  228                 mr |= (1 << (nb - 32));
  229                 mv_ic_set_mask_hi(mr);
  230 
  231         } else if ((nb < 96) && mv_ic_sc->ic_error_regs) {
  232                 mr = mv_ic_get_mask_error();
  233                 mr |= (1 << (nb - 64));
  234                 mv_ic_set_mask_error(mr);
  235         }
  236 }
  237 
  238 void
  239 mv_ic_set_mask(uint32_t val)
  240 {
  241 
  242         bus_space_write_4(mv_ic_sc->ic_bst, mv_ic_sc->ic_bsh,
  243             IRQ_MASK, val);
  244 }
  245 
  246 uint32_t
  247 mv_ic_get_mask(void)
  248 {
  249 
  250         return (bus_space_read_4(mv_ic_sc->ic_bst,
  251             mv_ic_sc->ic_bsh, IRQ_MASK));
  252 }
  253 
  254 uint32_t
  255 mv_ic_get_cause(void)
  256 {
  257 
  258         return (bus_space_read_4(mv_ic_sc->ic_bst,
  259             mv_ic_sc->ic_bsh, IRQ_CAUSE));
  260 }
  261 
  262 void
  263 mv_ic_set_mask_hi(uint32_t val)
  264 {
  265 
  266         bus_space_write_4(mv_ic_sc->ic_bst, mv_ic_sc->ic_bsh,
  267             IRQ_MASK_HI, val);
  268 }
  269 
  270 uint32_t
  271 mv_ic_get_mask_hi(void)
  272 {
  273 
  274         return (bus_space_read_4(mv_ic_sc->ic_bst,
  275             mv_ic_sc->ic_bsh, IRQ_MASK_HI));
  276 }
  277 
  278 uint32_t
  279 mv_ic_get_cause_hi(void)
  280 {
  281 
  282         return (bus_space_read_4(mv_ic_sc->ic_bst,
  283             mv_ic_sc->ic_bsh, IRQ_CAUSE_HI));
  284 }
  285 
  286 void
  287 mv_ic_set_mask_error(uint32_t val)
  288 {
  289 
  290         bus_space_write_4(mv_ic_sc->ic_bst, mv_ic_sc->ic_bsh,
  291             IRQ_MASK_ERROR, val);
  292 }
  293 
  294 uint32_t
  295 mv_ic_get_mask_error(void)
  296 {
  297 
  298         return (bus_space_read_4(mv_ic_sc->ic_bst,
  299             mv_ic_sc->ic_bsh, IRQ_MASK_ERROR));
  300 }
  301 
  302 uint32_t
  303 mv_ic_get_cause_error(void)
  304 {
  305 
  306         return (bus_space_read_4(mv_ic_sc->ic_bst,
  307             mv_ic_sc->ic_bsh, IRQ_CAUSE_ERROR));
  308 }

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