kirkwood.c

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    1 /*-
    2  * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
    3  * All rights reserved.
    4  *
    5  * Developed by Semihalf.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  * 3. Neither the name of MARVELL nor the names of contributors
   16  *    may be used to endorse or promote products derived from this software
   17  *    without specific prior written permission.
   18  *
   19  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   22  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
   23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   29  * SUCH DAMAGE.
   30  */
   31 
   32 #include <sys/cdefs.h>
   33 __FBSDID("$FreeBSD: releng/8.4/sys/arm/mv/kirkwood/kirkwood.c 205192 2010-03-15 19:51:24Z raj $");
   34 
   35 #include <sys/param.h>
   36 #include <sys/systm.h>
   37 #include <sys/bus.h>
   38 
   39 #include <machine/bus.h>
   40 
   41 #include <arm/mv/mvreg.h>
   42 #include <arm/mv/mvvar.h>
   43 #include <arm/mv/mvwin.h>
   44 
   45 struct obio_device obio_devices[] = {
   46         { "ic", MV_IC_BASE, MV_IC_SIZE,
   47                 { -1 },
   48                 { -1 },
   49                 CPU_PM_CTRL_NONE
   50         },
   51         { "timer", MV_TIMERS_BASE, MV_TIMERS_SIZE,
   52                 { MV_INT_BRIDGE, -1 },
   53                 { -1 },
   54                 CPU_PM_CTRL_NONE
   55         },
   56         { "rtc", MV_RTC_BASE, MV_RTC_SIZE,
   57                 { -1 },
   58                 { -1 },
   59                 CPU_PM_CTRL_NONE
   60         },
   61         { "gpio", MV_GPIO_BASE, MV_GPIO_SIZE,
   62                 { MV_INT_GPIO7_0, MV_INT_GPIO15_8,
   63                   MV_INT_GPIO23_16, MV_INT_GPIO31_24, 
   64                   MV_INT_GPIOHI7_0, MV_INT_GPIOHI15_8,
   65                   MV_INT_GPIOHI23_16, -1 },
   66                 { -1 },
   67                 CPU_PM_CTRL_NONE
   68         },
   69         { "uart", MV_UART0_BASE, MV_UART_SIZE,
   70                 { MV_INT_UART0, -1 },
   71                 { -1 },
   72                 CPU_PM_CTRL_NONE
   73         },
   74         { "uart", MV_UART1_BASE, MV_UART_SIZE,
   75                 { MV_INT_UART1, -1 },
   76                 { -1 },
   77                 CPU_PM_CTRL_NONE
   78         },
   79         { "xor", MV_XOR_BASE, MV_XOR_SIZE,
   80                 { MV_INT_XOR0_CHAN0, MV_INT_XOR0_CHAN1,
   81                   MV_INT_XOR1_CHAN0, MV_INT_XOR1_CHAN1,
   82                   MV_INT_XOR0_ERR, MV_INT_XOR1_ERR,
   83                   -1 },
   84                 { -1 },
   85                 CPU_PM_CTRL_XOR0 | CPU_PM_CTRL_XOR1
   86         },
   87         { "ehci", MV_USB0_BASE, MV_USB_SIZE,
   88                 { MV_INT_USB_BERR, MV_INT_USB_CI, -1 },
   89                 { -1 },
   90                 CPU_PM_CTRL_USB0
   91         },
   92         { "mge", MV_ETH0_BASE, MV_ETH_SIZE,
   93                 { MV_INT_GBERX, MV_INT_GBETX, MV_INT_GBEMISC,
   94                   MV_INT_GBESUM, MV_INT_GBEERR, -1 },
   95                 { -1 },
   96                 CPU_PM_CTRL_GE0
   97         },
   98         { "twsi", MV_TWSI0_BASE, MV_TWSI_SIZE,
   99                 { -1 }, { -1 },
  100                 CPU_PM_CTRL_NONE
  101         },
  102         { "sata", MV_SATAHC_BASE, MV_SATAHC_SIZE,
  103                 { MV_INT_SATA, -1 },
  104                 { -1 },
  105                 CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1
  106         },
  107         { NULL, 0, 0, { 0 }, { 0 }, 0 }
  108 };
  109 
  110 const struct obio_pci mv_pci_info[] = {
  111         { MV_TYPE_PCIE,
  112                 MV_PCIE_BASE, MV_PCIE_SIZE,
  113                 MV_PCIE_IO_BASE, MV_PCIE_IO_SIZE,       4, 0xE0,
  114                 MV_PCIE_MEM_BASE, MV_PCIE_MEM_SIZE,     4, 0xE8,
  115                 NULL, MV_INT_PEX0
  116         },
  117 
  118         { 0, 0, 0 }
  119 };
  120 
  121 struct resource_spec mv_gpio_res[] = {
  122         { SYS_RES_MEMORY,       0,      RF_ACTIVE },
  123         { SYS_RES_IRQ,          0,      RF_ACTIVE },
  124         { SYS_RES_IRQ,          1,      RF_ACTIVE },
  125         { SYS_RES_IRQ,          2,      RF_ACTIVE },
  126         { SYS_RES_IRQ,          3,      RF_ACTIVE },
  127         { SYS_RES_IRQ,          4,      RF_ACTIVE },
  128         { SYS_RES_IRQ,          5,      RF_ACTIVE },
  129         { SYS_RES_IRQ,          6,      RF_ACTIVE },
  130         { -1, 0 }
  131 };
  132 
  133 struct resource_spec mv_xor_res[] = {
  134         { SYS_RES_MEMORY,       0,      RF_ACTIVE },
  135         { SYS_RES_IRQ,          0,      RF_ACTIVE },
  136         { SYS_RES_IRQ,          1,      RF_ACTIVE },
  137         { SYS_RES_IRQ,          2,      RF_ACTIVE },
  138         { SYS_RES_IRQ,          3,      RF_ACTIVE },
  139         { SYS_RES_IRQ,          4,      RF_ACTIVE },
  140         { SYS_RES_IRQ,          5,      RF_ACTIVE },
  141         { -1, 0 }
  142 };
  143 
  144 const struct decode_win cpu_win_tbl[] = {
  145         /* Device bus BOOT */
  146         { 1, 0x0f, MV_DEV_BOOT_PHYS_BASE, MV_DEV_BOOT_SIZE, -1 },
  147 
  148         /* Device bus CS0 */
  149         { 1, 0x1e, MV_DEV_CS0_PHYS_BASE, MV_DEV_CS0_SIZE, -1 },
  150 
  151         /* Device bus CS1 */
  152         { 1, 0x1d, MV_DEV_CS1_PHYS_BASE, MV_DEV_CS1_SIZE, -1 },
  153 
  154         /* Device bus CS2 */
  155         { 1, 0x1b, MV_DEV_CS2_PHYS_BASE, MV_DEV_CS2_SIZE, -1 },
  156 
  157         /* CESA */
  158         { 3, 0x00, MV_CESA_SRAM_PHYS_BASE, MV_CESA_SRAM_SIZE, -1 },
  159 
  160 };
  161 const struct decode_win *cpu_wins = cpu_win_tbl;
  162 int cpu_wins_no = sizeof(cpu_win_tbl) / sizeof(struct decode_win);
  163 
  164 const struct decode_win xor_win_tbl[] = {
  165         /* PCIE MEM */
  166         { 4, 0xE8, MV_PCIE_MEM_PHYS_BASE, MV_PCIE_MEM_SIZE, -1 },
  167 };
  168 const struct decode_win *xor_wins = xor_win_tbl;
  169 int xor_wins_no = sizeof(xor_win_tbl) / sizeof(struct decode_win);
  170 
  171 uint32_t
  172 get_tclk(void)
  173 {
  174         uint32_t dev, rev;
  175 
  176         /*
  177          * On Kirkwood TCLK is not configurable and depends on silicon
  178          * revision:
  179          * - A0 and A1 have TCLK hardcoded to 200 MHz.
  180          * - Z0 and others have TCLK hardcoded to 166 MHz.
  181          */
  182         soc_id(&dev, &rev);
  183         if (dev == MV_DEV_88F6281 && (rev == 2 || rev == 3))
  184                 return (TCLK_200MHZ);
  185 
  186         return (TCLK_166MHZ);
  187 }

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sys/arm/mv/kirkwood/kirkwood.c