Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/arm/mv/mpic.c
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2006 Benno Rice. 5 * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD. 6 * Copyright (c) 2012 Semihalf. 7 * All rights reserved. 8 * 9 * Developed by Semihalf. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_icu.c, rev 1 32 * from: FreeBSD: src/sys/arm/mv/ic.c,v 1.5 2011/02/08 01:49:30 33 */ 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 #include "opt_platform.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/bus.h> 43 #include <sys/kernel.h> 44 #include <sys/cpuset.h> 45 #include <sys/ktr.h> 46 #include <sys/kdb.h> 47 #include <sys/module.h> 48 #include <sys/lock.h> 49 #include <sys/mutex.h> 50 #include <sys/rman.h> 51 #include <sys/proc.h> 52 #include <sys/smp.h> 53 54 #include <machine/bus.h> 55 #include <machine/intr.h> 56 #include <machine/smp.h> 57 58 #include <arm/mv/mvvar.h> 59 #include <arm/mv/mvreg.h> 60 61 #include <dev/ofw/ofw_bus.h> 62 #include <dev/ofw/ofw_bus_subr.h> 63 #include <dev/fdt/fdt_common.h> 64 65 #include "pic_if.h" 66 67 #ifdef DEBUG 68 #define debugf(fmt, args...) do { printf("%s(): ", __func__); \ 69 printf(fmt,##args); } while (0) 70 #else 71 #define debugf(fmt, args...) 72 #endif 73 74 #define MPIC_INT_LOCAL 3 75 #define MPIC_INT_ERR 4 76 #define MPIC_INT_MSI 96 77 78 #define MPIC_IRQ_MASK 0x3ff 79 80 #define MPIC_CTRL 0x0 81 #define MPIC_SOFT_INT 0x4 82 #define MPIC_SOFT_INT_DRBL1 (1 << 5) 83 #define MPIC_ERR_CAUSE 0x20 84 #define MPIC_ISE 0x30 85 #define MPIC_ICE 0x34 86 #define MPIC_INT_CTL(irq) (0x100 + (irq)*4) 87 88 #define MPIC_INT_IRQ_FIQ_MASK(cpuid) (0x101 << (cpuid)) 89 #define MPIC_CTRL_NIRQS(ctrl) (((ctrl) >> 2) & 0x3ff) 90 91 #define MPIC_IN_DRBL 0x08 92 #define MPIC_IN_DRBL_MASK 0x0c 93 #define MPIC_PPI_CAUSE 0x10 94 #define MPIC_CTP 0x40 95 #define MPIC_IIACK 0x44 96 #define MPIC_ISM 0x48 97 #define MPIC_ICM 0x4c 98 #define MPIC_ERR_MASK 0x50 99 #define MPIC_LOCAL_MASK 0x54 100 #define MPIC_CPU(n) (n) * 0x100 101 102 #define MPIC_PPI 32 103 104 struct mv_mpic_irqsrc { 105 struct intr_irqsrc mmi_isrc; 106 u_int mmi_irq; 107 }; 108 109 struct mv_mpic_softc { 110 device_t sc_dev; 111 struct resource * mpic_res[4]; 112 bus_space_tag_t mpic_bst; 113 bus_space_handle_t mpic_bsh; 114 bus_space_tag_t cpu_bst; 115 bus_space_handle_t cpu_bsh; 116 bus_space_tag_t drbl_bst; 117 bus_space_handle_t drbl_bsh; 118 struct mtx mtx; 119 struct mv_mpic_irqsrc * mpic_isrcs; 120 int nirqs; 121 void * intr_hand; 122 }; 123 124 static struct resource_spec mv_mpic_spec[] = { 125 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 126 { SYS_RES_MEMORY, 1, RF_ACTIVE }, 127 { SYS_RES_MEMORY, 2, RF_ACTIVE | RF_OPTIONAL }, 128 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_OPTIONAL }, 129 { -1, 0 } 130 }; 131 132 static struct ofw_compat_data compat_data[] = { 133 {"mrvl,mpic", true}, 134 {"marvell,mpic", true}, 135 {NULL, false} 136 }; 137 138 static struct mv_mpic_softc *mv_mpic_sc = NULL; 139 140 void mpic_send_ipi(int cpus, u_int ipi); 141 142 static int mv_mpic_probe(device_t); 143 static int mv_mpic_attach(device_t); 144 uint32_t mv_mpic_get_cause(void); 145 uint32_t mv_mpic_get_cause_err(void); 146 uint32_t mv_mpic_get_msi(void); 147 static void mpic_unmask_irq(uintptr_t nb); 148 static void mpic_mask_irq(uintptr_t nb); 149 static void mpic_mask_irq_err(uintptr_t nb); 150 static void mpic_unmask_irq_err(uintptr_t nb); 151 static boolean_t mpic_irq_is_percpu(uintptr_t); 152 static int mpic_intr(void *arg); 153 static void mpic_unmask_msi(void); 154 void mpic_init_secondary(device_t); 155 void mpic_ipi_send(device_t, struct intr_irqsrc*, cpuset_t, u_int); 156 int mpic_ipi_read(int); 157 void mpic_ipi_clear(int); 158 159 #define MPIC_WRITE(softc, reg, val) \ 160 bus_space_write_4((softc)->mpic_bst, (softc)->mpic_bsh, (reg), (val)) 161 #define MPIC_READ(softc, reg) \ 162 bus_space_read_4((softc)->mpic_bst, (softc)->mpic_bsh, (reg)) 163 164 #define MPIC_CPU_WRITE(softc, reg, val) \ 165 bus_space_write_4((softc)->cpu_bst, (softc)->cpu_bsh, (reg), (val)) 166 #define MPIC_CPU_READ(softc, reg) \ 167 bus_space_read_4((softc)->cpu_bst, (softc)->cpu_bsh, (reg)) 168 169 #define MPIC_DRBL_WRITE(softc, reg, val) \ 170 bus_space_write_4((softc)->drbl_bst, (softc)->drbl_bsh, (reg), (val)) 171 #define MPIC_DRBL_READ(softc, reg) \ 172 bus_space_read_4((softc)->drbl_bst, (softc)->drbl_bsh, (reg)) 173 174 static int 175 mv_mpic_probe(device_t dev) 176 { 177 178 if (!ofw_bus_status_okay(dev)) 179 return (ENXIO); 180 181 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 182 return (ENXIO); 183 184 device_set_desc(dev, "Marvell Integrated Interrupt Controller"); 185 return (0); 186 } 187 188 static int 189 mv_mpic_register_isrcs(struct mv_mpic_softc *sc) 190 { 191 int error; 192 uint32_t irq; 193 struct intr_irqsrc *isrc; 194 const char *name; 195 196 sc->mpic_isrcs = malloc(sc->nirqs * sizeof (*sc->mpic_isrcs), M_DEVBUF, 197 M_WAITOK | M_ZERO); 198 199 name = device_get_nameunit(sc->sc_dev); 200 for (irq = 0; irq < sc->nirqs; irq++) { 201 sc->mpic_isrcs[irq].mmi_irq = irq; 202 203 isrc = &sc->mpic_isrcs[irq].mmi_isrc; 204 if (irq < MPIC_PPI) { 205 error = intr_isrc_register(isrc, sc->sc_dev, 206 INTR_ISRCF_PPI, "%s", name); 207 } else { 208 error = intr_isrc_register(isrc, sc->sc_dev, 0, "%s", 209 name); 210 } 211 if (error != 0) { 212 /* XXX call intr_isrc_deregister() */ 213 device_printf(sc->sc_dev, "%s failed", __func__); 214 return (error); 215 } 216 } 217 return (0); 218 } 219 220 static int 221 mv_mpic_attach(device_t dev) 222 { 223 struct mv_mpic_softc *sc; 224 int error; 225 uint32_t val; 226 int cpu; 227 228 sc = (struct mv_mpic_softc *)device_get_softc(dev); 229 230 if (mv_mpic_sc != NULL) 231 return (ENXIO); 232 mv_mpic_sc = sc; 233 234 sc->sc_dev = dev; 235 236 mtx_init(&sc->mtx, "MPIC lock", NULL, MTX_SPIN); 237 238 error = bus_alloc_resources(dev, mv_mpic_spec, sc->mpic_res); 239 if (error) { 240 device_printf(dev, "could not allocate resources\n"); 241 return (ENXIO); 242 } 243 if (sc->mpic_res[3] == NULL) 244 device_printf(dev, "No interrupt to use.\n"); 245 else 246 bus_setup_intr(dev, sc->mpic_res[3], INTR_TYPE_CLK, 247 mpic_intr, NULL, sc, &sc->intr_hand); 248 249 sc->mpic_bst = rman_get_bustag(sc->mpic_res[0]); 250 sc->mpic_bsh = rman_get_bushandle(sc->mpic_res[0]); 251 252 sc->cpu_bst = rman_get_bustag(sc->mpic_res[1]); 253 sc->cpu_bsh = rman_get_bushandle(sc->mpic_res[1]); 254 255 if (sc->mpic_res[2] != NULL) { 256 /* This is required only if MSIs are used. */ 257 sc->drbl_bst = rman_get_bustag(sc->mpic_res[2]); 258 sc->drbl_bsh = rman_get_bushandle(sc->mpic_res[2]); 259 } 260 261 MPIC_WRITE(mv_mpic_sc, MPIC_CTRL, 1); 262 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CTP, 0); 263 264 val = MPIC_READ(mv_mpic_sc, MPIC_CTRL); 265 sc->nirqs = MPIC_CTRL_NIRQS(val); 266 267 if (mv_mpic_register_isrcs(sc) != 0) { 268 device_printf(dev, "could not register PIC ISRCs\n"); 269 bus_release_resources(dev, mv_mpic_spec, sc->mpic_res); 270 return (ENXIO); 271 } 272 273 OF_device_register_xref(OF_xref_from_node(ofw_bus_get_node(dev)), dev); 274 275 if (intr_pic_register(dev, OF_xref_from_device(dev)) == NULL) { 276 device_printf(dev, "could not register PIC\n"); 277 bus_release_resources(dev, mv_mpic_spec, sc->mpic_res); 278 return (ENXIO); 279 } 280 281 mpic_unmask_msi(); 282 283 /* Unmask CPU performance counters overflow irq */ 284 for (cpu = 0; cpu < mp_ncpus; cpu++) 285 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CPU(cpu) + MPIC_LOCAL_MASK, 286 (1 << cpu) | MPIC_CPU_READ(mv_mpic_sc, 287 MPIC_CPU(cpu) + MPIC_LOCAL_MASK)); 288 289 return (0); 290 } 291 292 static int 293 mpic_intr(void *arg) 294 { 295 struct mv_mpic_softc *sc; 296 uint32_t cause, irqsrc; 297 unsigned int irq; 298 u_int cpuid; 299 300 sc = arg; 301 cpuid = PCPU_GET(cpuid); 302 irq = 0; 303 304 for (cause = MPIC_CPU_READ(sc, MPIC_PPI_CAUSE); cause > 0; 305 cause >>= 1, irq++) { 306 if (cause & 1) { 307 irqsrc = MPIC_READ(sc, MPIC_INT_CTL(irq)); 308 if ((irqsrc & MPIC_INT_IRQ_FIQ_MASK(cpuid)) == 0) 309 continue; 310 if (intr_isrc_dispatch(&sc->mpic_isrcs[irq].mmi_isrc, 311 curthread->td_intr_frame) != 0) { 312 mpic_mask_irq(irq); 313 device_printf(sc->sc_dev, "Stray irq %u " 314 "disabled\n", irq); 315 } 316 } 317 } 318 319 return (FILTER_HANDLED); 320 } 321 322 static void 323 mpic_disable_intr(device_t dev, struct intr_irqsrc *isrc) 324 { 325 u_int irq; 326 327 irq = ((struct mv_mpic_irqsrc *)isrc)->mmi_irq; 328 mpic_mask_irq(irq); 329 } 330 331 static void 332 mpic_enable_intr(device_t dev, struct intr_irqsrc *isrc) 333 { 334 u_int irq; 335 336 irq = ((struct mv_mpic_irqsrc *)isrc)->mmi_irq; 337 mpic_unmask_irq(irq); 338 } 339 340 static int 341 mpic_map_intr(device_t dev, struct intr_map_data *data, 342 struct intr_irqsrc **isrcp) 343 { 344 struct intr_map_data_fdt *daf; 345 struct mv_mpic_softc *sc; 346 347 if (data->type != INTR_MAP_DATA_FDT) 348 return (ENOTSUP); 349 350 sc = device_get_softc(dev); 351 daf = (struct intr_map_data_fdt *)data; 352 353 if (daf->ncells !=1 || daf->cells[0] >= sc->nirqs) 354 return (EINVAL); 355 356 *isrcp = &sc->mpic_isrcs[daf->cells[0]].mmi_isrc; 357 return (0); 358 } 359 360 static void 361 mpic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 362 { 363 364 mpic_disable_intr(dev, isrc); 365 } 366 367 static void 368 mpic_post_ithread(device_t dev, struct intr_irqsrc *isrc) 369 { 370 371 mpic_enable_intr(dev, isrc); 372 } 373 374 static void 375 mpic_post_filter(device_t dev, struct intr_irqsrc *isrc) 376 { 377 } 378 379 static device_method_t mv_mpic_methods[] = { 380 DEVMETHOD(device_probe, mv_mpic_probe), 381 DEVMETHOD(device_attach, mv_mpic_attach), 382 383 DEVMETHOD(pic_disable_intr, mpic_disable_intr), 384 DEVMETHOD(pic_enable_intr, mpic_enable_intr), 385 DEVMETHOD(pic_map_intr, mpic_map_intr), 386 DEVMETHOD(pic_post_filter, mpic_post_filter), 387 DEVMETHOD(pic_post_ithread, mpic_post_ithread), 388 DEVMETHOD(pic_pre_ithread, mpic_pre_ithread), 389 DEVMETHOD(pic_init_secondary, mpic_init_secondary), 390 DEVMETHOD(pic_ipi_send, mpic_ipi_send), 391 { 0, 0 } 392 }; 393 394 static driver_t mv_mpic_driver = { 395 "mpic", 396 mv_mpic_methods, 397 sizeof(struct mv_mpic_softc), 398 }; 399 400 EARLY_DRIVER_MODULE(mpic, simplebus, mv_mpic_driver, 0, 0, 401 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE); 402 403 static void 404 mpic_unmask_msi(void) 405 { 406 407 mpic_unmask_irq(MPIC_INT_MSI); 408 } 409 410 static void 411 mpic_unmask_irq_err(uintptr_t nb) 412 { 413 uint32_t mask; 414 uint8_t bit_off; 415 416 MPIC_WRITE(mv_mpic_sc, MPIC_ISE, MPIC_INT_ERR); 417 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, MPIC_INT_ERR); 418 419 bit_off = nb - ERR_IRQ; 420 mask = MPIC_CPU_READ(mv_mpic_sc, MPIC_ERR_MASK); 421 mask |= (1 << bit_off); 422 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ERR_MASK, mask); 423 } 424 425 static void 426 mpic_mask_irq_err(uintptr_t nb) 427 { 428 uint32_t mask; 429 uint8_t bit_off; 430 431 bit_off = nb - ERR_IRQ; 432 mask = MPIC_CPU_READ(mv_mpic_sc, MPIC_ERR_MASK); 433 mask &= ~(1 << bit_off); 434 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ERR_MASK, mask); 435 } 436 437 static boolean_t 438 mpic_irq_is_percpu(uintptr_t nb) 439 { 440 if (nb < MPIC_PPI) 441 return TRUE; 442 443 return FALSE; 444 } 445 446 static void 447 mpic_unmask_irq(uintptr_t nb) 448 { 449 450 #ifdef SMP 451 int cpu; 452 453 if (nb == MPIC_INT_LOCAL) { 454 for (cpu = 0; cpu < mp_ncpus; cpu++) 455 MPIC_CPU_WRITE(mv_mpic_sc, 456 MPIC_CPU(cpu) + MPIC_ICM, nb); 457 return; 458 } 459 #endif 460 if (mpic_irq_is_percpu(nb)) 461 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, nb); 462 else if (nb < ERR_IRQ) 463 MPIC_WRITE(mv_mpic_sc, MPIC_ISE, nb); 464 else if (nb < MSI_IRQ) 465 mpic_unmask_irq_err(nb); 466 467 if (nb == 0) 468 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DRBL_MASK, 0xffffffff); 469 } 470 471 static void 472 mpic_mask_irq(uintptr_t nb) 473 { 474 475 #ifdef SMP 476 int cpu; 477 478 if (nb == MPIC_INT_LOCAL) { 479 for (cpu = 0; cpu < mp_ncpus; cpu++) 480 MPIC_CPU_WRITE(mv_mpic_sc, 481 MPIC_CPU(cpu) + MPIC_ISM, nb); 482 return; 483 } 484 #endif 485 if (mpic_irq_is_percpu(nb)) 486 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ISM, nb); 487 else if (nb < ERR_IRQ) 488 MPIC_WRITE(mv_mpic_sc, MPIC_ICE, nb); 489 else if (nb < MSI_IRQ) 490 mpic_mask_irq_err(nb); 491 } 492 493 uint32_t 494 mv_mpic_get_cause(void) 495 { 496 497 return (MPIC_CPU_READ(mv_mpic_sc, MPIC_IIACK)); 498 } 499 500 uint32_t 501 mv_mpic_get_cause_err(void) 502 { 503 uint32_t err_cause; 504 uint8_t bit_off; 505 506 err_cause = MPIC_READ(mv_mpic_sc, MPIC_ERR_CAUSE); 507 508 if (err_cause) 509 bit_off = ffs(err_cause) - 1; 510 else 511 return (-1); 512 513 debugf("%s: irq:%x cause:%x\n", __func__, bit_off, err_cause); 514 return (ERR_IRQ + bit_off); 515 } 516 517 uint32_t 518 mv_mpic_get_msi(void) 519 { 520 uint32_t cause; 521 uint8_t bit_off; 522 523 KASSERT(mv_mpic_sc->drbl_bst != NULL, ("No doorbell in mv_mpic_get_msi")); 524 cause = MPIC_DRBL_READ(mv_mpic_sc, 0); 525 526 if (cause) 527 bit_off = ffs(cause) - 1; 528 else 529 return (-1); 530 531 debugf("%s: irq:%x cause:%x\n", __func__, bit_off, cause); 532 533 cause &= ~(1 << bit_off); 534 MPIC_DRBL_WRITE(mv_mpic_sc, 0, cause); 535 536 return (MSI_IRQ + bit_off); 537 } 538 539 int 540 mv_msi_data(int irq, uint64_t *addr, uint32_t *data) 541 { 542 u_long phys, base, size; 543 phandle_t node; 544 int error; 545 546 node = ofw_bus_get_node(mv_mpic_sc->sc_dev); 547 548 /* Get physical address of register space */ 549 error = fdt_get_range(OF_parent(node), 0, &phys, &size); 550 if (error) { 551 printf("%s: Cannot get register physical address, err:%d", 552 __func__, error); 553 return (error); 554 } 555 556 /* Get offset of MPIC register space */ 557 error = fdt_regsize(node, &base, &size); 558 if (error) { 559 printf("%s: Cannot get MPIC register offset, err:%d", 560 __func__, error); 561 return (error); 562 } 563 564 *addr = phys + base + MPIC_SOFT_INT; 565 *data = MPIC_SOFT_INT_DRBL1 | irq; 566 567 return (0); 568 } 569 570 void 571 mpic_init_secondary(device_t dev) 572 { 573 } 574 575 void 576 mpic_ipi_send(device_t dev, struct intr_irqsrc *isrc, cpuset_t cpus, u_int ipi) 577 { 578 uint32_t val, i; 579 580 val = 0x00000000; 581 for (i = 0; i < MAXCPU; i++) 582 if (CPU_ISSET(i, &cpus)) 583 val |= (1 << (8 + i)); 584 val |= ipi; 585 MPIC_WRITE(mv_mpic_sc, MPIC_SOFT_INT, val); 586 } 587 588 int 589 mpic_ipi_read(int i __unused) 590 { 591 uint32_t val; 592 int ipi; 593 594 val = MPIC_CPU_READ(mv_mpic_sc, MPIC_IN_DRBL); 595 if (val) { 596 ipi = ffs(val) - 1; 597 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DRBL, ~(1 << ipi)); 598 return (ipi); 599 } 600 601 return (0x3ff); 602 } 603 604 void 605 mpic_ipi_clear(int ipi) 606 { 607 }
Cache object: c294f971536bf3a873d5b2a8d9da0fe7
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]