Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/arm/mv/mpic.c
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1 /*- 2 * Copyright (c) 2006 Benno Rice. 3 * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD. 4 * Copyright (c) 2012 Semihalf. 5 * All rights reserved. 6 * 7 * Developed by Semihalf. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_icu.c, rev 1 30 * from: FreeBSD: src/sys/arm/mv/ic.c,v 1.5 2011/02/08 01:49:30 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD: releng/11.0/sys/arm/mv/mpic.c 300410 2016-05-22 11:42:34Z skra $"); 35 36 #include "opt_platform.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/bus.h> 41 #include <sys/kernel.h> 42 #include <sys/cpuset.h> 43 #include <sys/ktr.h> 44 #include <sys/kdb.h> 45 #include <sys/module.h> 46 #include <sys/lock.h> 47 #include <sys/mutex.h> 48 #include <sys/rman.h> 49 #include <sys/proc.h> 50 51 #include <machine/bus.h> 52 #include <machine/intr.h> 53 #include <machine/cpufunc.h> 54 #include <machine/smp.h> 55 56 #include <arm/mv/mvvar.h> 57 #include <arm/mv/mvreg.h> 58 59 #include <dev/ofw/ofw_bus.h> 60 #include <dev/ofw/ofw_bus_subr.h> 61 #include <dev/fdt/fdt_common.h> 62 63 #ifdef INTRNG 64 #include "pic_if.h" 65 #endif 66 67 #ifdef DEBUG 68 #define debugf(fmt, args...) do { printf("%s(): ", __func__); \ 69 printf(fmt,##args); } while (0) 70 #else 71 #define debugf(fmt, args...) 72 #endif 73 74 #define MPIC_INT_ERR 4 75 #define MPIC_INT_MSI 96 76 77 #define MPIC_IRQ_MASK 0x3ff 78 79 #define MPIC_CTRL 0x0 80 #define MPIC_SOFT_INT 0x4 81 #define MPIC_SOFT_INT_DRBL1 (1 << 5) 82 #define MPIC_ERR_CAUSE 0x20 83 #define MPIC_ISE 0x30 84 #define MPIC_ICE 0x34 85 #define MPIC_INT_CTL(irq) (0x100 + (irq)*4) 86 87 #define MPIC_INT_IRQ_FIQ_MASK(cpuid) (0x101 << (cpuid)) 88 #define MPIC_CTRL_NIRQS(ctrl) (((ctrl) >> 2) & 0x3ff) 89 90 #define MPIC_IN_DRBL 0x08 91 #define MPIC_IN_DRBL_MASK 0x0c 92 #define MPIC_PPI_CAUSE 0x10 93 #define MPIC_CTP 0x40 94 #define MPIC_IIACK 0x44 95 #define MPIC_ISM 0x48 96 #define MPIC_ICM 0x4c 97 #define MPIC_ERR_MASK 0xe50 98 99 #define MPIC_PPI 32 100 101 #ifdef INTRNG 102 struct mv_mpic_irqsrc { 103 struct intr_irqsrc mmi_isrc; 104 u_int mmi_irq; 105 }; 106 #endif 107 108 struct mv_mpic_softc { 109 device_t sc_dev; 110 struct resource * mpic_res[4]; 111 bus_space_tag_t mpic_bst; 112 bus_space_handle_t mpic_bsh; 113 bus_space_tag_t cpu_bst; 114 bus_space_handle_t cpu_bsh; 115 bus_space_tag_t drbl_bst; 116 bus_space_handle_t drbl_bsh; 117 struct mtx mtx; 118 #ifdef INTRNG 119 struct mv_mpic_irqsrc * mpic_isrcs; 120 #endif 121 int nirqs; 122 void * intr_hand; 123 }; 124 125 static struct resource_spec mv_mpic_spec[] = { 126 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 127 { SYS_RES_MEMORY, 1, RF_ACTIVE }, 128 { SYS_RES_MEMORY, 2, RF_ACTIVE | RF_OPTIONAL }, 129 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_OPTIONAL }, 130 { -1, 0 } 131 }; 132 133 static struct ofw_compat_data compat_data[] = { 134 {"mrvl,mpic", true}, 135 {"marvell,mpic", true}, 136 {NULL, false} 137 }; 138 139 static struct mv_mpic_softc *mv_mpic_sc = NULL; 140 141 void mpic_send_ipi(int cpus, u_int ipi); 142 143 static int mv_mpic_probe(device_t); 144 static int mv_mpic_attach(device_t); 145 uint32_t mv_mpic_get_cause(void); 146 uint32_t mv_mpic_get_cause_err(void); 147 uint32_t mv_mpic_get_msi(void); 148 static void mpic_unmask_irq(uintptr_t nb); 149 static void mpic_mask_irq(uintptr_t nb); 150 static void mpic_mask_irq_err(uintptr_t nb); 151 static void mpic_unmask_irq_err(uintptr_t nb); 152 static int mpic_intr(void *arg); 153 static void mpic_unmask_msi(void); 154 #ifndef INTRNG 155 static void arm_mask_irq_err(uintptr_t); 156 static void arm_unmask_irq_err(uintptr_t); 157 #endif 158 159 #define MPIC_WRITE(softc, reg, val) \ 160 bus_space_write_4((softc)->mpic_bst, (softc)->mpic_bsh, (reg), (val)) 161 #define MPIC_READ(softc, reg) \ 162 bus_space_read_4((softc)->mpic_bst, (softc)->mpic_bsh, (reg)) 163 164 #define MPIC_CPU_WRITE(softc, reg, val) \ 165 bus_space_write_4((softc)->cpu_bst, (softc)->cpu_bsh, (reg), (val)) 166 #define MPIC_CPU_READ(softc, reg) \ 167 bus_space_read_4((softc)->cpu_bst, (softc)->cpu_bsh, (reg)) 168 169 #define MPIC_DRBL_WRITE(softc, reg, val) \ 170 bus_space_write_4((softc)->drbl_bst, (softc)->drbl_bsh, (reg), (val)) 171 #define MPIC_DRBL_READ(softc, reg) \ 172 bus_space_read_4((softc)->drbl_bst, (softc)->drbl_bsh, (reg)) 173 174 static int 175 mv_mpic_probe(device_t dev) 176 { 177 178 if (!ofw_bus_status_okay(dev)) 179 return (ENXIO); 180 181 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 182 return (ENXIO); 183 184 device_set_desc(dev, "Marvell Integrated Interrupt Controller"); 185 return (0); 186 } 187 188 #ifdef INTRNG 189 static int 190 mv_mpic_register_isrcs(struct mv_mpic_softc *sc) 191 { 192 int error; 193 uint32_t irq; 194 struct intr_irqsrc *isrc; 195 const char *name; 196 197 sc->mpic_isrcs = malloc(sc->nirqs * sizeof (*sc->mpic_isrcs), M_DEVBUF, 198 M_WAITOK | M_ZERO); 199 200 name = device_get_nameunit(sc->sc_dev); 201 for (irq = 0; irq < sc->nirqs; irq++) { 202 sc->mpic_isrcs[irq].mmi_irq = irq; 203 204 isrc = &sc->mpic_isrcs[irq].mmi_isrc; 205 if (irq < MPIC_PPI) { 206 error = intr_isrc_register(isrc, sc->sc_dev, 207 INTR_ISRCF_PPI, "%s", name); 208 } else { 209 error = intr_isrc_register(isrc, sc->sc_dev, 0, "%s", 210 name); 211 } 212 if (error != 0) { 213 /* XXX call intr_isrc_deregister() */ 214 device_printf(sc->sc_dev, "%s failed", __func__); 215 return (error); 216 } 217 } 218 return (0); 219 } 220 #endif 221 222 static int 223 mv_mpic_attach(device_t dev) 224 { 225 struct mv_mpic_softc *sc; 226 int error; 227 uint32_t val; 228 229 sc = (struct mv_mpic_softc *)device_get_softc(dev); 230 231 if (mv_mpic_sc != NULL) 232 return (ENXIO); 233 mv_mpic_sc = sc; 234 235 sc->sc_dev = dev; 236 237 mtx_init(&sc->mtx, "MPIC lock", NULL, MTX_SPIN); 238 239 error = bus_alloc_resources(dev, mv_mpic_spec, sc->mpic_res); 240 if (error) { 241 device_printf(dev, "could not allocate resources\n"); 242 return (ENXIO); 243 } 244 #ifdef INTRNG 245 if (sc->mpic_res[3] == NULL) 246 device_printf(dev, "No interrupt to use.\n"); 247 else 248 bus_setup_intr(dev, sc->mpic_res[3], INTR_TYPE_CLK, 249 mpic_intr, NULL, sc, &sc->intr_hand); 250 #endif 251 252 sc->mpic_bst = rman_get_bustag(sc->mpic_res[0]); 253 sc->mpic_bsh = rman_get_bushandle(sc->mpic_res[0]); 254 255 sc->cpu_bst = rman_get_bustag(sc->mpic_res[1]); 256 sc->cpu_bsh = rman_get_bushandle(sc->mpic_res[1]); 257 258 if (sc->mpic_res[2] != NULL) { 259 /* This is required only if MSIs are used. */ 260 sc->drbl_bst = rman_get_bustag(sc->mpic_res[2]); 261 sc->drbl_bsh = rman_get_bushandle(sc->mpic_res[2]); 262 } 263 264 bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh, 265 MPIC_CTRL, 1); 266 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CTP, 0); 267 268 val = MPIC_READ(mv_mpic_sc, MPIC_CTRL); 269 sc->nirqs = MPIC_CTRL_NIRQS(val); 270 271 #ifdef INTRNG 272 if (mv_mpic_register_isrcs(sc) != 0) { 273 device_printf(dev, "could not register PIC ISRCs\n"); 274 bus_release_resources(dev, mv_mpic_spec, sc->mpic_res); 275 return (ENXIO); 276 } 277 if (intr_pic_register(dev, OF_xref_from_device(dev)) == NULL) { 278 device_printf(dev, "could not register PIC\n"); 279 bus_release_resources(dev, mv_mpic_spec, sc->mpic_res); 280 return (ENXIO); 281 } 282 #endif 283 284 mpic_unmask_msi(); 285 286 return (0); 287 } 288 289 #ifdef INTRNG 290 static int 291 mpic_intr(void *arg) 292 { 293 struct mv_mpic_softc *sc; 294 uint32_t cause, irqsrc; 295 unsigned int irq; 296 u_int cpuid; 297 298 sc = arg; 299 cpuid = PCPU_GET(cpuid); 300 irq = 0; 301 302 for (cause = MPIC_CPU_READ(sc, MPIC_PPI_CAUSE); cause > 0; 303 cause >>= 1, irq++) { 304 if (cause & 1) { 305 irqsrc = MPIC_READ(sc, MPIC_INT_CTL(irq)); 306 if ((irqsrc & MPIC_INT_IRQ_FIQ_MASK(cpuid)) == 0) 307 continue; 308 if (intr_isrc_dispatch(&sc->mpic_isrcs[irq].mmi_isrc, 309 curthread->td_intr_frame) != 0) { 310 mpic_mask_irq(irq); 311 device_printf(sc->sc_dev, "Stray irq %u " 312 "disabled\n", irq); 313 } 314 } 315 } 316 317 return (FILTER_HANDLED); 318 } 319 320 static void 321 mpic_disable_intr(device_t dev, struct intr_irqsrc *isrc) 322 { 323 u_int irq; 324 325 irq = ((struct mv_mpic_irqsrc *)isrc)->mmi_irq; 326 mpic_mask_irq(irq); 327 } 328 329 static void 330 mpic_enable_intr(device_t dev, struct intr_irqsrc *isrc) 331 { 332 u_int irq; 333 334 irq = ((struct mv_mpic_irqsrc *)isrc)->mmi_irq; 335 mpic_unmask_irq(irq); 336 } 337 338 static int 339 mpic_map_intr(device_t dev, struct intr_map_data *data, 340 struct intr_irqsrc **isrcp) 341 { 342 struct intr_map_data_fdt *daf; 343 struct mv_mpic_softc *sc; 344 345 if (data->type != INTR_MAP_DATA_FDT) 346 return (ENOTSUP); 347 348 sc = device_get_softc(dev); 349 daf = (struct intr_map_data_fdt *)data; 350 351 if (daf->ncells !=1 || daf->cells[0] >= sc->nirqs) 352 return (EINVAL); 353 354 *isrcp = &sc->mpic_isrcs[daf->cells[0]].mmi_isrc; 355 return (0); 356 } 357 358 static void 359 mpic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 360 { 361 362 mpic_disable_intr(dev, isrc); 363 } 364 365 static void 366 mpic_post_ithread(device_t dev, struct intr_irqsrc *isrc) 367 { 368 369 mpic_enable_intr(dev, isrc); 370 } 371 372 static void 373 mpic_post_filter(device_t dev, struct intr_irqsrc *isrc) 374 { 375 } 376 #endif 377 378 static device_method_t mv_mpic_methods[] = { 379 DEVMETHOD(device_probe, mv_mpic_probe), 380 DEVMETHOD(device_attach, mv_mpic_attach), 381 382 #ifdef INTRNG 383 DEVMETHOD(pic_disable_intr, mpic_disable_intr), 384 DEVMETHOD(pic_enable_intr, mpic_enable_intr), 385 DEVMETHOD(pic_map_intr, mpic_map_intr), 386 DEVMETHOD(pic_post_filter, mpic_post_filter), 387 DEVMETHOD(pic_post_ithread, mpic_post_ithread), 388 DEVMETHOD(pic_pre_ithread, mpic_pre_ithread), 389 #endif 390 { 0, 0 } 391 }; 392 393 static driver_t mv_mpic_driver = { 394 "mpic", 395 mv_mpic_methods, 396 sizeof(struct mv_mpic_softc), 397 }; 398 399 static devclass_t mv_mpic_devclass; 400 401 EARLY_DRIVER_MODULE(mpic, simplebus, mv_mpic_driver, mv_mpic_devclass, 0, 0, 402 BUS_PASS_INTERRUPT); 403 404 #ifndef INTRNG 405 int 406 arm_get_next_irq(int last) 407 { 408 u_int irq, next = -1; 409 410 irq = mv_mpic_get_cause() & MPIC_IRQ_MASK; 411 CTR2(KTR_INTR, "%s: irq:%#x", __func__, irq); 412 413 if (irq != MPIC_IRQ_MASK) { 414 if (irq == MPIC_INT_ERR) 415 irq = mv_mpic_get_cause_err(); 416 if (irq == MPIC_INT_MSI) 417 irq = mv_mpic_get_msi(); 418 next = irq; 419 } 420 421 CTR3(KTR_INTR, "%s: last=%d, next=%d", __func__, last, next); 422 return (next); 423 } 424 425 /* 426 * XXX We can make arm_enable_irq to operate on ICE and then mask/unmask only 427 * by ISM/ICM and remove access to ICE in masking operation 428 */ 429 void 430 arm_mask_irq(uintptr_t nb) 431 { 432 433 mpic_mask_irq(nb); 434 } 435 436 437 static void 438 arm_mask_irq_err(uintptr_t nb) 439 { 440 441 mpic_mask_irq_err(nb); 442 } 443 444 void 445 arm_unmask_irq(uintptr_t nb) 446 { 447 448 mpic_unmask_irq(nb); 449 } 450 451 void 452 arm_unmask_irq_err(uintptr_t nb) 453 { 454 455 mpic_unmask_irq_err(nb); 456 } 457 #endif 458 459 static void 460 mpic_unmask_msi(void) 461 { 462 463 mpic_unmask_irq(MPIC_INT_MSI); 464 } 465 466 static void 467 mpic_unmask_irq_err(uintptr_t nb) 468 { 469 uint32_t mask; 470 uint8_t bit_off; 471 472 bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh, 473 MPIC_ISE, MPIC_INT_ERR); 474 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, MPIC_INT_ERR); 475 476 bit_off = nb - ERR_IRQ; 477 mask = MPIC_CPU_READ(mv_mpic_sc, MPIC_ERR_MASK); 478 mask |= (1 << bit_off); 479 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ERR_MASK, mask); 480 } 481 482 static void 483 mpic_mask_irq_err(uintptr_t nb) 484 { 485 uint32_t mask; 486 uint8_t bit_off; 487 488 bit_off = nb - ERR_IRQ; 489 mask = MPIC_CPU_READ(mv_mpic_sc, MPIC_ERR_MASK); 490 mask &= ~(1 << bit_off); 491 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ERR_MASK, mask); 492 } 493 494 static void 495 mpic_unmask_irq(uintptr_t nb) 496 { 497 498 if (nb < ERR_IRQ) { 499 bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh, 500 MPIC_ISE, nb); 501 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, nb); 502 } else if (nb < MSI_IRQ) 503 mpic_unmask_irq_err(nb); 504 505 if (nb == 0) 506 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DRBL_MASK, 0xffffffff); 507 } 508 509 static void 510 mpic_mask_irq(uintptr_t nb) 511 { 512 513 if (nb < ERR_IRQ) { 514 bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh, 515 MPIC_ICE, nb); 516 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ISM, nb); 517 } else if (nb < MSI_IRQ) 518 mpic_mask_irq_err(nb); 519 } 520 521 uint32_t 522 mv_mpic_get_cause(void) 523 { 524 525 return (MPIC_CPU_READ(mv_mpic_sc, MPIC_IIACK)); 526 } 527 528 uint32_t 529 mv_mpic_get_cause_err(void) 530 { 531 uint32_t err_cause; 532 uint8_t bit_off; 533 534 err_cause = bus_space_read_4(mv_mpic_sc->mpic_bst, 535 mv_mpic_sc->mpic_bsh, MPIC_ERR_CAUSE); 536 537 if (err_cause) 538 bit_off = ffs(err_cause) - 1; 539 else 540 return (-1); 541 542 debugf("%s: irq:%x cause:%x\n", __func__, bit_off, err_cause); 543 return (ERR_IRQ + bit_off); 544 } 545 546 uint32_t 547 mv_mpic_get_msi(void) 548 { 549 uint32_t cause; 550 uint8_t bit_off; 551 552 KASSERT(mv_mpic_sc->drbl_bst != NULL, ("No doorbell in mv_mpic_get_msi")); 553 cause = MPIC_DRBL_READ(mv_mpic_sc, 0); 554 555 if (cause) 556 bit_off = ffs(cause) - 1; 557 else 558 return (-1); 559 560 debugf("%s: irq:%x cause:%x\n", __func__, bit_off, cause); 561 562 cause &= ~(1 << bit_off); 563 MPIC_DRBL_WRITE(mv_mpic_sc, 0, cause); 564 565 return (MSI_IRQ + bit_off); 566 } 567 568 int 569 mv_msi_data(int irq, uint64_t *addr, uint32_t *data) 570 { 571 u_long phys, base, size; 572 phandle_t node; 573 int error; 574 575 node = ofw_bus_get_node(mv_mpic_sc->sc_dev); 576 577 /* Get physical address of register space */ 578 error = fdt_get_range(OF_parent(node), 0, &phys, &size); 579 if (error) { 580 printf("%s: Cannot get register physical address, err:%d", 581 __func__, error); 582 return (error); 583 } 584 585 /* Get offset of MPIC register space */ 586 error = fdt_regsize(node, &base, &size); 587 if (error) { 588 printf("%s: Cannot get MPIC register offset, err:%d", 589 __func__, error); 590 return (error); 591 } 592 593 *addr = phys + base + MPIC_SOFT_INT; 594 *data = MPIC_SOFT_INT_DRBL1 | irq; 595 596 return (0); 597 } 598 599 600 #if defined(SMP) && defined(SOC_MV_ARMADAXP) 601 void 602 intr_pic_init_secondary(void) 603 { 604 } 605 606 void 607 pic_ipi_send(cpuset_t cpus, u_int ipi) 608 { 609 uint32_t val, i; 610 611 val = 0x00000000; 612 for (i = 0; i < MAXCPU; i++) 613 if (CPU_ISSET(i, &cpus)) 614 val |= (1 << (8 + i)); 615 val |= ipi; 616 bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh, 617 MPIC_SOFT_INT, val); 618 } 619 620 int 621 pic_ipi_read(int i __unused) 622 { 623 uint32_t val; 624 int ipi; 625 626 val = MPIC_CPU_READ(mv_mpic_sc, MPIC_IN_DRBL); 627 if (val) { 628 ipi = ffs(val) - 1; 629 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DRBL, ~(1 << ipi)); 630 return (ipi); 631 } 632 633 return (0x3ff); 634 } 635 636 void 637 pic_ipi_clear(int ipi) 638 { 639 } 640 641 #endif
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