Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/arm/mv/mpic.c
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1 /*- 2 * Copyright (c) 2006 Benno Rice. 3 * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD. 4 * Copyright (c) 2012 Semihalf. 5 * All rights reserved. 6 * 7 * Developed by Semihalf. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_icu.c, rev 1 30 * from: FreeBSD: src/sys/arm/mv/ic.c,v 1.5 2011/02/08 01:49:30 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 #include "opt_platform.h" 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/bus.h> 41 #include <sys/kernel.h> 42 #include <sys/cpuset.h> 43 #include <sys/ktr.h> 44 #include <sys/kdb.h> 45 #include <sys/module.h> 46 #include <sys/lock.h> 47 #include <sys/mutex.h> 48 #include <sys/rman.h> 49 #include <sys/proc.h> 50 51 #include <machine/bus.h> 52 #include <machine/intr.h> 53 #include <machine/smp.h> 54 55 #include <arm/mv/mvvar.h> 56 #include <arm/mv/mvreg.h> 57 58 #include <dev/ofw/ofw_bus.h> 59 #include <dev/ofw/ofw_bus_subr.h> 60 #include <dev/fdt/fdt_common.h> 61 62 #ifdef INTRNG 63 #include "pic_if.h" 64 #endif 65 66 #ifdef DEBUG 67 #define debugf(fmt, args...) do { printf("%s(): ", __func__); \ 68 printf(fmt,##args); } while (0) 69 #else 70 #define debugf(fmt, args...) 71 #endif 72 73 #define MPIC_INT_ERR 4 74 #define MPIC_INT_MSI 96 75 76 #define MPIC_IRQ_MASK 0x3ff 77 78 #define MPIC_CTRL 0x0 79 #define MPIC_SOFT_INT 0x4 80 #define MPIC_SOFT_INT_DRBL1 (1 << 5) 81 #define MPIC_ERR_CAUSE 0x20 82 #define MPIC_ISE 0x30 83 #define MPIC_ICE 0x34 84 #define MPIC_INT_CTL(irq) (0x100 + (irq)*4) 85 86 #define MPIC_INT_IRQ_FIQ_MASK(cpuid) (0x101 << (cpuid)) 87 #define MPIC_CTRL_NIRQS(ctrl) (((ctrl) >> 2) & 0x3ff) 88 89 #define MPIC_IN_DRBL 0x08 90 #define MPIC_IN_DRBL_MASK 0x0c 91 #define MPIC_PPI_CAUSE 0x10 92 #define MPIC_CTP 0x40 93 #define MPIC_IIACK 0x44 94 #define MPIC_ISM 0x48 95 #define MPIC_ICM 0x4c 96 #define MPIC_ERR_MASK 0xe50 97 98 #define MPIC_PPI 32 99 100 #ifdef INTRNG 101 struct mv_mpic_irqsrc { 102 struct intr_irqsrc mmi_isrc; 103 u_int mmi_irq; 104 }; 105 #endif 106 107 struct mv_mpic_softc { 108 device_t sc_dev; 109 struct resource * mpic_res[4]; 110 bus_space_tag_t mpic_bst; 111 bus_space_handle_t mpic_bsh; 112 bus_space_tag_t cpu_bst; 113 bus_space_handle_t cpu_bsh; 114 bus_space_tag_t drbl_bst; 115 bus_space_handle_t drbl_bsh; 116 struct mtx mtx; 117 #ifdef INTRNG 118 struct mv_mpic_irqsrc * mpic_isrcs; 119 #endif 120 int nirqs; 121 void * intr_hand; 122 }; 123 124 static struct resource_spec mv_mpic_spec[] = { 125 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 126 { SYS_RES_MEMORY, 1, RF_ACTIVE }, 127 { SYS_RES_MEMORY, 2, RF_ACTIVE | RF_OPTIONAL }, 128 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_OPTIONAL }, 129 { -1, 0 } 130 }; 131 132 static struct ofw_compat_data compat_data[] = { 133 {"mrvl,mpic", true}, 134 {"marvell,mpic", true}, 135 {NULL, false} 136 }; 137 138 static struct mv_mpic_softc *mv_mpic_sc = NULL; 139 140 void mpic_send_ipi(int cpus, u_int ipi); 141 142 static int mv_mpic_probe(device_t); 143 static int mv_mpic_attach(device_t); 144 uint32_t mv_mpic_get_cause(void); 145 uint32_t mv_mpic_get_cause_err(void); 146 uint32_t mv_mpic_get_msi(void); 147 static void mpic_unmask_irq(uintptr_t nb); 148 static void mpic_mask_irq(uintptr_t nb); 149 static void mpic_mask_irq_err(uintptr_t nb); 150 static void mpic_unmask_irq_err(uintptr_t nb); 151 static int mpic_intr(void *arg); 152 static void mpic_unmask_msi(void); 153 #ifndef INTRNG 154 static void arm_mask_irq_err(uintptr_t); 155 static void arm_unmask_irq_err(uintptr_t); 156 #endif 157 158 #define MPIC_WRITE(softc, reg, val) \ 159 bus_space_write_4((softc)->mpic_bst, (softc)->mpic_bsh, (reg), (val)) 160 #define MPIC_READ(softc, reg) \ 161 bus_space_read_4((softc)->mpic_bst, (softc)->mpic_bsh, (reg)) 162 163 #define MPIC_CPU_WRITE(softc, reg, val) \ 164 bus_space_write_4((softc)->cpu_bst, (softc)->cpu_bsh, (reg), (val)) 165 #define MPIC_CPU_READ(softc, reg) \ 166 bus_space_read_4((softc)->cpu_bst, (softc)->cpu_bsh, (reg)) 167 168 #define MPIC_DRBL_WRITE(softc, reg, val) \ 169 bus_space_write_4((softc)->drbl_bst, (softc)->drbl_bsh, (reg), (val)) 170 #define MPIC_DRBL_READ(softc, reg) \ 171 bus_space_read_4((softc)->drbl_bst, (softc)->drbl_bsh, (reg)) 172 173 static int 174 mv_mpic_probe(device_t dev) 175 { 176 177 if (!ofw_bus_status_okay(dev)) 178 return (ENXIO); 179 180 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 181 return (ENXIO); 182 183 device_set_desc(dev, "Marvell Integrated Interrupt Controller"); 184 return (0); 185 } 186 187 #ifdef INTRNG 188 static int 189 mv_mpic_register_isrcs(struct mv_mpic_softc *sc) 190 { 191 int error; 192 uint32_t irq; 193 struct intr_irqsrc *isrc; 194 const char *name; 195 196 sc->mpic_isrcs = malloc(sc->nirqs * sizeof (*sc->mpic_isrcs), M_DEVBUF, 197 M_WAITOK | M_ZERO); 198 199 name = device_get_nameunit(sc->sc_dev); 200 for (irq = 0; irq < sc->nirqs; irq++) { 201 sc->mpic_isrcs[irq].mmi_irq = irq; 202 203 isrc = &sc->mpic_isrcs[irq].mmi_isrc; 204 if (irq < MPIC_PPI) { 205 error = intr_isrc_register(isrc, sc->sc_dev, 206 INTR_ISRCF_PPI, "%s", name); 207 } else { 208 error = intr_isrc_register(isrc, sc->sc_dev, 0, "%s", 209 name); 210 } 211 if (error != 0) { 212 /* XXX call intr_isrc_deregister() */ 213 device_printf(sc->sc_dev, "%s failed", __func__); 214 return (error); 215 } 216 } 217 return (0); 218 } 219 #endif 220 221 static int 222 mv_mpic_attach(device_t dev) 223 { 224 struct mv_mpic_softc *sc; 225 int error; 226 uint32_t val; 227 228 sc = (struct mv_mpic_softc *)device_get_softc(dev); 229 230 if (mv_mpic_sc != NULL) 231 return (ENXIO); 232 mv_mpic_sc = sc; 233 234 sc->sc_dev = dev; 235 236 mtx_init(&sc->mtx, "MPIC lock", NULL, MTX_SPIN); 237 238 error = bus_alloc_resources(dev, mv_mpic_spec, sc->mpic_res); 239 if (error) { 240 device_printf(dev, "could not allocate resources\n"); 241 return (ENXIO); 242 } 243 #ifdef INTRNG 244 if (sc->mpic_res[3] == NULL) 245 device_printf(dev, "No interrupt to use.\n"); 246 else 247 bus_setup_intr(dev, sc->mpic_res[3], INTR_TYPE_CLK, 248 mpic_intr, NULL, sc, &sc->intr_hand); 249 #endif 250 251 sc->mpic_bst = rman_get_bustag(sc->mpic_res[0]); 252 sc->mpic_bsh = rman_get_bushandle(sc->mpic_res[0]); 253 254 sc->cpu_bst = rman_get_bustag(sc->mpic_res[1]); 255 sc->cpu_bsh = rman_get_bushandle(sc->mpic_res[1]); 256 257 if (sc->mpic_res[2] != NULL) { 258 /* This is required only if MSIs are used. */ 259 sc->drbl_bst = rman_get_bustag(sc->mpic_res[2]); 260 sc->drbl_bsh = rman_get_bushandle(sc->mpic_res[2]); 261 } 262 263 bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh, 264 MPIC_CTRL, 1); 265 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_CTP, 0); 266 267 val = MPIC_READ(mv_mpic_sc, MPIC_CTRL); 268 sc->nirqs = MPIC_CTRL_NIRQS(val); 269 270 #ifdef INTRNG 271 if (mv_mpic_register_isrcs(sc) != 0) { 272 device_printf(dev, "could not register PIC ISRCs\n"); 273 bus_release_resources(dev, mv_mpic_spec, sc->mpic_res); 274 return (ENXIO); 275 } 276 if (intr_pic_register(dev, OF_xref_from_device(dev)) == NULL) { 277 device_printf(dev, "could not register PIC\n"); 278 bus_release_resources(dev, mv_mpic_spec, sc->mpic_res); 279 return (ENXIO); 280 } 281 #endif 282 283 mpic_unmask_msi(); 284 285 return (0); 286 } 287 288 #ifdef INTRNG 289 static int 290 mpic_intr(void *arg) 291 { 292 struct mv_mpic_softc *sc; 293 uint32_t cause, irqsrc; 294 unsigned int irq; 295 u_int cpuid; 296 297 sc = arg; 298 cpuid = PCPU_GET(cpuid); 299 irq = 0; 300 301 for (cause = MPIC_CPU_READ(sc, MPIC_PPI_CAUSE); cause > 0; 302 cause >>= 1, irq++) { 303 if (cause & 1) { 304 irqsrc = MPIC_READ(sc, MPIC_INT_CTL(irq)); 305 if ((irqsrc & MPIC_INT_IRQ_FIQ_MASK(cpuid)) == 0) 306 continue; 307 if (intr_isrc_dispatch(&sc->mpic_isrcs[irq].mmi_isrc, 308 curthread->td_intr_frame) != 0) { 309 mpic_mask_irq(irq); 310 device_printf(sc->sc_dev, "Stray irq %u " 311 "disabled\n", irq); 312 } 313 } 314 } 315 316 return (FILTER_HANDLED); 317 } 318 319 static void 320 mpic_disable_intr(device_t dev, struct intr_irqsrc *isrc) 321 { 322 u_int irq; 323 324 irq = ((struct mv_mpic_irqsrc *)isrc)->mmi_irq; 325 mpic_mask_irq(irq); 326 } 327 328 static void 329 mpic_enable_intr(device_t dev, struct intr_irqsrc *isrc) 330 { 331 u_int irq; 332 333 irq = ((struct mv_mpic_irqsrc *)isrc)->mmi_irq; 334 mpic_unmask_irq(irq); 335 } 336 337 static int 338 mpic_map_intr(device_t dev, struct intr_map_data *data, 339 struct intr_irqsrc **isrcp) 340 { 341 struct intr_map_data_fdt *daf; 342 struct mv_mpic_softc *sc; 343 344 if (data->type != INTR_MAP_DATA_FDT) 345 return (ENOTSUP); 346 347 sc = device_get_softc(dev); 348 daf = (struct intr_map_data_fdt *)data; 349 350 if (daf->ncells !=1 || daf->cells[0] >= sc->nirqs) 351 return (EINVAL); 352 353 *isrcp = &sc->mpic_isrcs[daf->cells[0]].mmi_isrc; 354 return (0); 355 } 356 357 static void 358 mpic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 359 { 360 361 mpic_disable_intr(dev, isrc); 362 } 363 364 static void 365 mpic_post_ithread(device_t dev, struct intr_irqsrc *isrc) 366 { 367 368 mpic_enable_intr(dev, isrc); 369 } 370 371 static void 372 mpic_post_filter(device_t dev, struct intr_irqsrc *isrc) 373 { 374 } 375 #endif 376 377 static device_method_t mv_mpic_methods[] = { 378 DEVMETHOD(device_probe, mv_mpic_probe), 379 DEVMETHOD(device_attach, mv_mpic_attach), 380 381 #ifdef INTRNG 382 DEVMETHOD(pic_disable_intr, mpic_disable_intr), 383 DEVMETHOD(pic_enable_intr, mpic_enable_intr), 384 DEVMETHOD(pic_map_intr, mpic_map_intr), 385 DEVMETHOD(pic_post_filter, mpic_post_filter), 386 DEVMETHOD(pic_post_ithread, mpic_post_ithread), 387 DEVMETHOD(pic_pre_ithread, mpic_pre_ithread), 388 #endif 389 { 0, 0 } 390 }; 391 392 static driver_t mv_mpic_driver = { 393 "mpic", 394 mv_mpic_methods, 395 sizeof(struct mv_mpic_softc), 396 }; 397 398 static devclass_t mv_mpic_devclass; 399 400 EARLY_DRIVER_MODULE(mpic, simplebus, mv_mpic_driver, mv_mpic_devclass, 0, 0, 401 BUS_PASS_INTERRUPT); 402 403 #ifndef INTRNG 404 int 405 arm_get_next_irq(int last) 406 { 407 u_int irq, next = -1; 408 409 irq = mv_mpic_get_cause() & MPIC_IRQ_MASK; 410 CTR2(KTR_INTR, "%s: irq:%#x", __func__, irq); 411 412 if (irq != MPIC_IRQ_MASK) { 413 if (irq == MPIC_INT_ERR) 414 irq = mv_mpic_get_cause_err(); 415 if (irq == MPIC_INT_MSI) 416 irq = mv_mpic_get_msi(); 417 next = irq; 418 } 419 420 CTR3(KTR_INTR, "%s: last=%d, next=%d", __func__, last, next); 421 return (next); 422 } 423 424 /* 425 * XXX We can make arm_enable_irq to operate on ICE and then mask/unmask only 426 * by ISM/ICM and remove access to ICE in masking operation 427 */ 428 void 429 arm_mask_irq(uintptr_t nb) 430 { 431 432 mpic_mask_irq(nb); 433 } 434 435 436 static void 437 arm_mask_irq_err(uintptr_t nb) 438 { 439 440 mpic_mask_irq_err(nb); 441 } 442 443 void 444 arm_unmask_irq(uintptr_t nb) 445 { 446 447 mpic_unmask_irq(nb); 448 } 449 450 void 451 arm_unmask_irq_err(uintptr_t nb) 452 { 453 454 mpic_unmask_irq_err(nb); 455 } 456 #endif 457 458 static void 459 mpic_unmask_msi(void) 460 { 461 462 mpic_unmask_irq(MPIC_INT_MSI); 463 } 464 465 static void 466 mpic_unmask_irq_err(uintptr_t nb) 467 { 468 uint32_t mask; 469 uint8_t bit_off; 470 471 bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh, 472 MPIC_ISE, MPIC_INT_ERR); 473 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, MPIC_INT_ERR); 474 475 bit_off = nb - ERR_IRQ; 476 mask = MPIC_CPU_READ(mv_mpic_sc, MPIC_ERR_MASK); 477 mask |= (1 << bit_off); 478 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ERR_MASK, mask); 479 } 480 481 static void 482 mpic_mask_irq_err(uintptr_t nb) 483 { 484 uint32_t mask; 485 uint8_t bit_off; 486 487 bit_off = nb - ERR_IRQ; 488 mask = MPIC_CPU_READ(mv_mpic_sc, MPIC_ERR_MASK); 489 mask &= ~(1 << bit_off); 490 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ERR_MASK, mask); 491 } 492 493 static void 494 mpic_unmask_irq(uintptr_t nb) 495 { 496 497 if (nb < ERR_IRQ) { 498 bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh, 499 MPIC_ISE, nb); 500 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, nb); 501 } else if (nb < MSI_IRQ) 502 mpic_unmask_irq_err(nb); 503 504 if (nb == 0) 505 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DRBL_MASK, 0xffffffff); 506 } 507 508 static void 509 mpic_mask_irq(uintptr_t nb) 510 { 511 512 if (nb < ERR_IRQ) { 513 bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh, 514 MPIC_ICE, nb); 515 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ISM, nb); 516 } else if (nb < MSI_IRQ) 517 mpic_mask_irq_err(nb); 518 } 519 520 uint32_t 521 mv_mpic_get_cause(void) 522 { 523 524 return (MPIC_CPU_READ(mv_mpic_sc, MPIC_IIACK)); 525 } 526 527 uint32_t 528 mv_mpic_get_cause_err(void) 529 { 530 uint32_t err_cause; 531 uint8_t bit_off; 532 533 err_cause = bus_space_read_4(mv_mpic_sc->mpic_bst, 534 mv_mpic_sc->mpic_bsh, MPIC_ERR_CAUSE); 535 536 if (err_cause) 537 bit_off = ffs(err_cause) - 1; 538 else 539 return (-1); 540 541 debugf("%s: irq:%x cause:%x\n", __func__, bit_off, err_cause); 542 return (ERR_IRQ + bit_off); 543 } 544 545 uint32_t 546 mv_mpic_get_msi(void) 547 { 548 uint32_t cause; 549 uint8_t bit_off; 550 551 KASSERT(mv_mpic_sc->drbl_bst != NULL, ("No doorbell in mv_mpic_get_msi")); 552 cause = MPIC_DRBL_READ(mv_mpic_sc, 0); 553 554 if (cause) 555 bit_off = ffs(cause) - 1; 556 else 557 return (-1); 558 559 debugf("%s: irq:%x cause:%x\n", __func__, bit_off, cause); 560 561 cause &= ~(1 << bit_off); 562 MPIC_DRBL_WRITE(mv_mpic_sc, 0, cause); 563 564 return (MSI_IRQ + bit_off); 565 } 566 567 int 568 mv_msi_data(int irq, uint64_t *addr, uint32_t *data) 569 { 570 u_long phys, base, size; 571 phandle_t node; 572 int error; 573 574 node = ofw_bus_get_node(mv_mpic_sc->sc_dev); 575 576 /* Get physical address of register space */ 577 error = fdt_get_range(OF_parent(node), 0, &phys, &size); 578 if (error) { 579 printf("%s: Cannot get register physical address, err:%d", 580 __func__, error); 581 return (error); 582 } 583 584 /* Get offset of MPIC register space */ 585 error = fdt_regsize(node, &base, &size); 586 if (error) { 587 printf("%s: Cannot get MPIC register offset, err:%d", 588 __func__, error); 589 return (error); 590 } 591 592 *addr = phys + base + MPIC_SOFT_INT; 593 *data = MPIC_SOFT_INT_DRBL1 | irq; 594 595 return (0); 596 } 597 598 599 #if defined(SMP) && defined(SOC_MV_ARMADAXP) 600 void 601 intr_pic_init_secondary(void) 602 { 603 } 604 605 void 606 pic_ipi_send(cpuset_t cpus, u_int ipi) 607 { 608 uint32_t val, i; 609 610 val = 0x00000000; 611 for (i = 0; i < MAXCPU; i++) 612 if (CPU_ISSET(i, &cpus)) 613 val |= (1 << (8 + i)); 614 val |= ipi; 615 bus_space_write_4(mv_mpic_sc->mpic_bst, mv_mpic_sc->mpic_bsh, 616 MPIC_SOFT_INT, val); 617 } 618 619 int 620 pic_ipi_read(int i __unused) 621 { 622 uint32_t val; 623 int ipi; 624 625 val = MPIC_CPU_READ(mv_mpic_sc, MPIC_IN_DRBL); 626 if (val) { 627 ipi = ffs(val) - 1; 628 MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DRBL, ~(1 << ipi)); 629 return (ipi); 630 } 631 632 return (0x3ff); 633 } 634 635 void 636 pic_ipi_clear(int ipi) 637 { 638 } 639 640 #endif
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