The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/mv/mv_machdep.c

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    1 /*-
    2  * Copyright (c) 1994-1998 Mark Brinicombe.
    3  * Copyright (c) 1994 Brini.
    4  * All rights reserved.
    5  *
    6  * This code is derived from software written for Brini by Mark Brinicombe
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  * 3. All advertising materials mentioning features or use of this software
   17  *    must display the following acknowledgement:
   18  *      This product includes software developed by Brini.
   19  * 4. The name of the company nor the name of the author may be used to
   20  *    endorse or promote products derived from this software without specific
   21  *    prior written permission.
   22  *
   23  * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
   24  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
   25  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   26  * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
   27  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
   28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
   29  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   30  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   31  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   32  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   33  * SUCH DAMAGE.
   34  *
   35  * from: FreeBSD: //depot/projects/arm/src/sys/arm/at91/kb920x_machdep.c, rev 45
   36  */
   37 
   38 #include "opt_ddb.h"
   39 #include "opt_platform.h"
   40 
   41 #include <sys/cdefs.h>
   42 __FBSDID("$FreeBSD: stable/10/sys/arm/mv/mv_machdep.c 266386 2014-05-18 00:32:35Z ian $");
   43 
   44 #define _ARM32_BUS_DMA_PRIVATE
   45 #include <sys/param.h>
   46 #include <sys/systm.h>
   47 #include <sys/bus.h>
   48 
   49 #include <vm/vm.h>
   50 #include <vm/pmap.h>
   51 
   52 #include <machine/bus.h>
   53 #include <machine/devmap.h>
   54 #include <machine/fdt.h>
   55 #include <machine/machdep.h>
   56 
   57 #include <arm/mv/mvreg.h>       /* XXX */
   58 #include <arm/mv/mvvar.h>       /* XXX eventually this should be eliminated */
   59 #include <arm/mv/mvwin.h>
   60 
   61 #include <dev/fdt/fdt_common.h>
   62 
   63 static int platform_mpp_init(void);
   64 #if defined(SOC_MV_ARMADAXP)
   65 void armadaxp_init_coher_fabric(void);
   66 void armadaxp_l2_init(void);
   67 #endif
   68 
   69 #define MPP_PIN_MAX             68
   70 #define MPP_PIN_CELLS           2
   71 #define MPP_PINS_PER_REG        8
   72 #define MPP_SEL(pin,func)       (((func) & 0xf) <<              \
   73     (((pin) % MPP_PINS_PER_REG) * 4))
   74 
   75 static int
   76 platform_mpp_init(void)
   77 {
   78         pcell_t pinmap[MPP_PIN_MAX * MPP_PIN_CELLS];
   79         int mpp[MPP_PIN_MAX];
   80         uint32_t ctrl_val, ctrl_offset;
   81         pcell_t reg[4];
   82         u_long start, size;
   83         phandle_t node;
   84         pcell_t pin_cells, *pinmap_ptr, pin_count;
   85         ssize_t len;
   86         int par_addr_cells, par_size_cells;
   87         int tuple_size, tuples, rv, pins, i, j;
   88         int mpp_pin, mpp_function;
   89 
   90         /*
   91          * Try to access the MPP node directly i.e. through /aliases/mpp.
   92          */
   93         if ((node = OF_finddevice("mpp")) != -1)
   94                 if (fdt_is_compatible(node, "mrvl,mpp"))
   95                         goto moveon;
   96         /*
   97          * Find the node the long way.
   98          */
   99         if ((node = OF_finddevice("/")) == -1)
  100                 return (ENXIO);
  101 
  102         if ((node = fdt_find_compatible(node, "simple-bus", 0)) == 0)
  103                 return (ENXIO);
  104 
  105         if ((node = fdt_find_compatible(node, "mrvl,mpp", 0)) == 0)
  106                 /*
  107                  * No MPP node. Fall back to how MPP got set by the
  108                  * first-stage loader and try to continue booting.
  109                  */
  110                 return (0);
  111 moveon:
  112         /*
  113          * Process 'reg' prop.
  114          */
  115         if ((rv = fdt_addrsize_cells(OF_parent(node), &par_addr_cells,
  116             &par_size_cells)) != 0)
  117                 return(ENXIO);
  118 
  119         tuple_size = sizeof(pcell_t) * (par_addr_cells + par_size_cells);
  120         len = OF_getprop(node, "reg", reg, sizeof(reg));
  121         tuples = len / tuple_size;
  122         if (tuple_size <= 0)
  123                 return (EINVAL);
  124 
  125         /*
  126          * Get address/size. XXX we assume only the first 'reg' tuple is used.
  127          */
  128         rv = fdt_data_to_res(reg, par_addr_cells, par_size_cells,
  129             &start, &size);
  130         if (rv != 0)
  131                 return (rv);
  132         start += fdt_immr_va;
  133 
  134         /*
  135          * Process 'pin-count' and 'pin-map' props.
  136          */
  137         if (OF_getprop(node, "pin-count", &pin_count, sizeof(pin_count)) <= 0)
  138                 return (ENXIO);
  139         pin_count = fdt32_to_cpu(pin_count);
  140         if (pin_count > MPP_PIN_MAX)
  141                 return (ERANGE);
  142 
  143         if (OF_getprop(node, "#pin-cells", &pin_cells, sizeof(pin_cells)) <= 0)
  144                 pin_cells = MPP_PIN_CELLS;
  145         pin_cells = fdt32_to_cpu(pin_cells);
  146         if (pin_cells > MPP_PIN_CELLS)
  147                 return (ERANGE);
  148         tuple_size = sizeof(pcell_t) * pin_cells;
  149 
  150         bzero(pinmap, sizeof(pinmap));
  151         len = OF_getprop(node, "pin-map", pinmap, sizeof(pinmap));
  152         if (len <= 0)
  153                 return (ERANGE);
  154         if (len % tuple_size)
  155                 return (ERANGE);
  156         pins = len / tuple_size;
  157         if (pins > pin_count)
  158                 return (ERANGE);
  159         /*
  160          * Fill out a "mpp[pin] => function" table. All pins unspecified in
  161          * the 'pin-map' property are defaulted to 0 function i.e. GPIO.
  162          */
  163         bzero(mpp, sizeof(mpp));
  164         pinmap_ptr = pinmap;
  165         for (i = 0; i < pins; i++) {
  166                 mpp_pin = fdt32_to_cpu(*pinmap_ptr);
  167                 mpp_function = fdt32_to_cpu(*(pinmap_ptr + 1));
  168                 mpp[mpp_pin] = mpp_function;
  169                 pinmap_ptr += pin_cells;
  170         }
  171 
  172         /*
  173          * Prepare and program MPP control register values.
  174          */
  175         ctrl_offset = 0;
  176         for (i = 0; i < pin_count;) {
  177                 ctrl_val = 0;
  178 
  179                 for (j = 0; j < MPP_PINS_PER_REG; j++) {
  180                         if (i + j == pin_count - 1)
  181                                 break;
  182                         ctrl_val |= MPP_SEL(i + j, mpp[i + j]);
  183                 }
  184                 i += MPP_PINS_PER_REG;
  185                 bus_space_write_4(fdtbus_bs_tag, start, ctrl_offset,
  186                     ctrl_val);
  187 
  188 #if defined(SOC_MV_ORION)
  189                 /*
  190                  * Third MPP reg on Orion SoC is placed
  191                  * non-linearly (with different offset).
  192                  */
  193                 if (i ==  (2 * MPP_PINS_PER_REG))
  194                         ctrl_offset = 0x50;
  195                 else
  196 #endif
  197                         ctrl_offset += 4;
  198         }
  199 
  200         return (0);
  201 }
  202 
  203 vm_offset_t
  204 initarm_lastaddr(void)
  205 {
  206 
  207         return (fdt_immr_va);
  208 }
  209 
  210 void
  211 initarm_early_init(void)
  212 {
  213 
  214         if (fdt_immr_addr(MV_BASE) != 0)
  215                 while (1);
  216 }
  217 
  218 void
  219 initarm_gpio_init(void)
  220 {
  221 
  222         /*
  223          * Re-initialise MPP. It is important to call this prior to using
  224          * console as the physical connection can be routed via MPP.
  225          */
  226         if (platform_mpp_init() != 0)
  227                 while (1);
  228 }
  229 
  230 void
  231 initarm_late_init(void)
  232 {
  233         /*
  234          * Re-initialise decode windows
  235          */
  236 #if !defined(SOC_MV_FREY)
  237         if (soc_decode_win() != 0)
  238                 printf("WARNING: could not re-initialise decode windows! "
  239                     "Running with existing settings...\n");
  240 #else
  241         /* Disable watchdog and timers */
  242         write_cpu_ctrl(CPU_TIMERS_BASE + CPU_TIMER_CONTROL, 0);
  243 #endif
  244 #if defined(SOC_MV_ARMADAXP)
  245 #if !defined(SMP)
  246         /* For SMP case it should be initialized after APs are booted */
  247         armadaxp_init_coher_fabric();
  248 #endif
  249         armadaxp_l2_init();
  250 #endif
  251 }
  252 
  253 #define FDT_DEVMAP_MAX  (MV_WIN_CPU_MAX + 2)
  254 static struct arm_devmap_entry fdt_devmap[FDT_DEVMAP_MAX] = {
  255         { 0, 0, 0, 0, 0, }
  256 };
  257 
  258 static int
  259 platform_sram_devmap(struct arm_devmap_entry *map)
  260 {
  261 #if !defined(SOC_MV_ARMADAXP)
  262         phandle_t child, root;
  263         u_long base, size;
  264         /*
  265          * SRAM range.
  266          */
  267         if ((child = OF_finddevice("/sram")) != 0)
  268                 if (fdt_is_compatible(child, "mrvl,cesa-sram") ||
  269                     fdt_is_compatible(child, "mrvl,scratchpad"))
  270                         goto moveon;
  271 
  272         if ((root = OF_finddevice("/")) == 0)
  273                 return (ENXIO);
  274 
  275         if ((child = fdt_find_compatible(root, "mrvl,cesa-sram", 0)) == 0 &&
  276             (child = fdt_find_compatible(root, "mrvl,scratchpad", 0)) == 0)
  277                         goto out;
  278 
  279 moveon:
  280         if (fdt_regsize(child, &base, &size) != 0)
  281                 return (EINVAL);
  282 
  283         map->pd_va = MV_CESA_SRAM_BASE; /* XXX */
  284         map->pd_pa = base;
  285         map->pd_size = size;
  286         map->pd_prot = VM_PROT_READ | VM_PROT_WRITE;
  287         map->pd_cache = PTE_DEVICE;
  288 
  289         return (0);
  290 out:
  291 #endif
  292         return (ENOENT);
  293 
  294 }
  295 
  296 /*
  297  * Supply a default do-nothing implementation of mv_pci_devmap() via a weak
  298  * alias.  Many Marvell platforms don't support a PCI interface, but to support
  299  * those that do, we end up with a reference to this function below, in
  300  * platform_devmap_init().  If "device pci" appears in the kernel config, the
  301  * real implementation of this function in arm/mv/mv_pci.c overrides the weak
  302  * alias defined here.
  303  */
  304 int mv_default_fdt_pci_devmap(phandle_t node, struct arm_devmap_entry *devmap,
  305     vm_offset_t io_va, vm_offset_t mem_va);
  306 int
  307 mv_default_fdt_pci_devmap(phandle_t node, struct arm_devmap_entry *devmap,
  308     vm_offset_t io_va, vm_offset_t mem_va)
  309 {
  310 
  311         return (0);
  312 }
  313 __weak_reference(mv_default_fdt_pci_devmap, mv_pci_devmap);
  314 
  315 /*
  316  * XXX: When device entry in devmap has pd_size smaller than section size,
  317  * system will freeze during initialization
  318  */
  319 
  320 /*
  321  * Construct pmap_devmap[] with DT-derived config data.
  322  */
  323 int
  324 initarm_devmap_init(void)
  325 {
  326         phandle_t root, child;
  327         pcell_t bank_count;
  328         int i, num_mapped;
  329 
  330         i = 0;
  331         arm_devmap_register_table(&fdt_devmap[0]);
  332 
  333 #ifdef SOC_MV_ARMADAXP
  334         vm_paddr_t cur_immr_pa;
  335 
  336         /*
  337          * Acquire SoC registers' base passed by u-boot and fill devmap
  338          * accordingly. DTB is going to be modified basing on this data
  339          * later.
  340          */
  341         __asm __volatile("mrc p15, 4, %0, c15, c0, 0" : "=r" (cur_immr_pa));
  342         cur_immr_pa = (cur_immr_pa << 13) & 0xff000000;
  343         if (cur_immr_pa != 0)
  344                 fdt_immr_pa = cur_immr_pa;
  345 #endif
  346         /*
  347          * IMMR range.
  348          */
  349         fdt_devmap[i].pd_va = fdt_immr_va;
  350         fdt_devmap[i].pd_pa = fdt_immr_pa;
  351         fdt_devmap[i].pd_size = fdt_immr_size;
  352         fdt_devmap[i].pd_prot = VM_PROT_READ | VM_PROT_WRITE;
  353         fdt_devmap[i].pd_cache = PTE_DEVICE;
  354         i++;
  355 
  356         /*
  357          * SRAM range.
  358          */
  359         if (i < FDT_DEVMAP_MAX)
  360                 if (platform_sram_devmap(&fdt_devmap[i]) == 0)
  361                         i++;
  362 
  363         /*
  364          * PCI range(s).
  365          * PCI range(s) and localbus.
  366          */
  367         if ((root = OF_finddevice("/")) == -1)
  368                 return (ENXIO);
  369         for (child = OF_child(root); child != 0; child = OF_peer(child)) {
  370                 if (fdt_is_type(child, "pci") || fdt_is_type(child, "pciep")) {
  371                         /*
  372                          * Check space: each PCI node will consume 2 devmap
  373                          * entries.
  374                          */
  375                         if (i + 1 >= FDT_DEVMAP_MAX)
  376                                 return (ENOMEM);
  377 
  378                         /*
  379                          * XXX this should account for PCI and multiple ranges
  380                          * of a given kind.
  381                          */
  382                         if (mv_pci_devmap(child, &fdt_devmap[i], MV_PCI_VA_IO_BASE,
  383                                     MV_PCI_VA_MEM_BASE) != 0)
  384                                 return (ENXIO);
  385                         i += 2;
  386                 }
  387 
  388                 if (fdt_is_compatible(child, "mrvl,lbc")) {
  389                         /* Check available space */
  390                         if (OF_getprop(child, "bank-count", (void *)&bank_count,
  391                             sizeof(bank_count)) <= 0)
  392                                 /* If no property, use default value */
  393                                 bank_count = 1;
  394                         else
  395                                 bank_count = fdt32_to_cpu(bank_count);
  396 
  397                         if ((i + bank_count) >= FDT_DEVMAP_MAX)
  398                                 return (ENOMEM);
  399 
  400                         /* Add all localbus ranges to device map */
  401                         num_mapped = 0;
  402 
  403                         if (fdt_localbus_devmap(child, &fdt_devmap[i],
  404                             (int)bank_count, &num_mapped) != 0)
  405                                 return (ENXIO);
  406 
  407                         i += num_mapped;
  408                 }
  409         }
  410 
  411         return (0);
  412 }
  413 
  414 struct arm32_dma_range *
  415 bus_dma_get_range(void)
  416 {
  417 
  418         return (NULL);
  419 }
  420 
  421 int
  422 bus_dma_get_range_nb(void)
  423 {
  424 
  425         return (0);
  426 }
  427 
  428 #if defined(CPU_MV_PJ4B)
  429 #ifdef DDB
  430 #include <ddb/ddb.h>
  431 
  432 DB_SHOW_COMMAND(cp15, db_show_cp15)
  433 {
  434         u_int reg;
  435 
  436         __asm __volatile("mrc p15, 0, %0, c0, c0, 0" : "=r" (reg));
  437         db_printf("Cpu ID: 0x%08x\n", reg);
  438         __asm __volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (reg));
  439         db_printf("Current Cache Lvl ID: 0x%08x\n",reg);
  440 
  441         __asm __volatile("mrc p15, 0, %0, c1, c0, 0" : "=r" (reg));
  442         db_printf("Ctrl: 0x%08x\n",reg);
  443         __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (reg));
  444         db_printf("Aux Ctrl: 0x%08x\n",reg);
  445 
  446         __asm __volatile("mrc p15, 0, %0, c0, c1, 0" : "=r" (reg));
  447         db_printf("Processor Feat 0: 0x%08x\n", reg);
  448         __asm __volatile("mrc p15, 0, %0, c0, c1, 1" : "=r" (reg));
  449         db_printf("Processor Feat 1: 0x%08x\n", reg);
  450         __asm __volatile("mrc p15, 0, %0, c0, c1, 2" : "=r" (reg));
  451         db_printf("Debug Feat 0: 0x%08x\n", reg);
  452         __asm __volatile("mrc p15, 0, %0, c0, c1, 3" : "=r" (reg));
  453         db_printf("Auxiliary Feat 0: 0x%08x\n", reg);
  454         __asm __volatile("mrc p15, 0, %0, c0, c1, 4" : "=r" (reg));
  455         db_printf("Memory Model Feat 0: 0x%08x\n", reg);
  456         __asm __volatile("mrc p15, 0, %0, c0, c1, 5" : "=r" (reg));
  457         db_printf("Memory Model Feat 1: 0x%08x\n", reg);
  458         __asm __volatile("mrc p15, 0, %0, c0, c1, 6" : "=r" (reg));
  459         db_printf("Memory Model Feat 2: 0x%08x\n", reg);
  460         __asm __volatile("mrc p15, 0, %0, c0, c1, 7" : "=r" (reg));
  461         db_printf("Memory Model Feat 3: 0x%08x\n", reg);
  462 
  463         __asm __volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (reg));
  464         db_printf("Aux Func Modes Ctrl 0: 0x%08x\n",reg);
  465         __asm __volatile("mrc p15, 1, %0, c15, c2, 1" : "=r" (reg));
  466         db_printf("Aux Func Modes Ctrl 1: 0x%08x\n",reg);
  467 
  468         __asm __volatile("mrc p15, 1, %0, c15, c12, 0" : "=r" (reg));
  469         db_printf("CPU ID code extension: 0x%08x\n",reg);
  470 }
  471 
  472 DB_SHOW_COMMAND(vtop, db_show_vtop)
  473 {
  474         u_int reg;
  475 
  476         if (have_addr) {
  477                 __asm __volatile("mcr p15, 0, %0, c7, c8, 0" : : "r" (addr));
  478                 __asm __volatile("mrc p15, 0, %0, c7, c4, 0" : "=r" (reg));
  479                 db_printf("Physical address reg: 0x%08x\n",reg);
  480         } else
  481                 db_printf("show vtop <virt_addr>\n");
  482 }
  483 #endif /* DDB */
  484 #endif /* CPU_MV_PJ4B */
  485 

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