mv_machdep.c

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    1 /*-
    2  * Copyright (c) 1994-1998 Mark Brinicombe.
    3  * Copyright (c) 1994 Brini.
    4  * All rights reserved.
    5  *
    6  * This code is derived from software written for Brini by Mark Brinicombe
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  * 3. All advertising materials mentioning features or use of this software
   17  *    must display the following acknowledgement:
   18  *      This product includes software developed by Brini.
   19  * 4. The name of the company nor the name of the author may be used to
   20  *    endorse or promote products derived from this software without specific
   21  *    prior written permission.
   22  *
   23  * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
   24  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
   25  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   26  * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
   27  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
   28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
   29  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   30  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   31  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   32  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   33  * SUCH DAMAGE.
   34  *
   35  * from: FreeBSD: //depot/projects/arm/src/sys/arm/at91/kb920x_machdep.c, rev 45
   36  */
   37 
   38 #include "opt_ddb.h"
   39 #include "opt_platform.h"
   40 
   41 #include <sys/cdefs.h>
   42 __FBSDID("$FreeBSD: releng/11.0/sys/arm/mv/mv_machdep.c 301220 2016-06-02 18:31:36Z zbb $");
   43 
   44 #define _ARM32_BUS_DMA_PRIVATE
   45 #include <sys/param.h>
   46 #include <sys/systm.h>
   47 #include <sys/bus.h>
   48 #include <sys/devmap.h>
   49 
   50 #include <vm/vm.h>
   51 #include <vm/pmap.h>
   52 
   53 #include <machine/bus.h>
   54 #include <machine/fdt.h>
   55 #include <machine/machdep.h>
   56 #include <machine/platform.h> 
   57 
   58 #if __ARM_ARCH < 6
   59 #include <machine/cpu-v4.h>
   60 #else
   61 #include <machine/cpu-v6.h>
   62 #endif
   63 
   64 #include <arm/mv/mvreg.h>       /* XXX */
   65 #include <arm/mv/mvvar.h>       /* XXX eventually this should be eliminated */
   66 #include <arm/mv/mvwin.h>
   67 
   68 #include <dev/fdt/fdt_common.h>
   69 
   70 static int platform_mpp_init(void);
   71 #if defined(SOC_MV_ARMADAXP)
   72 void armadaxp_init_coher_fabric(void);
   73 void armadaxp_l2_init(void);
   74 #endif
   75 #if defined(SOC_MV_ARMADA38X)
   76 int armada38x_win_set_iosync_barrier(void);
   77 int armada38x_scu_enable(void);
   78 int armada38x_open_bootrom_win(void);
   79 #endif
   80 
   81 #define MPP_PIN_MAX             68
   82 #define MPP_PIN_CELLS           2
   83 #define MPP_PINS_PER_REG        8
   84 #define MPP_SEL(pin,func)       (((func) & 0xf) <<              \
   85     (((pin) % MPP_PINS_PER_REG) * 4))
   86 
   87 static int
   88 platform_mpp_init(void)
   89 {
   90         pcell_t pinmap[MPP_PIN_MAX * MPP_PIN_CELLS];
   91         int mpp[MPP_PIN_MAX];
   92         uint32_t ctrl_val, ctrl_offset;
   93         pcell_t reg[4];
   94         u_long start, size;
   95         phandle_t node;
   96         pcell_t pin_cells, *pinmap_ptr, pin_count;
   97         ssize_t len;
   98         int par_addr_cells, par_size_cells;
   99         int tuple_size, tuples, rv, pins, i, j;
  100         int mpp_pin, mpp_function;
  101 
  102         /*
  103          * Try to access the MPP node directly i.e. through /aliases/mpp.
  104          */
  105         if ((node = OF_finddevice("mpp")) != -1)
  106                 if (fdt_is_compatible(node, "mrvl,mpp"))
  107                         goto moveon;
  108         /*
  109          * Find the node the long way.
  110          */
  111         if ((node = OF_finddevice("/")) == -1)
  112                 return (ENXIO);
  113 
  114         if ((node = fdt_find_compatible(node, "simple-bus", 0)) == 0)
  115                 return (ENXIO);
  116 
  117         if ((node = fdt_find_compatible(node, "mrvl,mpp", 0)) == 0)
  118                 /*
  119                  * No MPP node. Fall back to how MPP got set by the
  120                  * first-stage loader and try to continue booting.
  121                  */
  122                 return (0);
  123 moveon:
  124         /*
  125          * Process 'reg' prop.
  126          */
  127         if ((rv = fdt_addrsize_cells(OF_parent(node), &par_addr_cells,
  128             &par_size_cells)) != 0)
  129                 return(ENXIO);
  130 
  131         tuple_size = sizeof(pcell_t) * (par_addr_cells + par_size_cells);
  132         len = OF_getprop(node, "reg", reg, sizeof(reg));
  133         tuples = len / tuple_size;
  134         if (tuple_size <= 0)
  135                 return (EINVAL);
  136 
  137         /*
  138          * Get address/size. XXX we assume only the first 'reg' tuple is used.
  139          */
  140         rv = fdt_data_to_res(reg, par_addr_cells, par_size_cells,
  141             &start, &size);
  142         if (rv != 0)
  143                 return (rv);
  144         start += fdt_immr_va;
  145 
  146         /*
  147          * Process 'pin-count' and 'pin-map' props.
  148          */
  149         if (OF_getprop(node, "pin-count", &pin_count, sizeof(pin_count)) <= 0)
  150                 return (ENXIO);
  151         pin_count = fdt32_to_cpu(pin_count);
  152         if (pin_count > MPP_PIN_MAX)
  153                 return (ERANGE);
  154 
  155         if (OF_getprop(node, "#pin-cells", &pin_cells, sizeof(pin_cells)) <= 0)
  156                 pin_cells = MPP_PIN_CELLS;
  157         pin_cells = fdt32_to_cpu(pin_cells);
  158         if (pin_cells > MPP_PIN_CELLS)
  159                 return (ERANGE);
  160         tuple_size = sizeof(pcell_t) * pin_cells;
  161 
  162         bzero(pinmap, sizeof(pinmap));
  163         len = OF_getprop(node, "pin-map", pinmap, sizeof(pinmap));
  164         if (len <= 0)
  165                 return (ERANGE);
  166         if (len % tuple_size)
  167                 return (ERANGE);
  168         pins = len / tuple_size;
  169         if (pins > pin_count)
  170                 return (ERANGE);
  171         /*
  172          * Fill out a "mpp[pin] => function" table. All pins unspecified in
  173          * the 'pin-map' property are defaulted to 0 function i.e. GPIO.
  174          */
  175         bzero(mpp, sizeof(mpp));
  176         pinmap_ptr = pinmap;
  177         for (i = 0; i < pins; i++) {
  178                 mpp_pin = fdt32_to_cpu(*pinmap_ptr);
  179                 mpp_function = fdt32_to_cpu(*(pinmap_ptr + 1));
  180                 mpp[mpp_pin] = mpp_function;
  181                 pinmap_ptr += pin_cells;
  182         }
  183 
  184         /*
  185          * Prepare and program MPP control register values.
  186          */
  187         ctrl_offset = 0;
  188         for (i = 0; i < pin_count;) {
  189                 ctrl_val = 0;
  190 
  191                 for (j = 0; j < MPP_PINS_PER_REG; j++) {
  192                         if (i + j == pin_count - 1)
  193                                 break;
  194                         ctrl_val |= MPP_SEL(i + j, mpp[i + j]);
  195                 }
  196                 i += MPP_PINS_PER_REG;
  197                 bus_space_write_4(fdtbus_bs_tag, start, ctrl_offset,
  198                     ctrl_val);
  199 
  200 #if defined(SOC_MV_ORION)
  201                 /*
  202                  * Third MPP reg on Orion SoC is placed
  203                  * non-linearly (with different offset).
  204                  */
  205                 if (i ==  (2 * MPP_PINS_PER_REG))
  206                         ctrl_offset = 0x50;
  207                 else
  208 #endif
  209                         ctrl_offset += 4;
  210         }
  211 
  212         return (0);
  213 }
  214 
  215 vm_offset_t
  216 platform_lastaddr(void)
  217 {
  218 
  219         return (fdt_immr_va);
  220 }
  221 
  222 void
  223 platform_probe_and_attach(void)
  224 {
  225 
  226         if (fdt_immr_addr(MV_BASE) != 0)
  227                 while (1);
  228 }
  229 
  230 void
  231 platform_gpio_init(void)
  232 {
  233 
  234         /*
  235          * Re-initialise MPP. It is important to call this prior to using
  236          * console as the physical connection can be routed via MPP.
  237          */
  238         if (platform_mpp_init() != 0)
  239                 while (1);
  240 }
  241 
  242 void
  243 platform_late_init(void)
  244 {
  245         /*
  246          * Re-initialise decode windows
  247          */
  248 #if !defined(SOC_MV_FREY)
  249         if (soc_decode_win() != 0)
  250                 printf("WARNING: could not re-initialise decode windows! "
  251                     "Running with existing settings...\n");
  252 #else
  253         /* Disable watchdog and timers */
  254         write_cpu_ctrl(CPU_TIMERS_BASE + CPU_TIMER_CONTROL, 0);
  255 #endif
  256 #if defined(SOC_MV_ARMADAXP)
  257 #if !defined(SMP)
  258         /* For SMP case it should be initialized after APs are booted */
  259         armadaxp_init_coher_fabric();
  260 #endif
  261         armadaxp_l2_init();
  262 #endif
  263 
  264 #if defined(SOC_MV_ARMADA38X)
  265         /* Set IO Sync Barrier bit for all Mbus devices */
  266         if (armada38x_win_set_iosync_barrier() != 0)
  267                 printf("WARNING: could not map CPU Subsystem registers\n");
  268         if (armada38x_scu_enable() != 0)
  269                 printf("WARNING: could not enable SCU\n");
  270 #ifdef SMP
  271         /* Open window to bootROM memory - needed for SMP */
  272         if (armada38x_open_bootrom_win() != 0)
  273                 printf("WARNING: could not open window to bootROM\n");
  274 #endif
  275 #endif
  276 }
  277 
  278 #define FDT_DEVMAP_MAX  (MV_WIN_CPU_MAX + 2)
  279 static struct devmap_entry fdt_devmap[FDT_DEVMAP_MAX] = {
  280         { 0, 0, 0, }
  281 };
  282 
  283 static int
  284 platform_sram_devmap(struct devmap_entry *map)
  285 {
  286 #if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
  287         phandle_t child, root;
  288         u_long base, size;
  289         /*
  290          * SRAM range.
  291          */
  292         if ((child = OF_finddevice("/sram")) != 0)
  293                 if (fdt_is_compatible(child, "mrvl,cesa-sram") ||
  294                     fdt_is_compatible(child, "mrvl,scratchpad"))
  295                         goto moveon;
  296 
  297         if ((root = OF_finddevice("/")) == 0)
  298                 return (ENXIO);
  299 
  300         if ((child = fdt_find_compatible(root, "mrvl,cesa-sram", 0)) == 0 &&
  301             (child = fdt_find_compatible(root, "mrvl,scratchpad", 0)) == 0)
  302                         goto out;
  303 
  304 moveon:
  305         if (fdt_regsize(child, &base, &size) != 0)
  306                 return (EINVAL);
  307 
  308         map->pd_va = MV_CESA_SRAM_BASE; /* XXX */
  309         map->pd_pa = base;
  310         map->pd_size = size;
  311 
  312         return (0);
  313 out:
  314 #endif
  315         return (ENOENT);
  316 
  317 }
  318 
  319 /*
  320  * Supply a default do-nothing implementation of mv_pci_devmap() via a weak
  321  * alias.  Many Marvell platforms don't support a PCI interface, but to support
  322  * those that do, we end up with a reference to this function below, in
  323  * platform_devmap_init().  If "device pci" appears in the kernel config, the
  324  * real implementation of this function in arm/mv/mv_pci.c overrides the weak
  325  * alias defined here.
  326  */
  327 int mv_default_fdt_pci_devmap(phandle_t node, struct devmap_entry *devmap,
  328     vm_offset_t io_va, vm_offset_t mem_va);
  329 int
  330 mv_default_fdt_pci_devmap(phandle_t node, struct devmap_entry *devmap,
  331     vm_offset_t io_va, vm_offset_t mem_va)
  332 {
  333 
  334         return (0);
  335 }
  336 __weak_reference(mv_default_fdt_pci_devmap, mv_pci_devmap);
  337 
  338 /*
  339  * XXX: When device entry in devmap has pd_size smaller than section size,
  340  * system will freeze during initialization
  341  */
  342 
  343 /*
  344  * Construct devmap table with DT-derived config data.
  345  */
  346 int
  347 platform_devmap_init(void)
  348 {
  349         phandle_t root, child;
  350         pcell_t bank_count;
  351         int i, num_mapped;
  352 
  353         i = 0;
  354         devmap_register_table(&fdt_devmap[0]);
  355 
  356 #ifdef SOC_MV_ARMADAXP
  357         vm_paddr_t cur_immr_pa;
  358 
  359         /*
  360          * Acquire SoC registers' base passed by u-boot and fill devmap
  361          * accordingly. DTB is going to be modified basing on this data
  362          * later.
  363          */
  364         __asm __volatile("mrc p15, 4, %0, c15, c0, 0" : "=r" (cur_immr_pa));
  365         cur_immr_pa = (cur_immr_pa << 13) & 0xff000000;
  366         if (cur_immr_pa != 0)
  367                 fdt_immr_pa = cur_immr_pa;
  368 #endif
  369         /*
  370          * IMMR range.
  371          */
  372         fdt_devmap[i].pd_va = fdt_immr_va;
  373         fdt_devmap[i].pd_pa = fdt_immr_pa;
  374         fdt_devmap[i].pd_size = fdt_immr_size;
  375         i++;
  376 
  377         /*
  378          * SRAM range.
  379          */
  380         if (i < FDT_DEVMAP_MAX)
  381                 if (platform_sram_devmap(&fdt_devmap[i]) == 0)
  382                         i++;
  383 
  384         /*
  385          * PCI range(s).
  386          * PCI range(s) and localbus.
  387          */
  388         if ((root = OF_finddevice("/")) == -1)
  389                 return (ENXIO);
  390         for (child = OF_child(root); child != 0; child = OF_peer(child)) {
  391                 if (fdt_is_type(child, "pci") || fdt_is_type(child, "pciep")) {
  392                         /*
  393                          * Check space: each PCI node will consume 2 devmap
  394                          * entries.
  395                          */
  396                         if (i + 1 >= FDT_DEVMAP_MAX)
  397                                 return (ENOMEM);
  398 
  399                         /*
  400                          * XXX this should account for PCI and multiple ranges
  401                          * of a given kind.
  402                          */
  403                         if (mv_pci_devmap(child, &fdt_devmap[i], MV_PCI_VA_IO_BASE,
  404                                     MV_PCI_VA_MEM_BASE) != 0)
  405                                 return (ENXIO);
  406                         i += 2;
  407                 }
  408 
  409                 if (fdt_is_compatible(child, "mrvl,lbc")) {
  410                         /* Check available space */
  411                         if (OF_getprop(child, "bank-count", (void *)&bank_count,
  412                             sizeof(bank_count)) <= 0)
  413                                 /* If no property, use default value */
  414                                 bank_count = 1;
  415                         else
  416                                 bank_count = fdt32_to_cpu(bank_count);
  417 
  418                         if ((i + bank_count) >= FDT_DEVMAP_MAX)
  419                                 return (ENOMEM);
  420 
  421                         /* Add all localbus ranges to device map */
  422                         num_mapped = 0;
  423 
  424                         if (fdt_localbus_devmap(child, &fdt_devmap[i],
  425                             (int)bank_count, &num_mapped) != 0)
  426                                 return (ENXIO);
  427 
  428                         i += num_mapped;
  429                 }
  430         }
  431 
  432         return (0);
  433 }
  434 
  435 struct arm32_dma_range *
  436 bus_dma_get_range(void)
  437 {
  438 
  439         return (NULL);
  440 }
  441 
  442 int
  443 bus_dma_get_range_nb(void)
  444 {
  445 
  446         return (0);
  447 }
  448 
  449 #if defined(CPU_MV_PJ4B)
  450 #ifdef DDB
  451 #include <ddb/ddb.h>
  452 
  453 DB_SHOW_COMMAND(cp15, db_show_cp15)
  454 {
  455         u_int reg;
  456 
  457         __asm __volatile("mrc p15, 0, %0, c0, c0, 0" : "=r" (reg));
  458         db_printf("Cpu ID: 0x%08x\n", reg);
  459         __asm __volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (reg));
  460         db_printf("Current Cache Lvl ID: 0x%08x\n",reg);
  461 
  462         reg = cp15_sctlr_get();
  463         db_printf("Ctrl: 0x%08x\n",reg);
  464         reg = cp15_actlr_get();
  465         db_printf("Aux Ctrl: 0x%08x\n",reg);
  466 
  467         __asm __volatile("mrc p15, 0, %0, c0, c1, 0" : "=r" (reg));
  468         db_printf("Processor Feat 0: 0x%08x\n", reg);
  469         __asm __volatile("mrc p15, 0, %0, c0, c1, 1" : "=r" (reg));
  470         db_printf("Processor Feat 1: 0x%08x\n", reg);
  471         __asm __volatile("mrc p15, 0, %0, c0, c1, 2" : "=r" (reg));
  472         db_printf("Debug Feat 0: 0x%08x\n", reg);
  473         __asm __volatile("mrc p15, 0, %0, c0, c1, 3" : "=r" (reg));
  474         db_printf("Auxiliary Feat 0: 0x%08x\n", reg);
  475         __asm __volatile("mrc p15, 0, %0, c0, c1, 4" : "=r" (reg));
  476         db_printf("Memory Model Feat 0: 0x%08x\n", reg);
  477         __asm __volatile("mrc p15, 0, %0, c0, c1, 5" : "=r" (reg));
  478         db_printf("Memory Model Feat 1: 0x%08x\n", reg);
  479         __asm __volatile("mrc p15, 0, %0, c0, c1, 6" : "=r" (reg));
  480         db_printf("Memory Model Feat 2: 0x%08x\n", reg);
  481         __asm __volatile("mrc p15, 0, %0, c0, c1, 7" : "=r" (reg));
  482         db_printf("Memory Model Feat 3: 0x%08x\n", reg);
  483 
  484         __asm __volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (reg));
  485         db_printf("Aux Func Modes Ctrl 0: 0x%08x\n",reg);
  486         __asm __volatile("mrc p15, 1, %0, c15, c2, 1" : "=r" (reg));
  487         db_printf("Aux Func Modes Ctrl 1: 0x%08x\n",reg);
  488 
  489         __asm __volatile("mrc p15, 1, %0, c15, c12, 0" : "=r" (reg));
  490         db_printf("CPU ID code extension: 0x%08x\n",reg);
  491 }
  492 
  493 DB_SHOW_COMMAND(vtop, db_show_vtop)
  494 {
  495         u_int reg;
  496 
  497         if (have_addr) {
  498                 __asm __volatile("mcr p15, 0, %0, c7, c8, 0" : : "r" (addr));
  499                 __asm __volatile("mrc p15, 0, %0, c7, c4, 0" : "=r" (reg));
  500                 db_printf("Physical address reg: 0x%08x\n",reg);
  501         } else
  502                 db_printf("show vtop <virt_addr>\n");
  503 }
  504 #endif /* DDB */
  505 #endif /* CPU_MV_PJ4B */
  506
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FreeBSD/Linux Kernel Cross Reference sys/arm/mv/mv_machdep.c

FreeBSD/Linux Kernel Cross Reference
sys/arm/mv/mv_machdep.c
