The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/arm/mv/mv_machdep.c

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    1 /*-
    2  * Copyright (c) 1994-1998 Mark Brinicombe.
    3  * Copyright (c) 1994 Brini.
    4  * All rights reserved.
    5  *
    6  * This code is derived from software written for Brini by Mark Brinicombe
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  * 3. All advertising materials mentioning features or use of this software
   17  *    must display the following acknowledgement:
   18  *      This product includes software developed by Brini.
   19  * 4. The name of the company nor the name of the author may be used to
   20  *    endorse or promote products derived from this software without specific
   21  *    prior written permission.
   22  *
   23  * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
   24  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
   25  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   26  * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
   27  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
   28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
   29  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   30  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   31  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   32  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   33  * SUCH DAMAGE.
   34  *
   35  * from: FreeBSD: //depot/projects/arm/src/sys/arm/at91/kb920x_machdep.c, rev 45
   36  */
   37 
   38 #include "opt_ddb.h"
   39 #include "opt_platform.h"
   40 
   41 #include <sys/cdefs.h>
   42 __FBSDID("$FreeBSD: releng/11.1/sys/arm/mv/mv_machdep.c 314506 2017-03-01 19:55:04Z ian $");
   43 
   44 #define _ARM32_BUS_DMA_PRIVATE
   45 #include <sys/param.h>
   46 #include <sys/systm.h>
   47 #include <sys/bus.h>
   48 #include <sys/devmap.h>
   49 
   50 #include <vm/vm.h>
   51 #include <vm/pmap.h>
   52 
   53 #include <machine/bus.h>
   54 #include <machine/fdt.h>
   55 #include <machine/machdep.h>
   56 #include <machine/platform.h> 
   57 
   58 #if __ARM_ARCH < 6
   59 #include <machine/cpu-v4.h>
   60 #else
   61 #include <machine/cpu-v6.h>
   62 #endif
   63 
   64 #include <arm/mv/mvreg.h>       /* XXX */
   65 #include <arm/mv/mvvar.h>       /* XXX eventually this should be eliminated */
   66 #include <arm/mv/mvwin.h>
   67 
   68 #include <dev/fdt/fdt_common.h>
   69 
   70 static int platform_mpp_init(void);
   71 #if defined(SOC_MV_ARMADAXP)
   72 void armadaxp_init_coher_fabric(void);
   73 void armadaxp_l2_init(void);
   74 #endif
   75 #if defined(SOC_MV_ARMADA38X)
   76 int armada38x_win_set_iosync_barrier(void);
   77 int armada38x_scu_enable(void);
   78 int armada38x_open_bootrom_win(void);
   79 #endif
   80 
   81 #define MPP_PIN_MAX             68
   82 #define MPP_PIN_CELLS           2
   83 #define MPP_PINS_PER_REG        8
   84 #define MPP_SEL(pin,func)       (((func) & 0xf) <<              \
   85     (((pin) % MPP_PINS_PER_REG) * 4))
   86 
   87 static int
   88 platform_mpp_init(void)
   89 {
   90         pcell_t pinmap[MPP_PIN_MAX * MPP_PIN_CELLS];
   91         int mpp[MPP_PIN_MAX];
   92         uint32_t ctrl_val, ctrl_offset;
   93         pcell_t reg[4];
   94         u_long start, size;
   95         phandle_t node;
   96         pcell_t pin_cells, *pinmap_ptr, pin_count;
   97         ssize_t len;
   98         int par_addr_cells, par_size_cells;
   99         int tuple_size, tuples, rv, pins, i, j;
  100         int mpp_pin, mpp_function;
  101 
  102         /*
  103          * Try to access the MPP node directly i.e. through /aliases/mpp.
  104          */
  105         if ((node = OF_finddevice("mpp")) != -1)
  106                 if (fdt_is_compatible(node, "mrvl,mpp"))
  107                         goto moveon;
  108         /*
  109          * Find the node the long way.
  110          */
  111         if ((node = OF_finddevice("/")) == -1)
  112                 return (ENXIO);
  113 
  114         if ((node = fdt_find_compatible(node, "simple-bus", 0)) == 0)
  115                 return (ENXIO);
  116 
  117         if ((node = fdt_find_compatible(node, "mrvl,mpp", 0)) == 0)
  118                 /*
  119                  * No MPP node. Fall back to how MPP got set by the
  120                  * first-stage loader and try to continue booting.
  121                  */
  122                 return (0);
  123 moveon:
  124         /*
  125          * Process 'reg' prop.
  126          */
  127         if ((rv = fdt_addrsize_cells(OF_parent(node), &par_addr_cells,
  128             &par_size_cells)) != 0)
  129                 return(ENXIO);
  130 
  131         tuple_size = sizeof(pcell_t) * (par_addr_cells + par_size_cells);
  132         len = OF_getprop(node, "reg", reg, sizeof(reg));
  133         tuples = len / tuple_size;
  134         if (tuple_size <= 0)
  135                 return (EINVAL);
  136 
  137         /*
  138          * Get address/size. XXX we assume only the first 'reg' tuple is used.
  139          */
  140         rv = fdt_data_to_res(reg, par_addr_cells, par_size_cells,
  141             &start, &size);
  142         if (rv != 0)
  143                 return (rv);
  144         start += fdt_immr_va;
  145 
  146         /*
  147          * Process 'pin-count' and 'pin-map' props.
  148          */
  149         if (OF_getencprop(node, "pin-count", &pin_count, sizeof(pin_count)) <= 0)
  150                 return (ENXIO);
  151         if (pin_count > MPP_PIN_MAX)
  152                 return (ERANGE);
  153 
  154         if (OF_getencprop(node, "#pin-cells", &pin_cells, sizeof(pin_cells)) <= 0)
  155                 pin_cells = MPP_PIN_CELLS;
  156         if (pin_cells > MPP_PIN_CELLS)
  157                 return (ERANGE);
  158         tuple_size = sizeof(pcell_t) * pin_cells;
  159 
  160         bzero(pinmap, sizeof(pinmap));
  161         len = OF_getencprop(node, "pin-map", pinmap, sizeof(pinmap));
  162         if (len <= 0)
  163                 return (ERANGE);
  164         if (len % tuple_size)
  165                 return (ERANGE);
  166         pins = len / tuple_size;
  167         if (pins > pin_count)
  168                 return (ERANGE);
  169         /*
  170          * Fill out a "mpp[pin] => function" table. All pins unspecified in
  171          * the 'pin-map' property are defaulted to 0 function i.e. GPIO.
  172          */
  173         bzero(mpp, sizeof(mpp));
  174         pinmap_ptr = pinmap;
  175         for (i = 0; i < pins; i++) {
  176                 mpp_pin = *pinmap_ptr;
  177                 mpp_function = *(pinmap_ptr + 1);
  178                 mpp[mpp_pin] = mpp_function;
  179                 pinmap_ptr += pin_cells;
  180         }
  181 
  182         /*
  183          * Prepare and program MPP control register values.
  184          */
  185         ctrl_offset = 0;
  186         for (i = 0; i < pin_count;) {
  187                 ctrl_val = 0;
  188 
  189                 for (j = 0; j < MPP_PINS_PER_REG; j++) {
  190                         if (i + j == pin_count - 1)
  191                                 break;
  192                         ctrl_val |= MPP_SEL(i + j, mpp[i + j]);
  193                 }
  194                 i += MPP_PINS_PER_REG;
  195                 bus_space_write_4(fdtbus_bs_tag, start, ctrl_offset,
  196                     ctrl_val);
  197 
  198 #if defined(SOC_MV_ORION)
  199                 /*
  200                  * Third MPP reg on Orion SoC is placed
  201                  * non-linearly (with different offset).
  202                  */
  203                 if (i ==  (2 * MPP_PINS_PER_REG))
  204                         ctrl_offset = 0x50;
  205                 else
  206 #endif
  207                         ctrl_offset += 4;
  208         }
  209 
  210         return (0);
  211 }
  212 
  213 vm_offset_t
  214 platform_lastaddr(void)
  215 {
  216 
  217         return (fdt_immr_va);
  218 }
  219 
  220 void
  221 platform_probe_and_attach(void)
  222 {
  223 
  224         if (fdt_immr_addr(MV_BASE) != 0)
  225                 while (1);
  226 }
  227 
  228 void
  229 platform_gpio_init(void)
  230 {
  231 
  232         /*
  233          * Re-initialise MPP. It is important to call this prior to using
  234          * console as the physical connection can be routed via MPP.
  235          */
  236         if (platform_mpp_init() != 0)
  237                 while (1);
  238 }
  239 
  240 void
  241 platform_late_init(void)
  242 {
  243         /*
  244          * Re-initialise decode windows
  245          */
  246 #if !defined(SOC_MV_FREY)
  247         if (soc_decode_win() != 0)
  248                 printf("WARNING: could not re-initialise decode windows! "
  249                     "Running with existing settings...\n");
  250 #else
  251         /* Disable watchdog and timers */
  252         write_cpu_ctrl(CPU_TIMERS_BASE + CPU_TIMER_CONTROL, 0);
  253 #endif
  254 #if defined(SOC_MV_ARMADAXP)
  255 #if !defined(SMP)
  256         /* For SMP case it should be initialized after APs are booted */
  257         armadaxp_init_coher_fabric();
  258 #endif
  259         armadaxp_l2_init();
  260 #endif
  261 
  262 #if defined(SOC_MV_ARMADA38X)
  263         /* Set IO Sync Barrier bit for all Mbus devices */
  264         if (armada38x_win_set_iosync_barrier() != 0)
  265                 printf("WARNING: could not map CPU Subsystem registers\n");
  266         if (armada38x_scu_enable() != 0)
  267                 printf("WARNING: could not enable SCU\n");
  268 #ifdef SMP
  269         /* Open window to bootROM memory - needed for SMP */
  270         if (armada38x_open_bootrom_win() != 0)
  271                 printf("WARNING: could not open window to bootROM\n");
  272 #endif
  273 #endif
  274 }
  275 
  276 #define FDT_DEVMAP_MAX  (MV_WIN_CPU_MAX + 2)
  277 static struct devmap_entry fdt_devmap[FDT_DEVMAP_MAX] = {
  278         { 0, 0, 0, }
  279 };
  280 
  281 static int
  282 platform_sram_devmap(struct devmap_entry *map)
  283 {
  284 #if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X)
  285         phandle_t child, root;
  286         u_long base, size;
  287         /*
  288          * SRAM range.
  289          */
  290         if ((child = OF_finddevice("/sram")) != 0)
  291                 if (fdt_is_compatible(child, "mrvl,cesa-sram") ||
  292                     fdt_is_compatible(child, "mrvl,scratchpad"))
  293                         goto moveon;
  294 
  295         if ((root = OF_finddevice("/")) == 0)
  296                 return (ENXIO);
  297 
  298         if ((child = fdt_find_compatible(root, "mrvl,cesa-sram", 0)) == 0 &&
  299             (child = fdt_find_compatible(root, "mrvl,scratchpad", 0)) == 0)
  300                         goto out;
  301 
  302 moveon:
  303         if (fdt_regsize(child, &base, &size) != 0)
  304                 return (EINVAL);
  305 
  306         map->pd_va = MV_CESA_SRAM_BASE; /* XXX */
  307         map->pd_pa = base;
  308         map->pd_size = size;
  309 
  310         return (0);
  311 out:
  312 #endif
  313         return (ENOENT);
  314 
  315 }
  316 
  317 /*
  318  * Supply a default do-nothing implementation of mv_pci_devmap() via a weak
  319  * alias.  Many Marvell platforms don't support a PCI interface, but to support
  320  * those that do, we end up with a reference to this function below, in
  321  * platform_devmap_init().  If "device pci" appears in the kernel config, the
  322  * real implementation of this function in arm/mv/mv_pci.c overrides the weak
  323  * alias defined here.
  324  */
  325 int mv_default_fdt_pci_devmap(phandle_t node, struct devmap_entry *devmap,
  326     vm_offset_t io_va, vm_offset_t mem_va);
  327 int
  328 mv_default_fdt_pci_devmap(phandle_t node, struct devmap_entry *devmap,
  329     vm_offset_t io_va, vm_offset_t mem_va)
  330 {
  331 
  332         return (0);
  333 }
  334 __weak_reference(mv_default_fdt_pci_devmap, mv_pci_devmap);
  335 
  336 /*
  337  * XXX: When device entry in devmap has pd_size smaller than section size,
  338  * system will freeze during initialization
  339  */
  340 
  341 /*
  342  * Construct devmap table with DT-derived config data.
  343  */
  344 int
  345 platform_devmap_init(void)
  346 {
  347         phandle_t root, child;
  348         pcell_t bank_count;
  349         int i, num_mapped;
  350 
  351         i = 0;
  352         devmap_register_table(&fdt_devmap[0]);
  353 
  354 #ifdef SOC_MV_ARMADAXP
  355         vm_paddr_t cur_immr_pa;
  356 
  357         /*
  358          * Acquire SoC registers' base passed by u-boot and fill devmap
  359          * accordingly. DTB is going to be modified basing on this data
  360          * later.
  361          */
  362         __asm __volatile("mrc p15, 4, %0, c15, c0, 0" : "=r" (cur_immr_pa));
  363         cur_immr_pa = (cur_immr_pa << 13) & 0xff000000;
  364         if (cur_immr_pa != 0)
  365                 fdt_immr_pa = cur_immr_pa;
  366 #endif
  367         /*
  368          * IMMR range.
  369          */
  370         fdt_devmap[i].pd_va = fdt_immr_va;
  371         fdt_devmap[i].pd_pa = fdt_immr_pa;
  372         fdt_devmap[i].pd_size = fdt_immr_size;
  373         i++;
  374 
  375         /*
  376          * SRAM range.
  377          */
  378         if (i < FDT_DEVMAP_MAX)
  379                 if (platform_sram_devmap(&fdt_devmap[i]) == 0)
  380                         i++;
  381 
  382         /*
  383          * PCI range(s).
  384          * PCI range(s) and localbus.
  385          */
  386         if ((root = OF_finddevice("/")) == -1)
  387                 return (ENXIO);
  388         for (child = OF_child(root); child != 0; child = OF_peer(child)) {
  389                 if (fdt_is_type(child, "pci") || fdt_is_type(child, "pciep")) {
  390                         /*
  391                          * Check space: each PCI node will consume 2 devmap
  392                          * entries.
  393                          */
  394                         if (i + 1 >= FDT_DEVMAP_MAX)
  395                                 return (ENOMEM);
  396 
  397                         /*
  398                          * XXX this should account for PCI and multiple ranges
  399                          * of a given kind.
  400                          */
  401                         if (mv_pci_devmap(child, &fdt_devmap[i], MV_PCI_VA_IO_BASE,
  402                                     MV_PCI_VA_MEM_BASE) != 0)
  403                                 return (ENXIO);
  404                         i += 2;
  405                 }
  406 
  407                 if (fdt_is_compatible(child, "mrvl,lbc")) {
  408                         /* Check available space */
  409                         if (OF_getencprop(child, "bank-count", &bank_count,
  410                             sizeof(bank_count)) <= 0)
  411                                 /* If no property, use default value */
  412                                 bank_count = 1;
  413 
  414                         if ((i + bank_count) >= FDT_DEVMAP_MAX)
  415                                 return (ENOMEM);
  416 
  417                         /* Add all localbus ranges to device map */
  418                         num_mapped = 0;
  419 
  420                         if (fdt_localbus_devmap(child, &fdt_devmap[i],
  421                             (int)bank_count, &num_mapped) != 0)
  422                                 return (ENXIO);
  423 
  424                         i += num_mapped;
  425                 }
  426         }
  427 
  428         return (0);
  429 }
  430 
  431 #if __ARM_ARCH < 6
  432 struct arm32_dma_range *
  433 bus_dma_get_range(void)
  434 {
  435 
  436         return (NULL);
  437 }
  438 
  439 int
  440 bus_dma_get_range_nb(void)
  441 {
  442 
  443         return (0);
  444 }
  445 #endif
  446 
  447 #if defined(CPU_MV_PJ4B)
  448 #ifdef DDB
  449 #include <ddb/ddb.h>
  450 
  451 DB_SHOW_COMMAND(cp15, db_show_cp15)
  452 {
  453         u_int reg;
  454 
  455         __asm __volatile("mrc p15, 0, %0, c0, c0, 0" : "=r" (reg));
  456         db_printf("Cpu ID: 0x%08x\n", reg);
  457         __asm __volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (reg));
  458         db_printf("Current Cache Lvl ID: 0x%08x\n",reg);
  459 
  460         reg = cp15_sctlr_get();
  461         db_printf("Ctrl: 0x%08x\n",reg);
  462         reg = cp15_actlr_get();
  463         db_printf("Aux Ctrl: 0x%08x\n",reg);
  464 
  465         __asm __volatile("mrc p15, 0, %0, c0, c1, 0" : "=r" (reg));
  466         db_printf("Processor Feat 0: 0x%08x\n", reg);
  467         __asm __volatile("mrc p15, 0, %0, c0, c1, 1" : "=r" (reg));
  468         db_printf("Processor Feat 1: 0x%08x\n", reg);
  469         __asm __volatile("mrc p15, 0, %0, c0, c1, 2" : "=r" (reg));
  470         db_printf("Debug Feat 0: 0x%08x\n", reg);
  471         __asm __volatile("mrc p15, 0, %0, c0, c1, 3" : "=r" (reg));
  472         db_printf("Auxiliary Feat 0: 0x%08x\n", reg);
  473         __asm __volatile("mrc p15, 0, %0, c0, c1, 4" : "=r" (reg));
  474         db_printf("Memory Model Feat 0: 0x%08x\n", reg);
  475         __asm __volatile("mrc p15, 0, %0, c0, c1, 5" : "=r" (reg));
  476         db_printf("Memory Model Feat 1: 0x%08x\n", reg);
  477         __asm __volatile("mrc p15, 0, %0, c0, c1, 6" : "=r" (reg));
  478         db_printf("Memory Model Feat 2: 0x%08x\n", reg);
  479         __asm __volatile("mrc p15, 0, %0, c0, c1, 7" : "=r" (reg));
  480         db_printf("Memory Model Feat 3: 0x%08x\n", reg);
  481 
  482         __asm __volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (reg));
  483         db_printf("Aux Func Modes Ctrl 0: 0x%08x\n",reg);
  484         __asm __volatile("mrc p15, 1, %0, c15, c2, 1" : "=r" (reg));
  485         db_printf("Aux Func Modes Ctrl 1: 0x%08x\n",reg);
  486 
  487         __asm __volatile("mrc p15, 1, %0, c15, c12, 0" : "=r" (reg));
  488         db_printf("CPU ID code extension: 0x%08x\n",reg);
  489 }
  490 
  491 DB_SHOW_COMMAND(vtop, db_show_vtop)
  492 {
  493         u_int reg;
  494 
  495         if (have_addr) {
  496                 __asm __volatile("mcr p15, 0, %0, c7, c8, 0" : : "r" (addr));
  497                 __asm __volatile("mrc p15, 0, %0, c7, c4, 0" : "=r" (reg));
  498                 db_printf("Physical address reg: 0x%08x\n",reg);
  499         } else
  500                 db_printf("show vtop <virt_addr>\n");
  501 }
  502 #endif /* DDB */
  503 #endif /* CPU_MV_PJ4B */
  504 

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