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sys/arm/mv/mv_pci.c
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1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2008 MARVELL INTERNATIONAL LTD. 5 * Copyright (c) 2010 The FreeBSD Foundation 6 * Copyright (c) 2010-2015 Semihalf 7 * All rights reserved. 8 * 9 * Developed by Semihalf. 10 * 11 * Portions of this software were developed by Semihalf 12 * under sponsorship from the FreeBSD Foundation. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 3. Neither the name of MARVELL nor the names of contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 */ 38 39 /* 40 * Marvell integrated PCI/PCI-Express controller driver. 41 */ 42 43 #include <sys/cdefs.h> 44 __FBSDID("$FreeBSD$"); 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/lock.h> 50 #include <sys/malloc.h> 51 #include <sys/module.h> 52 #include <sys/mutex.h> 53 #include <sys/queue.h> 54 #include <sys/bus.h> 55 #include <sys/rman.h> 56 #include <sys/endian.h> 57 #include <sys/devmap.h> 58 59 #include <machine/fdt.h> 60 #include <machine/intr.h> 61 62 #include <vm/vm.h> 63 #include <vm/pmap.h> 64 65 #include <dev/fdt/fdt_common.h> 66 #include <dev/ofw/ofw_bus.h> 67 #include <dev/ofw/ofw_bus_subr.h> 68 #include <dev/ofw/ofw_pci.h> 69 #include <dev/pci/pcivar.h> 70 #include <dev/pci/pcireg.h> 71 #include <dev/pci/pcib_private.h> 72 73 #include "ofw_bus_if.h" 74 #include "pcib_if.h" 75 76 #include <machine/resource.h> 77 #include <machine/bus.h> 78 79 #include <arm/mv/mvreg.h> 80 #include <arm/mv/mvvar.h> 81 #include <arm/mv/mvwin.h> 82 83 #ifdef DEBUG 84 #define debugf(fmt, args...) do { printf(fmt,##args); } while (0) 85 #else 86 #define debugf(fmt, args...) 87 #endif 88 89 /* 90 * Code and data related to fdt-based PCI configuration. 91 * 92 * This stuff used to be in dev/fdt/fdt_pci.c and fdt_common.h, but it was 93 * always Marvell-specific so that was deleted and the code now lives here. 94 */ 95 96 struct mv_pci_range { 97 u_long base_pci; 98 u_long base_parent; 99 u_long len; 100 }; 101 102 #define FDT_RANGES_CELLS ((3 + 3 + 2) * 2) 103 #define PCI_SPACE_LEN 0x00400000 104 105 static void 106 mv_pci_range_dump(struct mv_pci_range *range) 107 { 108 #ifdef DEBUG 109 printf("\n"); 110 printf(" base_pci = 0x%08lx\n", range->base_pci); 111 printf(" base_par = 0x%08lx\n", range->base_parent); 112 printf(" len = 0x%08lx\n", range->len); 113 #endif 114 } 115 116 static int 117 mv_pci_ranges_decode(phandle_t node, struct mv_pci_range *io_space, 118 struct mv_pci_range *mem_space) 119 { 120 pcell_t ranges[FDT_RANGES_CELLS]; 121 struct mv_pci_range *pci_space; 122 pcell_t addr_cells, size_cells, par_addr_cells; 123 pcell_t *rangesptr; 124 pcell_t cell0, cell2; 125 int tuple_size, tuples, i, rv, offset_cells, len; 126 int portid, is_io_space; 127 128 /* 129 * Retrieve 'ranges' property. 130 */ 131 if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0) 132 return (EINVAL); 133 if (addr_cells != 3 || size_cells != 2) 134 return (ERANGE); 135 136 par_addr_cells = fdt_parent_addr_cells(node); 137 if (par_addr_cells > 3) 138 return (ERANGE); 139 140 len = OF_getproplen(node, "ranges"); 141 if (len > sizeof(ranges)) 142 return (ENOMEM); 143 144 if (OF_getprop(node, "ranges", ranges, sizeof(ranges)) <= 0) 145 return (EINVAL); 146 147 tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells + 148 size_cells); 149 tuples = len / tuple_size; 150 151 /* 152 * Initialize the ranges so that we don't have to worry about 153 * having them all defined in the FDT. In particular, it is 154 * perfectly fine not to want I/O space on PCI buses. 155 */ 156 bzero(io_space, sizeof(*io_space)); 157 bzero(mem_space, sizeof(*mem_space)); 158 159 rangesptr = &ranges[0]; 160 offset_cells = 0; 161 for (i = 0; i < tuples; i++) { 162 cell0 = fdt_data_get((void *)rangesptr, 1); 163 rangesptr++; 164 /* cell1 */ 165 rangesptr++; 166 cell2 = fdt_data_get((void *)rangesptr, 1); 167 rangesptr++; 168 portid = fdt_data_get((void *)(rangesptr+1), 1); 169 170 if (cell0 & 0x02000000) { 171 pci_space = mem_space; 172 is_io_space = 0; 173 } else if (cell0 & 0x01000000) { 174 pci_space = io_space; 175 is_io_space = 1; 176 } else { 177 rv = ERANGE; 178 goto out; 179 } 180 181 if (par_addr_cells == 3) { 182 /* 183 * This is a PCI subnode 'ranges'. Skip cell0 and 184 * cell1 of this entry and only use cell2. 185 */ 186 offset_cells = 2; 187 rangesptr += offset_cells; 188 } 189 190 if ((par_addr_cells - offset_cells) > 2) { 191 rv = ERANGE; 192 goto out; 193 } 194 pci_space->base_parent = fdt_data_get((void *)rangesptr, 195 par_addr_cells - offset_cells); 196 rangesptr += par_addr_cells - offset_cells; 197 198 if (size_cells > 2) { 199 rv = ERANGE; 200 goto out; 201 } 202 pci_space->len = fdt_data_get((void *)rangesptr, size_cells); 203 rangesptr += size_cells; 204 205 pci_space->base_pci = cell2; 206 207 if (pci_space->len == 0) { 208 pci_space->len = PCI_SPACE_LEN; 209 pci_space->base_parent = fdt_immr_va + 210 PCI_SPACE_LEN * ( 2 * portid + is_io_space); 211 } 212 } 213 rv = 0; 214 out: 215 return (rv); 216 } 217 218 static int 219 mv_pci_ranges(phandle_t node, struct mv_pci_range *io_space, 220 struct mv_pci_range *mem_space) 221 { 222 int err; 223 224 debugf("Processing PCI node: %x\n", node); 225 if ((err = mv_pci_ranges_decode(node, io_space, mem_space)) != 0) { 226 debugf("could not decode parent PCI node 'ranges'\n"); 227 return (err); 228 } 229 230 debugf("Post fixup dump:\n"); 231 mv_pci_range_dump(io_space); 232 mv_pci_range_dump(mem_space); 233 return (0); 234 } 235 236 int 237 mv_pci_devmap(phandle_t node, struct devmap_entry *devmap, vm_offset_t io_va, 238 vm_offset_t mem_va) 239 { 240 struct mv_pci_range io_space, mem_space; 241 int error; 242 243 if ((error = mv_pci_ranges_decode(node, &io_space, &mem_space)) != 0) 244 return (error); 245 246 devmap->pd_va = (io_va ? io_va : io_space.base_parent); 247 devmap->pd_pa = io_space.base_parent; 248 devmap->pd_size = io_space.len; 249 devmap++; 250 251 devmap->pd_va = (mem_va ? mem_va : mem_space.base_parent); 252 devmap->pd_pa = mem_space.base_parent; 253 devmap->pd_size = mem_space.len; 254 return (0); 255 } 256 257 /* 258 * Code and data related to the Marvell pcib driver. 259 */ 260 261 #define PCI_CFG_ENA (1U << 31) 262 #define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16) 263 #define PCI_CFG_DEV(dev) (((dev) & 0x1f) << 11) 264 #define PCI_CFG_FUN(fun) (((fun) & 0x7) << 8) 265 #define PCI_CFG_PCIE_REG(reg) ((reg) & 0xfc) 266 267 #define PCI_REG_CFG_ADDR 0x0C78 268 #define PCI_REG_CFG_DATA 0x0C7C 269 270 #define PCIE_REG_CFG_ADDR 0x18F8 271 #define PCIE_REG_CFG_DATA 0x18FC 272 #define PCIE_REG_CONTROL 0x1A00 273 #define PCIE_CTRL_LINK1X 0x00000001 274 #define PCIE_REG_STATUS 0x1A04 275 #define PCIE_REG_IRQ_MASK 0x1910 276 277 #define PCIE_CONTROL_ROOT_CMPLX (1 << 1) 278 #define PCIE_CONTROL_HOT_RESET (1 << 24) 279 280 #define PCIE_LINK_TIMEOUT 1000000 281 282 #define PCIE_STATUS_LINK_DOWN 1 283 #define PCIE_STATUS_DEV_OFFS 16 284 285 /* Minimum PCI Memory and I/O allocations taken from PCI spec (in bytes) */ 286 #define PCI_MIN_IO_ALLOC 4 287 #define PCI_MIN_MEM_ALLOC 16 288 289 #define BITS_PER_UINT32 (NBBY * sizeof(uint32_t)) 290 291 struct mv_pcib_softc { 292 device_t sc_dev; 293 294 struct rman sc_mem_rman; 295 bus_addr_t sc_mem_base; 296 bus_addr_t sc_mem_size; 297 uint32_t sc_mem_map[MV_PCI_MEM_SLICE_SIZE / 298 (PCI_MIN_MEM_ALLOC * BITS_PER_UINT32)]; 299 int sc_win_target; 300 int sc_mem_win_attr; 301 302 struct rman sc_io_rman; 303 bus_addr_t sc_io_base; 304 bus_addr_t sc_io_size; 305 uint32_t sc_io_map[MV_PCI_IO_SLICE_SIZE / 306 (PCI_MIN_IO_ALLOC * BITS_PER_UINT32)]; 307 int sc_io_win_attr; 308 309 struct resource *sc_res; 310 bus_space_handle_t sc_bsh; 311 bus_space_tag_t sc_bst; 312 int sc_rid; 313 314 struct mtx sc_msi_mtx; 315 uint32_t sc_msi_bitmap; 316 317 int sc_busnr; /* Host bridge bus number */ 318 int sc_devnr; /* Host bridge device number */ 319 int sc_type; 320 int sc_mode; /* Endpoint / Root Complex */ 321 322 int sc_msi_supported; 323 int sc_skip_enable_procedure; 324 int sc_enable_find_root_slot; 325 struct ofw_bus_iinfo sc_pci_iinfo; 326 327 int ap_segment; /* PCI domain */ 328 }; 329 330 /* Local forward prototypes */ 331 static int mv_pcib_decode_win(phandle_t, struct mv_pcib_softc *); 332 static void mv_pcib_hw_cfginit(void); 333 static uint32_t mv_pcib_hw_cfgread(struct mv_pcib_softc *, u_int, u_int, 334 u_int, u_int, int); 335 static void mv_pcib_hw_cfgwrite(struct mv_pcib_softc *, u_int, u_int, 336 u_int, u_int, uint32_t, int); 337 static int mv_pcib_init(struct mv_pcib_softc *, int, int); 338 static int mv_pcib_init_all_bars(struct mv_pcib_softc *, int, int, int, int); 339 static void mv_pcib_init_bridge(struct mv_pcib_softc *, int, int, int); 340 static inline void pcib_write_irq_mask(struct mv_pcib_softc *, uint32_t); 341 static void mv_pcib_enable(struct mv_pcib_softc *, uint32_t); 342 static int mv_pcib_mem_init(struct mv_pcib_softc *); 343 344 /* Forward prototypes */ 345 static int mv_pcib_probe(device_t); 346 static int mv_pcib_attach(device_t); 347 348 static struct resource *mv_pcib_alloc_resource(device_t, device_t, int, int *, 349 rman_res_t, rman_res_t, rman_res_t, u_int); 350 static int mv_pcib_release_resource(device_t, device_t, int, int, 351 struct resource *); 352 static int mv_pcib_read_ivar(device_t, device_t, int, uintptr_t *); 353 static int mv_pcib_write_ivar(device_t, device_t, int, uintptr_t); 354 355 static int mv_pcib_maxslots(device_t); 356 static uint32_t mv_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int); 357 static void mv_pcib_write_config(device_t, u_int, u_int, u_int, u_int, 358 uint32_t, int); 359 static int mv_pcib_route_interrupt(device_t, device_t, int); 360 361 static int mv_pcib_alloc_msi(device_t, device_t, int, int, int *); 362 static int mv_pcib_map_msi(device_t, device_t, int, uint64_t *, uint32_t *); 363 static int mv_pcib_release_msi(device_t, device_t, int, int *); 364 365 /* 366 * Bus interface definitions. 367 */ 368 static device_method_t mv_pcib_methods[] = { 369 /* Device interface */ 370 DEVMETHOD(device_probe, mv_pcib_probe), 371 DEVMETHOD(device_attach, mv_pcib_attach), 372 373 /* Bus interface */ 374 DEVMETHOD(bus_read_ivar, mv_pcib_read_ivar), 375 DEVMETHOD(bus_write_ivar, mv_pcib_write_ivar), 376 DEVMETHOD(bus_alloc_resource, mv_pcib_alloc_resource), 377 DEVMETHOD(bus_release_resource, mv_pcib_release_resource), 378 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 379 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 380 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 381 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 382 383 /* pcib interface */ 384 DEVMETHOD(pcib_maxslots, mv_pcib_maxslots), 385 DEVMETHOD(pcib_read_config, mv_pcib_read_config), 386 DEVMETHOD(pcib_write_config, mv_pcib_write_config), 387 DEVMETHOD(pcib_route_interrupt, mv_pcib_route_interrupt), 388 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow), 389 390 DEVMETHOD(pcib_alloc_msi, mv_pcib_alloc_msi), 391 DEVMETHOD(pcib_release_msi, mv_pcib_release_msi), 392 DEVMETHOD(pcib_map_msi, mv_pcib_map_msi), 393 394 /* OFW bus interface */ 395 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 396 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 397 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 398 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 399 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 400 401 DEVMETHOD_END 402 }; 403 404 static driver_t mv_pcib_driver = { 405 "pcib", 406 mv_pcib_methods, 407 sizeof(struct mv_pcib_softc), 408 }; 409 410 DRIVER_MODULE(mv_pcib, ofwbus, mv_pcib_driver, 0, 0); 411 DRIVER_MODULE(mv_pcib, pcib_ctrl, mv_pcib_driver, 0, 0); 412 413 static struct mtx pcicfg_mtx; 414 415 static int 416 mv_pcib_probe(device_t self) 417 { 418 phandle_t node; 419 420 node = ofw_bus_get_node(self); 421 if (!mv_fdt_is_type(node, "pci")) 422 return (ENXIO); 423 424 if (!(ofw_bus_is_compatible(self, "mrvl,pcie") || 425 ofw_bus_is_compatible(self, "mrvl,pci") || 426 ofw_bus_node_is_compatible( 427 OF_parent(node), "marvell,armada-370-pcie"))) 428 return (ENXIO); 429 430 if (!ofw_bus_status_okay(self)) 431 return (ENXIO); 432 433 device_set_desc(self, "Marvell Integrated PCI/PCI-E Controller"); 434 return (BUS_PROBE_DEFAULT); 435 } 436 437 static int 438 mv_pcib_attach(device_t self) 439 { 440 struct mv_pcib_softc *sc; 441 phandle_t node, parnode; 442 uint32_t val, reg0; 443 int err, bus, devfn, port_id; 444 445 sc = device_get_softc(self); 446 sc->sc_dev = self; 447 448 node = ofw_bus_get_node(self); 449 parnode = OF_parent(node); 450 451 if (OF_getencprop(node, "marvell,pcie-port", &(port_id), 452 sizeof(port_id)) <= 0) { 453 /* If port ID does not exist in the FDT set value to 0 */ 454 if (!OF_hasprop(node, "marvell,pcie-port")) 455 port_id = 0; 456 else 457 return(ENXIO); 458 } 459 460 sc->ap_segment = port_id; 461 462 if (ofw_bus_node_is_compatible(node, "mrvl,pcie")) { 463 sc->sc_type = MV_TYPE_PCIE; 464 sc->sc_win_target = MV_WIN_PCIE_TARGET(port_id); 465 sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR(port_id); 466 sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR(port_id); 467 sc->sc_skip_enable_procedure = 1; 468 } else if (ofw_bus_node_is_compatible(parnode, "marvell,armada-370-pcie")) { 469 sc->sc_type = MV_TYPE_PCIE; 470 sc->sc_win_target = MV_WIN_PCIE_TARGET_ARMADA38X(port_id); 471 sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR_ARMADA38X(port_id); 472 sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR_ARMADA38X(port_id); 473 sc->sc_enable_find_root_slot = 1; 474 } else if (ofw_bus_node_is_compatible(node, "mrvl,pci")) { 475 sc->sc_type = MV_TYPE_PCI; 476 sc->sc_win_target = MV_WIN_PCI_TARGET; 477 sc->sc_mem_win_attr = MV_WIN_PCI_MEM_ATTR; 478 sc->sc_io_win_attr = MV_WIN_PCI_IO_ATTR; 479 } else 480 return (ENXIO); 481 482 /* 483 * Retrieve our mem-mapped registers range. 484 */ 485 sc->sc_rid = 0; 486 sc->sc_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &sc->sc_rid, 487 RF_ACTIVE); 488 if (sc->sc_res == NULL) { 489 device_printf(self, "could not map memory\n"); 490 return (ENXIO); 491 } 492 sc->sc_bst = rman_get_bustag(sc->sc_res); 493 sc->sc_bsh = rman_get_bushandle(sc->sc_res); 494 495 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_CONTROL); 496 sc->sc_mode = (val & PCIE_CONTROL_ROOT_CMPLX ? MV_MODE_ROOT : 497 MV_MODE_ENDPOINT); 498 499 /* 500 * Get PCI interrupt info. 501 */ 502 if (sc->sc_mode == MV_MODE_ROOT) 503 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(pcell_t)); 504 505 /* 506 * Configure decode windows for PCI(E) access. 507 */ 508 if (mv_pcib_decode_win(node, sc) != 0) 509 return (ENXIO); 510 511 mv_pcib_hw_cfginit(); 512 513 /* 514 * Enable PCIE device. 515 */ 516 mv_pcib_enable(sc, port_id); 517 518 /* 519 * Memory management. 520 */ 521 err = mv_pcib_mem_init(sc); 522 if (err) 523 return (err); 524 525 /* 526 * Preliminary bus enumeration to find first linked devices and set 527 * appropriate bus number from which should start the actual enumeration 528 */ 529 for (bus = 0; bus < PCI_BUSMAX; bus++) { 530 for (devfn = 0; devfn < mv_pcib_maxslots(self); devfn++) { 531 reg0 = mv_pcib_read_config(self, bus, devfn, devfn & 0x7, 0x0, 4); 532 if (reg0 == (~0U)) 533 continue; /* no device */ 534 else { 535 sc->sc_busnr = bus; /* update bus number */ 536 break; 537 } 538 } 539 } 540 541 if (sc->sc_mode == MV_MODE_ROOT) { 542 err = mv_pcib_init(sc, sc->sc_busnr, 543 mv_pcib_maxslots(sc->sc_dev)); 544 if (err) 545 goto error; 546 547 device_add_child(self, "pci", -1); 548 } else { 549 sc->sc_devnr = 1; 550 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 551 PCIE_REG_STATUS, 1 << PCIE_STATUS_DEV_OFFS); 552 device_add_child(self, "pci_ep", -1); 553 } 554 555 mtx_init(&sc->sc_msi_mtx, "msi_mtx", NULL, MTX_DEF); 556 return (bus_generic_attach(self)); 557 558 error: 559 /* XXX SYS_RES_ should be released here */ 560 rman_fini(&sc->sc_mem_rman); 561 rman_fini(&sc->sc_io_rman); 562 563 return (err); 564 } 565 566 static void 567 mv_pcib_enable(struct mv_pcib_softc *sc, uint32_t unit) 568 { 569 uint32_t val; 570 int timeout; 571 572 if (sc->sc_skip_enable_procedure) 573 goto pcib_enable_root_mode; 574 575 /* 576 * Check if PCIE device is enabled. 577 */ 578 if ((sc->sc_skip_enable_procedure == 0) && 579 (read_cpu_ctrl(CPU_CONTROL) & CPU_CONTROL_PCIE_DISABLE(unit))) { 580 write_cpu_ctrl(CPU_CONTROL, read_cpu_ctrl(CPU_CONTROL) & 581 ~(CPU_CONTROL_PCIE_DISABLE(unit))); 582 583 timeout = PCIE_LINK_TIMEOUT; 584 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 585 PCIE_REG_STATUS); 586 while (((val & PCIE_STATUS_LINK_DOWN) == 1) && (timeout > 0)) { 587 DELAY(1000); 588 timeout -= 1000; 589 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, 590 PCIE_REG_STATUS); 591 } 592 } 593 594 pcib_enable_root_mode: 595 if (sc->sc_mode == MV_MODE_ROOT) { 596 /* 597 * Enable PCI bridge. 598 */ 599 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND); 600 val |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | 601 PCIM_CMD_MEMEN | PCIM_CMD_PORTEN; 602 bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND, val); 603 } 604 } 605 606 static int 607 mv_pcib_mem_init(struct mv_pcib_softc *sc) 608 { 609 int err; 610 611 /* 612 * Memory management. 613 */ 614 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 615 err = rman_init(&sc->sc_mem_rman); 616 if (err) 617 return (err); 618 619 sc->sc_io_rman.rm_type = RMAN_ARRAY; 620 err = rman_init(&sc->sc_io_rman); 621 if (err) { 622 rman_fini(&sc->sc_mem_rman); 623 return (err); 624 } 625 626 err = rman_manage_region(&sc->sc_mem_rman, sc->sc_mem_base, 627 sc->sc_mem_base + sc->sc_mem_size - 1); 628 if (err) 629 goto error; 630 631 err = rman_manage_region(&sc->sc_io_rman, sc->sc_io_base, 632 sc->sc_io_base + sc->sc_io_size - 1); 633 if (err) 634 goto error; 635 636 return (0); 637 638 error: 639 rman_fini(&sc->sc_mem_rman); 640 rman_fini(&sc->sc_io_rman); 641 642 return (err); 643 } 644 645 static inline uint32_t 646 pcib_bit_get(uint32_t *map, uint32_t bit) 647 { 648 uint32_t n = bit / BITS_PER_UINT32; 649 650 bit = bit % BITS_PER_UINT32; 651 return (map[n] & (1 << bit)); 652 } 653 654 static inline void 655 pcib_bit_set(uint32_t *map, uint32_t bit) 656 { 657 uint32_t n = bit / BITS_PER_UINT32; 658 659 bit = bit % BITS_PER_UINT32; 660 map[n] |= (1 << bit); 661 } 662 663 static inline uint32_t 664 pcib_map_check(uint32_t *map, uint32_t start, uint32_t bits) 665 { 666 uint32_t i; 667 668 for (i = start; i < start + bits; i++) 669 if (pcib_bit_get(map, i)) 670 return (0); 671 672 return (1); 673 } 674 675 static inline void 676 pcib_map_set(uint32_t *map, uint32_t start, uint32_t bits) 677 { 678 uint32_t i; 679 680 for (i = start; i < start + bits; i++) 681 pcib_bit_set(map, i); 682 } 683 684 /* 685 * The idea of this allocator is taken from ARM No-Cache memory 686 * management code (sys/arm/arm/vm_machdep.c). 687 */ 688 static bus_addr_t 689 pcib_alloc(struct mv_pcib_softc *sc, uint32_t smask) 690 { 691 uint32_t bits, bits_limit, i, *map, min_alloc, size; 692 bus_addr_t addr = 0; 693 bus_addr_t base; 694 695 if (smask & 1) { 696 base = sc->sc_io_base; 697 min_alloc = PCI_MIN_IO_ALLOC; 698 bits_limit = sc->sc_io_size / min_alloc; 699 map = sc->sc_io_map; 700 smask &= ~0x3; 701 } else { 702 base = sc->sc_mem_base; 703 min_alloc = PCI_MIN_MEM_ALLOC; 704 bits_limit = sc->sc_mem_size / min_alloc; 705 map = sc->sc_mem_map; 706 smask &= ~0xF; 707 } 708 709 size = ~smask + 1; 710 bits = size / min_alloc; 711 712 for (i = 0; i + bits <= bits_limit; i += bits) 713 if (pcib_map_check(map, i, bits)) { 714 pcib_map_set(map, i, bits); 715 addr = base + (i * min_alloc); 716 return (addr); 717 } 718 719 return (addr); 720 } 721 722 static int 723 mv_pcib_init_bar(struct mv_pcib_softc *sc, int bus, int slot, int func, 724 int barno) 725 { 726 uint32_t addr, bar; 727 int reg, width; 728 729 reg = PCIR_BAR(barno); 730 731 /* 732 * Need to init the BAR register with 0xffffffff before correct 733 * value can be read. 734 */ 735 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4); 736 bar = mv_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4); 737 if (bar == 0) 738 return (1); 739 740 /* Calculate BAR size: 64 or 32 bit (in 32-bit units) */ 741 width = ((bar & 7) == 4) ? 2 : 1; 742 743 addr = pcib_alloc(sc, bar); 744 if (!addr) 745 return (-1); 746 747 if (bootverbose) 748 printf("PCI %u:%u:%u: reg %x: smask=%08x: addr=%08x\n", 749 bus, slot, func, reg, bar, addr); 750 751 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4); 752 if (width == 2) 753 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg + 4, 754 0, 4); 755 756 return (width); 757 } 758 759 static void 760 mv_pcib_init_bridge(struct mv_pcib_softc *sc, int bus, int slot, int func) 761 { 762 bus_addr_t io_base, mem_base; 763 uint32_t io_limit, mem_limit; 764 int secbus; 765 766 io_base = sc->sc_io_base; 767 io_limit = io_base + sc->sc_io_size - 1; 768 mem_base = sc->sc_mem_base; 769 mem_limit = mem_base + sc->sc_mem_size - 1; 770 771 /* Configure I/O decode registers */ 772 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEL_1, 773 io_base >> 8, 1); 774 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEH_1, 775 io_base >> 16, 2); 776 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITL_1, 777 io_limit >> 8, 1); 778 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITH_1, 779 io_limit >> 16, 2); 780 781 /* Configure memory decode registers */ 782 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMBASE_1, 783 mem_base >> 16, 2); 784 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMLIMIT_1, 785 mem_limit >> 16, 2); 786 787 /* Disable memory prefetch decode */ 788 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEL_1, 789 0x10, 2); 790 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEH_1, 791 0x0, 4); 792 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITL_1, 793 0xF, 2); 794 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITH_1, 795 0x0, 4); 796 797 secbus = mv_pcib_read_config(sc->sc_dev, bus, slot, func, 798 PCIR_SECBUS_1, 1); 799 800 /* Configure buses behind the bridge */ 801 mv_pcib_init(sc, secbus, PCI_SLOTMAX); 802 } 803 804 static int 805 mv_pcib_init(struct mv_pcib_softc *sc, int bus, int maxslot) 806 { 807 int slot, func, maxfunc, error; 808 uint8_t hdrtype, command, class, subclass; 809 810 for (slot = 0; slot <= maxslot; slot++) { 811 maxfunc = 0; 812 for (func = 0; func <= maxfunc; func++) { 813 hdrtype = mv_pcib_read_config(sc->sc_dev, bus, slot, 814 func, PCIR_HDRTYPE, 1); 815 816 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 817 continue; 818 819 if (func == 0 && (hdrtype & PCIM_MFDEV)) 820 maxfunc = PCI_FUNCMAX; 821 822 command = mv_pcib_read_config(sc->sc_dev, bus, slot, 823 func, PCIR_COMMAND, 1); 824 command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN); 825 mv_pcib_write_config(sc->sc_dev, bus, slot, func, 826 PCIR_COMMAND, command, 1); 827 828 error = mv_pcib_init_all_bars(sc, bus, slot, func, 829 hdrtype); 830 831 if (error) 832 return (error); 833 834 command |= PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | 835 PCIM_CMD_PORTEN; 836 mv_pcib_write_config(sc->sc_dev, bus, slot, func, 837 PCIR_COMMAND, command, 1); 838 839 /* Handle PCI-PCI bridges */ 840 class = mv_pcib_read_config(sc->sc_dev, bus, slot, 841 func, PCIR_CLASS, 1); 842 subclass = mv_pcib_read_config(sc->sc_dev, bus, slot, 843 func, PCIR_SUBCLASS, 1); 844 845 if (class != PCIC_BRIDGE || 846 subclass != PCIS_BRIDGE_PCI) 847 continue; 848 849 mv_pcib_init_bridge(sc, bus, slot, func); 850 } 851 } 852 853 /* Enable all ABCD interrupts */ 854 pcib_write_irq_mask(sc, (0xF << 24)); 855 856 return (0); 857 } 858 859 static int 860 mv_pcib_init_all_bars(struct mv_pcib_softc *sc, int bus, int slot, 861 int func, int hdrtype) 862 { 863 int maxbar, bar, i; 864 865 maxbar = (hdrtype & PCIM_HDRTYPE) ? 0 : 6; 866 bar = 0; 867 868 /* Program the base address registers */ 869 while (bar < maxbar) { 870 i = mv_pcib_init_bar(sc, bus, slot, func, bar); 871 bar += i; 872 if (i < 0) { 873 device_printf(sc->sc_dev, 874 "PCI IO/Memory space exhausted\n"); 875 return (ENOMEM); 876 } 877 } 878 879 return (0); 880 } 881 882 static struct resource * 883 mv_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 884 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 885 { 886 struct mv_pcib_softc *sc = device_get_softc(dev); 887 struct rman *rm = NULL; 888 struct resource *res; 889 890 switch (type) { 891 case SYS_RES_IOPORT: 892 rm = &sc->sc_io_rman; 893 break; 894 case SYS_RES_MEMORY: 895 rm = &sc->sc_mem_rman; 896 break; 897 #ifdef PCI_RES_BUS 898 case PCI_RES_BUS: 899 return (pci_domain_alloc_bus(sc->ap_segment, child, rid, start, 900 end, count, flags)); 901 #endif 902 default: 903 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, 904 type, rid, start, end, count, flags)); 905 } 906 907 if (RMAN_IS_DEFAULT_RANGE(start, end)) { 908 start = sc->sc_mem_base; 909 end = sc->sc_mem_base + sc->sc_mem_size - 1; 910 count = sc->sc_mem_size; 911 } 912 913 if ((start < sc->sc_mem_base) || (start + count - 1 != end) || 914 (end > sc->sc_mem_base + sc->sc_mem_size - 1)) 915 return (NULL); 916 917 res = rman_reserve_resource(rm, start, end, count, flags, child); 918 if (res == NULL) 919 return (NULL); 920 921 rman_set_rid(res, *rid); 922 rman_set_bustag(res, fdtbus_bs_tag); 923 rman_set_bushandle(res, start); 924 925 if (flags & RF_ACTIVE) 926 if (bus_activate_resource(child, type, *rid, res)) { 927 rman_release_resource(res); 928 return (NULL); 929 } 930 931 return (res); 932 } 933 934 static int 935 mv_pcib_release_resource(device_t dev, device_t child, int type, int rid, 936 struct resource *res) 937 { 938 #ifdef PCI_RES_BUS 939 struct mv_pcib_softc *sc = device_get_softc(dev); 940 941 if (type == PCI_RES_BUS) 942 return (pci_domain_release_bus(sc->ap_segment, child, rid, res)); 943 #endif 944 if (type != SYS_RES_IOPORT && type != SYS_RES_MEMORY) 945 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child, 946 type, rid, res)); 947 948 return (rman_release_resource(res)); 949 } 950 951 static int 952 mv_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 953 { 954 struct mv_pcib_softc *sc = device_get_softc(dev); 955 956 switch (which) { 957 case PCIB_IVAR_BUS: 958 *result = sc->sc_busnr; 959 return (0); 960 case PCIB_IVAR_DOMAIN: 961 *result = device_get_unit(dev); 962 return (0); 963 } 964 965 return (ENOENT); 966 } 967 968 static int 969 mv_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 970 { 971 struct mv_pcib_softc *sc = device_get_softc(dev); 972 973 switch (which) { 974 case PCIB_IVAR_BUS: 975 sc->sc_busnr = value; 976 return (0); 977 } 978 979 return (ENOENT); 980 } 981 982 static inline void 983 pcib_write_irq_mask(struct mv_pcib_softc *sc, uint32_t mask) 984 { 985 986 if (sc->sc_type != MV_TYPE_PCIE) 987 return; 988 989 bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_IRQ_MASK, mask); 990 } 991 992 static void 993 mv_pcib_hw_cfginit(void) 994 { 995 static int opened = 0; 996 997 if (opened) 998 return; 999 1000 mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN); 1001 opened = 1; 1002 } 1003 1004 static uint32_t 1005 mv_pcib_hw_cfgread(struct mv_pcib_softc *sc, u_int bus, u_int slot, 1006 u_int func, u_int reg, int bytes) 1007 { 1008 uint32_t addr, data, ca, cd; 1009 1010 ca = (sc->sc_type != MV_TYPE_PCI) ? 1011 PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR; 1012 cd = (sc->sc_type != MV_TYPE_PCI) ? 1013 PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA; 1014 addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | 1015 PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg); 1016 1017 mtx_lock_spin(&pcicfg_mtx); 1018 bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr); 1019 1020 data = ~0; 1021 switch (bytes) { 1022 case 1: 1023 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 1024 cd + (reg & 3)); 1025 break; 1026 case 2: 1027 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh, 1028 cd + (reg & 2))); 1029 break; 1030 case 4: 1031 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh, 1032 cd)); 1033 break; 1034 } 1035 mtx_unlock_spin(&pcicfg_mtx); 1036 return (data); 1037 } 1038 1039 static void 1040 mv_pcib_hw_cfgwrite(struct mv_pcib_softc *sc, u_int bus, u_int slot, 1041 u_int func, u_int reg, uint32_t data, int bytes) 1042 { 1043 uint32_t addr, ca, cd; 1044 1045 ca = (sc->sc_type != MV_TYPE_PCI) ? 1046 PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR; 1047 cd = (sc->sc_type != MV_TYPE_PCI) ? 1048 PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA; 1049 addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) | 1050 PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg); 1051 1052 mtx_lock_spin(&pcicfg_mtx); 1053 bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr); 1054 1055 switch (bytes) { 1056 case 1: 1057 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 1058 cd + (reg & 3), data); 1059 break; 1060 case 2: 1061 bus_space_write_2(sc->sc_bst, sc->sc_bsh, 1062 cd + (reg & 2), htole16(data)); 1063 break; 1064 case 4: 1065 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 1066 cd, htole32(data)); 1067 break; 1068 } 1069 mtx_unlock_spin(&pcicfg_mtx); 1070 } 1071 1072 static int 1073 mv_pcib_maxslots(device_t dev) 1074 { 1075 struct mv_pcib_softc *sc = device_get_softc(dev); 1076 1077 return ((sc->sc_type != MV_TYPE_PCI) ? 1 : PCI_SLOTMAX); 1078 } 1079 1080 static int 1081 mv_pcib_root_slot(device_t dev, u_int bus, u_int slot, u_int func) 1082 { 1083 struct mv_pcib_softc *sc = device_get_softc(dev); 1084 uint32_t vendor, device; 1085 1086 /* On platforms other than Armada38x, root link is always at slot 0 */ 1087 if (!sc->sc_enable_find_root_slot) 1088 return (slot == 0); 1089 1090 vendor = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_VENDOR, 1091 PCIR_VENDOR_LENGTH); 1092 device = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_DEVICE, 1093 PCIR_DEVICE_LENGTH) & MV_DEV_FAMILY_MASK; 1094 1095 return (vendor == PCI_VENDORID_MRVL && device == MV_DEV_ARMADA38X); 1096 } 1097 1098 static uint32_t 1099 mv_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 1100 u_int reg, int bytes) 1101 { 1102 struct mv_pcib_softc *sc = device_get_softc(dev); 1103 1104 /* Return ~0 if link is inactive or trying to read from Root */ 1105 if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) & 1106 PCIE_STATUS_LINK_DOWN) || mv_pcib_root_slot(dev, bus, slot, func)) 1107 return (~0U); 1108 1109 return (mv_pcib_hw_cfgread(sc, bus, slot, func, reg, bytes)); 1110 } 1111 1112 static void 1113 mv_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 1114 u_int reg, uint32_t val, int bytes) 1115 { 1116 struct mv_pcib_softc *sc = device_get_softc(dev); 1117 1118 /* Return if link is inactive or trying to write to Root */ 1119 if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) & 1120 PCIE_STATUS_LINK_DOWN) || mv_pcib_root_slot(dev, bus, slot, func)) 1121 return; 1122 1123 mv_pcib_hw_cfgwrite(sc, bus, slot, func, reg, val, bytes); 1124 } 1125 1126 static int 1127 mv_pcib_route_interrupt(device_t bus, device_t dev, int pin) 1128 { 1129 struct mv_pcib_softc *sc; 1130 struct ofw_pci_register reg; 1131 uint32_t pintr, mintr[4]; 1132 int icells; 1133 phandle_t iparent; 1134 1135 sc = device_get_softc(bus); 1136 pintr = pin; 1137 1138 /* Fabricate imap information in case this isn't an OFW device */ 1139 bzero(®, sizeof(reg)); 1140 reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) | 1141 (pci_get_slot(dev) << OFW_PCI_PHYS_HI_DEVICESHIFT) | 1142 (pci_get_function(dev) << OFW_PCI_PHYS_HI_FUNCTIONSHIFT); 1143 1144 icells = ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo, 1145 ®, sizeof(reg), &pintr, sizeof(pintr), mintr, sizeof(mintr), 1146 &iparent); 1147 if (icells > 0) 1148 return (ofw_bus_map_intr(dev, iparent, icells, mintr)); 1149 1150 /* Maybe it's a real interrupt, not an intpin */ 1151 if (pin > 4) 1152 return (pin); 1153 1154 device_printf(bus, "could not route pin %d for device %d.%d\n", 1155 pin, pci_get_slot(dev), pci_get_function(dev)); 1156 return (PCI_INVALID_IRQ); 1157 } 1158 1159 static int 1160 mv_pcib_decode_win(phandle_t node, struct mv_pcib_softc *sc) 1161 { 1162 struct mv_pci_range io_space, mem_space; 1163 device_t dev; 1164 int error; 1165 1166 dev = sc->sc_dev; 1167 1168 if ((error = mv_pci_ranges(node, &io_space, &mem_space)) != 0) { 1169 device_printf(dev, "could not retrieve 'ranges' data\n"); 1170 return (error); 1171 } 1172 1173 /* Configure CPU decoding windows */ 1174 error = decode_win_cpu_set(sc->sc_win_target, 1175 sc->sc_io_win_attr, io_space.base_parent, io_space.len, ~0); 1176 if (error < 0) { 1177 device_printf(dev, "could not set up CPU decode " 1178 "window for PCI IO\n"); 1179 return (ENXIO); 1180 } 1181 error = decode_win_cpu_set(sc->sc_win_target, 1182 sc->sc_mem_win_attr, mem_space.base_parent, mem_space.len, 1183 mem_space.base_parent); 1184 if (error < 0) { 1185 device_printf(dev, "could not set up CPU decode " 1186 "windows for PCI MEM\n"); 1187 return (ENXIO); 1188 } 1189 1190 sc->sc_io_base = io_space.base_parent; 1191 sc->sc_io_size = io_space.len; 1192 1193 sc->sc_mem_base = mem_space.base_parent; 1194 sc->sc_mem_size = mem_space.len; 1195 1196 return (0); 1197 } 1198 1199 static int 1200 mv_pcib_map_msi(device_t dev, device_t child, int irq, uint64_t *addr, 1201 uint32_t *data) 1202 { 1203 struct mv_pcib_softc *sc; 1204 1205 sc = device_get_softc(dev); 1206 if (!sc->sc_msi_supported) 1207 return (ENOTSUP); 1208 1209 irq = irq - MSI_IRQ; 1210 1211 /* validate parameters */ 1212 if (isclr(&sc->sc_msi_bitmap, irq)) { 1213 device_printf(dev, "invalid MSI 0x%x\n", irq); 1214 return (EINVAL); 1215 } 1216 1217 mv_msi_data(irq, addr, data); 1218 1219 debugf("%s: irq: %d addr: %jx data: %x\n", 1220 __func__, irq, *addr, *data); 1221 1222 return (0); 1223 } 1224 1225 static int 1226 mv_pcib_alloc_msi(device_t dev, device_t child, int count, 1227 int maxcount __unused, int *irqs) 1228 { 1229 struct mv_pcib_softc *sc; 1230 u_int start = 0, i; 1231 1232 sc = device_get_softc(dev); 1233 if (!sc->sc_msi_supported) 1234 return (ENOTSUP); 1235 1236 if (powerof2(count) == 0 || count > MSI_IRQ_NUM) 1237 return (EINVAL); 1238 1239 mtx_lock(&sc->sc_msi_mtx); 1240 1241 for (start = 0; (start + count) < MSI_IRQ_NUM; start++) { 1242 for (i = start; i < start + count; i++) { 1243 if (isset(&sc->sc_msi_bitmap, i)) 1244 break; 1245 } 1246 if (i == start + count) 1247 break; 1248 } 1249 1250 if ((start + count) == MSI_IRQ_NUM) { 1251 mtx_unlock(&sc->sc_msi_mtx); 1252 return (ENXIO); 1253 } 1254 1255 for (i = start; i < start + count; i++) { 1256 setbit(&sc->sc_msi_bitmap, i); 1257 *irqs++ = MSI_IRQ + i; 1258 } 1259 debugf("%s: start: %x count: %x\n", __func__, start, count); 1260 1261 mtx_unlock(&sc->sc_msi_mtx); 1262 return (0); 1263 } 1264 1265 static int 1266 mv_pcib_release_msi(device_t dev, device_t child, int count, int *irqs) 1267 { 1268 struct mv_pcib_softc *sc; 1269 u_int i; 1270 1271 sc = device_get_softc(dev); 1272 if(!sc->sc_msi_supported) 1273 return (ENOTSUP); 1274 1275 mtx_lock(&sc->sc_msi_mtx); 1276 1277 for (i = 0; i < count; i++) 1278 clrbit(&sc->sc_msi_bitmap, irqs[i] - MSI_IRQ); 1279 1280 mtx_unlock(&sc->sc_msi_mtx); 1281 return (0); 1282 }
Cache object: 0c7109325144767db8bc2960460fddd2
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