FreeBSD/Linux Kernel Cross Reference
sys/arm/mv/mv_pci.c
1 /*-
2 * Copyright (c) 2008 MARVELL INTERNATIONAL LTD.
3 * Copyright (c) 2010 The FreeBSD Foundation
4 * Copyright (c) 2010-2012 Semihalf
5 * All rights reserved.
6 *
7 * Developed by Semihalf.
8 *
9 * Portions of this software were developed by Semihalf
10 * under sponsorship from the FreeBSD Foundation.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. Neither the name of MARVELL nor the names of contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 */
36
37 /*
38 * Marvell integrated PCI/PCI-Express controller driver.
39 */
40
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD: releng/10.0/sys/arm/mv/mv_pci.c 240493 2012-09-14 10:06:56Z gber $");
43
44 #include <sys/param.h>
45 #include <sys/systm.h>
46 #include <sys/kernel.h>
47 #include <sys/lock.h>
48 #include <sys/malloc.h>
49 #include <sys/module.h>
50 #include <sys/mutex.h>
51 #include <sys/queue.h>
52 #include <sys/bus.h>
53 #include <sys/rman.h>
54 #include <sys/endian.h>
55
56 #include <machine/intr.h>
57
58 #include <vm/vm.h>
59 #include <vm/pmap.h>
60
61 #include <dev/fdt/fdt_common.h>
62 #include <dev/ofw/ofw_bus.h>
63 #include <dev/ofw/ofw_bus_subr.h>
64 #include <dev/pci/pcivar.h>
65 #include <dev/pci/pcireg.h>
66 #include <dev/pci/pcib_private.h>
67
68 #include "ofw_bus_if.h"
69 #include "pcib_if.h"
70
71 #include <machine/resource.h>
72 #include <machine/bus.h>
73
74 #include <arm/mv/mvreg.h>
75 #include <arm/mv/mvvar.h>
76 #include <arm/mv/mvwin.h>
77
78 #ifdef DEBUG
79 #define debugf(fmt, args...) do { printf(fmt,##args); } while (0)
80 #else
81 #define debugf(fmt, args...)
82 #endif
83
84 #define PCI_CFG_ENA (1 << 31)
85 #define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16)
86 #define PCI_CFG_DEV(dev) (((dev) & 0x1f) << 11)
87 #define PCI_CFG_FUN(fun) (((fun) & 0x7) << 8)
88 #define PCI_CFG_PCIE_REG(reg) ((reg) & 0xfc)
89
90 #define PCI_REG_CFG_ADDR 0x0C78
91 #define PCI_REG_CFG_DATA 0x0C7C
92
93 #define PCIE_REG_CFG_ADDR 0x18F8
94 #define PCIE_REG_CFG_DATA 0x18FC
95 #define PCIE_REG_CONTROL 0x1A00
96 #define PCIE_CTRL_LINK1X 0x00000001
97 #define PCIE_REG_STATUS 0x1A04
98 #define PCIE_REG_IRQ_MASK 0x1910
99
100 #define PCIE_CONTROL_ROOT_CMPLX (1 << 1)
101 #define PCIE_CONTROL_HOT_RESET (1 << 24)
102
103 #define PCIE_LINK_TIMEOUT 1000000
104
105 #define PCIE_STATUS_LINK_DOWN 1
106 #define PCIE_STATUS_DEV_OFFS 16
107
108 /* Minimum PCI Memory and I/O allocations taken from PCI spec (in bytes) */
109 #define PCI_MIN_IO_ALLOC 4
110 #define PCI_MIN_MEM_ALLOC 16
111
112 #define BITS_PER_UINT32 (NBBY * sizeof(uint32_t))
113
114 struct mv_pcib_softc {
115 device_t sc_dev;
116
117 struct rman sc_mem_rman;
118 bus_addr_t sc_mem_base;
119 bus_addr_t sc_mem_size;
120 uint32_t sc_mem_map[MV_PCI_MEM_SLICE_SIZE /
121 (PCI_MIN_MEM_ALLOC * BITS_PER_UINT32)];
122 int sc_win_target;
123 int sc_mem_win_attr;
124
125 struct rman sc_io_rman;
126 bus_addr_t sc_io_base;
127 bus_addr_t sc_io_size;
128 uint32_t sc_io_map[MV_PCI_IO_SLICE_SIZE /
129 (PCI_MIN_IO_ALLOC * BITS_PER_UINT32)];
130 int sc_io_win_attr;
131
132 struct resource *sc_res;
133 bus_space_handle_t sc_bsh;
134 bus_space_tag_t sc_bst;
135 int sc_rid;
136
137 struct mtx sc_msi_mtx;
138 uint32_t sc_msi_bitmap;
139
140 int sc_busnr; /* Host bridge bus number */
141 int sc_devnr; /* Host bridge device number */
142 int sc_type;
143 int sc_mode; /* Endpoint / Root Complex */
144
145 struct fdt_pci_intr sc_intr_info;
146 };
147
148 /* Local forward prototypes */
149 static int mv_pcib_decode_win(phandle_t, struct mv_pcib_softc *);
150 static void mv_pcib_hw_cfginit(void);
151 static uint32_t mv_pcib_hw_cfgread(struct mv_pcib_softc *, u_int, u_int,
152 u_int, u_int, int);
153 static void mv_pcib_hw_cfgwrite(struct mv_pcib_softc *, u_int, u_int,
154 u_int, u_int, uint32_t, int);
155 static int mv_pcib_init(struct mv_pcib_softc *, int, int);
156 static int mv_pcib_init_all_bars(struct mv_pcib_softc *, int, int, int, int);
157 static void mv_pcib_init_bridge(struct mv_pcib_softc *, int, int, int);
158 static int mv_pcib_intr_info(phandle_t, struct mv_pcib_softc *);
159 static inline void pcib_write_irq_mask(struct mv_pcib_softc *, uint32_t);
160 static void mv_pcib_enable(struct mv_pcib_softc *, uint32_t);
161 static int mv_pcib_mem_init(struct mv_pcib_softc *);
162
163 /* Forward prototypes */
164 static int mv_pcib_probe(device_t);
165 static int mv_pcib_attach(device_t);
166
167 static struct resource *mv_pcib_alloc_resource(device_t, device_t, int, int *,
168 u_long, u_long, u_long, u_int);
169 static int mv_pcib_release_resource(device_t, device_t, int, int,
170 struct resource *);
171 static int mv_pcib_read_ivar(device_t, device_t, int, uintptr_t *);
172 static int mv_pcib_write_ivar(device_t, device_t, int, uintptr_t);
173
174 static int mv_pcib_maxslots(device_t);
175 static uint32_t mv_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int);
176 static void mv_pcib_write_config(device_t, u_int, u_int, u_int, u_int,
177 uint32_t, int);
178 static int mv_pcib_route_interrupt(device_t, device_t, int);
179 #if defined(SOC_MV_ARMADAXP)
180 static int mv_pcib_alloc_msi(device_t, device_t, int, int, int *);
181 static int mv_pcib_map_msi(device_t, device_t, int, uint64_t *, uint32_t *);
182 static int mv_pcib_release_msi(device_t, device_t, int, int *);
183 #endif
184
185 /*
186 * Bus interface definitions.
187 */
188 static device_method_t mv_pcib_methods[] = {
189 /* Device interface */
190 DEVMETHOD(device_probe, mv_pcib_probe),
191 DEVMETHOD(device_attach, mv_pcib_attach),
192
193 /* Bus interface */
194 DEVMETHOD(bus_read_ivar, mv_pcib_read_ivar),
195 DEVMETHOD(bus_write_ivar, mv_pcib_write_ivar),
196 DEVMETHOD(bus_alloc_resource, mv_pcib_alloc_resource),
197 DEVMETHOD(bus_release_resource, mv_pcib_release_resource),
198 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
199 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
200 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
201 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
202
203 /* pcib interface */
204 DEVMETHOD(pcib_maxslots, mv_pcib_maxslots),
205 DEVMETHOD(pcib_read_config, mv_pcib_read_config),
206 DEVMETHOD(pcib_write_config, mv_pcib_write_config),
207 DEVMETHOD(pcib_route_interrupt, mv_pcib_route_interrupt),
208
209 #if defined(SOC_MV_ARMADAXP)
210 DEVMETHOD(pcib_alloc_msi, mv_pcib_alloc_msi),
211 DEVMETHOD(pcib_release_msi, mv_pcib_release_msi),
212 DEVMETHOD(pcib_map_msi, mv_pcib_map_msi),
213 #endif
214
215 /* OFW bus interface */
216 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
217 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
218 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
219 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
220 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
221
222 DEVMETHOD_END
223 };
224
225 static driver_t mv_pcib_driver = {
226 "pcib",
227 mv_pcib_methods,
228 sizeof(struct mv_pcib_softc),
229 };
230
231 devclass_t pcib_devclass;
232
233 DRIVER_MODULE(pcib, fdtbus, mv_pcib_driver, pcib_devclass, 0, 0);
234
235 static struct mtx pcicfg_mtx;
236
237 static int
238 mv_pcib_probe(device_t self)
239 {
240 phandle_t node;
241
242 node = ofw_bus_get_node(self);
243 if (!fdt_is_type(node, "pci"))
244 return (ENXIO);
245
246 if (!(fdt_is_compatible(node, "mrvl,pcie") ||
247 fdt_is_compatible(node, "mrvl,pci")))
248 return (ENXIO);
249
250 device_set_desc(self, "Marvell Integrated PCI/PCI-E Controller");
251 return (BUS_PROBE_DEFAULT);
252 }
253
254 static int
255 mv_pcib_attach(device_t self)
256 {
257 struct mv_pcib_softc *sc;
258 phandle_t node, parnode;
259 uint32_t val, unit;
260 int err;
261
262 sc = device_get_softc(self);
263 sc->sc_dev = self;
264 unit = fdt_get_unit(self);
265
266
267 node = ofw_bus_get_node(self);
268 parnode = OF_parent(node);
269 if (fdt_is_compatible(node, "mrvl,pcie")) {
270 sc->sc_type = MV_TYPE_PCIE;
271 sc->sc_win_target = MV_WIN_PCIE_TARGET(unit);
272 sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR(unit);
273 sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR(unit);
274 } else if (fdt_is_compatible(node, "mrvl,pci")) {
275 sc->sc_type = MV_TYPE_PCI;
276 sc->sc_win_target = MV_WIN_PCI_TARGET;
277 sc->sc_mem_win_attr = MV_WIN_PCI_MEM_ATTR;
278 sc->sc_io_win_attr = MV_WIN_PCI_IO_ATTR;
279 } else
280 return (ENXIO);
281
282 /*
283 * Retrieve our mem-mapped registers range.
284 */
285 sc->sc_rid = 0;
286 sc->sc_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &sc->sc_rid,
287 RF_ACTIVE);
288 if (sc->sc_res == NULL) {
289 device_printf(self, "could not map memory\n");
290 return (ENXIO);
291 }
292 sc->sc_bst = rman_get_bustag(sc->sc_res);
293 sc->sc_bsh = rman_get_bushandle(sc->sc_res);
294
295 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_CONTROL);
296 sc->sc_mode = (val & PCIE_CONTROL_ROOT_CMPLX ? MV_MODE_ROOT :
297 MV_MODE_ENDPOINT);
298
299 /*
300 * Get PCI interrupt info.
301 */
302 if ((sc->sc_mode == MV_MODE_ROOT) &&
303 (mv_pcib_intr_info(node, sc) != 0)) {
304 device_printf(self, "could not retrieve interrupt info\n");
305 return (ENXIO);
306 }
307
308 /*
309 * Configure decode windows for PCI(E) access.
310 */
311 if (mv_pcib_decode_win(node, sc) != 0)
312 return (ENXIO);
313
314 mv_pcib_hw_cfginit();
315
316 /*
317 * Enable PCIE device.
318 */
319 mv_pcib_enable(sc, unit);
320
321 /*
322 * Memory management.
323 */
324 err = mv_pcib_mem_init(sc);
325 if (err)
326 return (err);
327
328 if (sc->sc_mode == MV_MODE_ROOT) {
329 err = mv_pcib_init(sc, sc->sc_busnr,
330 mv_pcib_maxslots(sc->sc_dev));
331 if (err)
332 goto error;
333
334 device_add_child(self, "pci", -1);
335 } else {
336 sc->sc_devnr = 1;
337 bus_space_write_4(sc->sc_bst, sc->sc_bsh,
338 PCIE_REG_STATUS, 1 << PCIE_STATUS_DEV_OFFS);
339 device_add_child(self, "pci_ep", -1);
340 }
341
342 mtx_init(&sc->sc_msi_mtx, "msi_mtx", NULL, MTX_DEF);
343 return (bus_generic_attach(self));
344
345 error:
346 /* XXX SYS_RES_ should be released here */
347 rman_fini(&sc->sc_mem_rman);
348 rman_fini(&sc->sc_io_rman);
349
350 return (err);
351 }
352
353 static void
354 mv_pcib_enable(struct mv_pcib_softc *sc, uint32_t unit)
355 {
356 uint32_t val;
357 #if !defined(SOC_MV_ARMADAXP)
358 int timeout;
359
360 /*
361 * Check if PCIE device is enabled.
362 */
363 if (read_cpu_ctrl(CPU_CONTROL) & CPU_CONTROL_PCIE_DISABLE(unit)) {
364 write_cpu_ctrl(CPU_CONTROL, read_cpu_ctrl(CPU_CONTROL) &
365 ~(CPU_CONTROL_PCIE_DISABLE(unit)));
366
367 timeout = PCIE_LINK_TIMEOUT;
368 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
369 PCIE_REG_STATUS);
370 while (((val & PCIE_STATUS_LINK_DOWN) == 1) && (timeout > 0)) {
371 DELAY(1000);
372 timeout -= 1000;
373 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
374 PCIE_REG_STATUS);
375 }
376 }
377 #endif
378
379
380 if (sc->sc_mode == MV_MODE_ROOT) {
381 /*
382 * Enable PCI bridge.
383 */
384 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND);
385 val |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN |
386 PCIM_CMD_MEMEN | PCIM_CMD_PORTEN;
387 bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND, val);
388 }
389 }
390
391 static int
392 mv_pcib_mem_init(struct mv_pcib_softc *sc)
393 {
394 int err;
395
396 /*
397 * Memory management.
398 */
399 sc->sc_mem_rman.rm_type = RMAN_ARRAY;
400 err = rman_init(&sc->sc_mem_rman);
401 if (err)
402 return (err);
403
404 sc->sc_io_rman.rm_type = RMAN_ARRAY;
405 err = rman_init(&sc->sc_io_rman);
406 if (err) {
407 rman_fini(&sc->sc_mem_rman);
408 return (err);
409 }
410
411 err = rman_manage_region(&sc->sc_mem_rman, sc->sc_mem_base,
412 sc->sc_mem_base + sc->sc_mem_size - 1);
413 if (err)
414 goto error;
415
416 err = rman_manage_region(&sc->sc_io_rman, sc->sc_io_base,
417 sc->sc_io_base + sc->sc_io_size - 1);
418 if (err)
419 goto error;
420
421 return (0);
422
423 error:
424 rman_fini(&sc->sc_mem_rman);
425 rman_fini(&sc->sc_io_rman);
426
427 return (err);
428 }
429
430 static inline uint32_t
431 pcib_bit_get(uint32_t *map, uint32_t bit)
432 {
433 uint32_t n = bit / BITS_PER_UINT32;
434
435 bit = bit % BITS_PER_UINT32;
436 return (map[n] & (1 << bit));
437 }
438
439 static inline void
440 pcib_bit_set(uint32_t *map, uint32_t bit)
441 {
442 uint32_t n = bit / BITS_PER_UINT32;
443
444 bit = bit % BITS_PER_UINT32;
445 map[n] |= (1 << bit);
446 }
447
448 static inline uint32_t
449 pcib_map_check(uint32_t *map, uint32_t start, uint32_t bits)
450 {
451 uint32_t i;
452
453 for (i = start; i < start + bits; i++)
454 if (pcib_bit_get(map, i))
455 return (0);
456
457 return (1);
458 }
459
460 static inline void
461 pcib_map_set(uint32_t *map, uint32_t start, uint32_t bits)
462 {
463 uint32_t i;
464
465 for (i = start; i < start + bits; i++)
466 pcib_bit_set(map, i);
467 }
468
469 /*
470 * The idea of this allocator is taken from ARM No-Cache memory
471 * management code (sys/arm/arm/vm_machdep.c).
472 */
473 static bus_addr_t
474 pcib_alloc(struct mv_pcib_softc *sc, uint32_t smask)
475 {
476 uint32_t bits, bits_limit, i, *map, min_alloc, size;
477 bus_addr_t addr = 0;
478 bus_addr_t base;
479
480 if (smask & 1) {
481 base = sc->sc_io_base;
482 min_alloc = PCI_MIN_IO_ALLOC;
483 bits_limit = sc->sc_io_size / min_alloc;
484 map = sc->sc_io_map;
485 smask &= ~0x3;
486 } else {
487 base = sc->sc_mem_base;
488 min_alloc = PCI_MIN_MEM_ALLOC;
489 bits_limit = sc->sc_mem_size / min_alloc;
490 map = sc->sc_mem_map;
491 smask &= ~0xF;
492 }
493
494 size = ~smask + 1;
495 bits = size / min_alloc;
496
497 for (i = 0; i + bits <= bits_limit; i += bits)
498 if (pcib_map_check(map, i, bits)) {
499 pcib_map_set(map, i, bits);
500 addr = base + (i * min_alloc);
501 return (addr);
502 }
503
504 return (addr);
505 }
506
507 static int
508 mv_pcib_init_bar(struct mv_pcib_softc *sc, int bus, int slot, int func,
509 int barno)
510 {
511 uint32_t addr, bar;
512 int reg, width;
513
514 reg = PCIR_BAR(barno);
515
516 /*
517 * Need to init the BAR register with 0xffffffff before correct
518 * value can be read.
519 */
520 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4);
521 bar = mv_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4);
522 if (bar == 0)
523 return (1);
524
525 /* Calculate BAR size: 64 or 32 bit (in 32-bit units) */
526 width = ((bar & 7) == 4) ? 2 : 1;
527
528 addr = pcib_alloc(sc, bar);
529 if (!addr)
530 return (-1);
531
532 if (bootverbose)
533 printf("PCI %u:%u:%u: reg %x: smask=%08x: addr=%08x\n",
534 bus, slot, func, reg, bar, addr);
535
536 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4);
537 if (width == 2)
538 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg + 4,
539 0, 4);
540
541 return (width);
542 }
543
544 static void
545 mv_pcib_init_bridge(struct mv_pcib_softc *sc, int bus, int slot, int func)
546 {
547 bus_addr_t io_base, mem_base;
548 uint32_t io_limit, mem_limit;
549 int secbus;
550
551 io_base = sc->sc_io_base;
552 io_limit = io_base + sc->sc_io_size - 1;
553 mem_base = sc->sc_mem_base;
554 mem_limit = mem_base + sc->sc_mem_size - 1;
555
556 /* Configure I/O decode registers */
557 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEL_1,
558 io_base >> 8, 1);
559 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEH_1,
560 io_base >> 16, 2);
561 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITL_1,
562 io_limit >> 8, 1);
563 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITH_1,
564 io_limit >> 16, 2);
565
566 /* Configure memory decode registers */
567 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMBASE_1,
568 mem_base >> 16, 2);
569 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMLIMIT_1,
570 mem_limit >> 16, 2);
571
572 /* Disable memory prefetch decode */
573 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEL_1,
574 0x10, 2);
575 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEH_1,
576 0x0, 4);
577 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITL_1,
578 0xF, 2);
579 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITH_1,
580 0x0, 4);
581
582 secbus = mv_pcib_read_config(sc->sc_dev, bus, slot, func,
583 PCIR_SECBUS_1, 1);
584
585 /* Configure buses behind the bridge */
586 mv_pcib_init(sc, secbus, PCI_SLOTMAX);
587 }
588
589 static int
590 mv_pcib_init(struct mv_pcib_softc *sc, int bus, int maxslot)
591 {
592 int slot, func, maxfunc, error;
593 uint8_t hdrtype, command, class, subclass;
594
595 for (slot = 0; slot <= maxslot; slot++) {
596 maxfunc = 0;
597 for (func = 0; func <= maxfunc; func++) {
598 hdrtype = mv_pcib_read_config(sc->sc_dev, bus, slot,
599 func, PCIR_HDRTYPE, 1);
600
601 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
602 continue;
603
604 if (func == 0 && (hdrtype & PCIM_MFDEV))
605 maxfunc = PCI_FUNCMAX;
606
607 command = mv_pcib_read_config(sc->sc_dev, bus, slot,
608 func, PCIR_COMMAND, 1);
609 command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN);
610 mv_pcib_write_config(sc->sc_dev, bus, slot, func,
611 PCIR_COMMAND, command, 1);
612
613 error = mv_pcib_init_all_bars(sc, bus, slot, func,
614 hdrtype);
615
616 if (error)
617 return (error);
618
619 command |= PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN |
620 PCIM_CMD_PORTEN;
621 mv_pcib_write_config(sc->sc_dev, bus, slot, func,
622 PCIR_COMMAND, command, 1);
623
624 /* Handle PCI-PCI bridges */
625 class = mv_pcib_read_config(sc->sc_dev, bus, slot,
626 func, PCIR_CLASS, 1);
627 subclass = mv_pcib_read_config(sc->sc_dev, bus, slot,
628 func, PCIR_SUBCLASS, 1);
629
630 if (class != PCIC_BRIDGE ||
631 subclass != PCIS_BRIDGE_PCI)
632 continue;
633
634 mv_pcib_init_bridge(sc, bus, slot, func);
635 }
636 }
637
638 /* Enable all ABCD interrupts */
639 pcib_write_irq_mask(sc, (0xF << 24));
640
641 return (0);
642 }
643
644 static int
645 mv_pcib_init_all_bars(struct mv_pcib_softc *sc, int bus, int slot,
646 int func, int hdrtype)
647 {
648 int maxbar, bar, i;
649
650 maxbar = (hdrtype & PCIM_HDRTYPE) ? 0 : 6;
651 bar = 0;
652
653 /* Program the base address registers */
654 while (bar < maxbar) {
655 i = mv_pcib_init_bar(sc, bus, slot, func, bar);
656 bar += i;
657 if (i < 0) {
658 device_printf(sc->sc_dev,
659 "PCI IO/Memory space exhausted\n");
660 return (ENOMEM);
661 }
662 }
663
664 return (0);
665 }
666
667 static struct resource *
668 mv_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
669 u_long start, u_long end, u_long count, u_int flags)
670 {
671 struct mv_pcib_softc *sc = device_get_softc(dev);
672 struct rman *rm = NULL;
673 struct resource *res;
674
675 switch (type) {
676 case SYS_RES_IOPORT:
677 rm = &sc->sc_io_rman;
678 break;
679 case SYS_RES_MEMORY:
680 rm = &sc->sc_mem_rman;
681 break;
682 default:
683 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
684 type, rid, start, end, count, flags));
685 };
686
687 if ((start == 0UL) && (end == ~0UL)) {
688 start = sc->sc_mem_base;
689 end = sc->sc_mem_base + sc->sc_mem_size - 1;
690 count = sc->sc_mem_size;
691 }
692
693 if ((start < sc->sc_mem_base) || (start + count - 1 != end) ||
694 (end > sc->sc_mem_base + sc->sc_mem_size - 1))
695 return (NULL);
696
697 res = rman_reserve_resource(rm, start, end, count, flags, child);
698 if (res == NULL)
699 return (NULL);
700
701 rman_set_rid(res, *rid);
702 rman_set_bustag(res, fdtbus_bs_tag);
703 rman_set_bushandle(res, start);
704
705 if (flags & RF_ACTIVE)
706 if (bus_activate_resource(child, type, *rid, res)) {
707 rman_release_resource(res);
708 return (NULL);
709 }
710
711 return (res);
712 }
713
714 static int
715 mv_pcib_release_resource(device_t dev, device_t child, int type, int rid,
716 struct resource *res)
717 {
718
719 if (type != SYS_RES_IOPORT && type != SYS_RES_MEMORY)
720 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
721 type, rid, res));
722
723 return (rman_release_resource(res));
724 }
725
726 static int
727 mv_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
728 {
729 struct mv_pcib_softc *sc = device_get_softc(dev);
730
731 switch (which) {
732 case PCIB_IVAR_BUS:
733 *result = sc->sc_busnr;
734 return (0);
735 case PCIB_IVAR_DOMAIN:
736 *result = device_get_unit(dev);
737 return (0);
738 }
739
740 return (ENOENT);
741 }
742
743 static int
744 mv_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
745 {
746 struct mv_pcib_softc *sc = device_get_softc(dev);
747
748 switch (which) {
749 case PCIB_IVAR_BUS:
750 sc->sc_busnr = value;
751 return (0);
752 }
753
754 return (ENOENT);
755 }
756
757 static inline void
758 pcib_write_irq_mask(struct mv_pcib_softc *sc, uint32_t mask)
759 {
760
761 if (!sc->sc_type != MV_TYPE_PCI)
762 return;
763
764 bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_IRQ_MASK, mask);
765 }
766
767 static void
768 mv_pcib_hw_cfginit(void)
769 {
770 static int opened = 0;
771
772 if (opened)
773 return;
774
775 mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
776 opened = 1;
777 }
778
779 static uint32_t
780 mv_pcib_hw_cfgread(struct mv_pcib_softc *sc, u_int bus, u_int slot,
781 u_int func, u_int reg, int bytes)
782 {
783 uint32_t addr, data, ca, cd;
784
785 ca = (sc->sc_type != MV_TYPE_PCI) ?
786 PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR;
787 cd = (sc->sc_type != MV_TYPE_PCI) ?
788 PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA;
789 addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) |
790 PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg);
791
792 mtx_lock_spin(&pcicfg_mtx);
793 bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr);
794
795 data = ~0;
796 switch (bytes) {
797 case 1:
798 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh,
799 cd + (reg & 3));
800 break;
801 case 2:
802 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh,
803 cd + (reg & 2)));
804 break;
805 case 4:
806 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh,
807 cd));
808 break;
809 }
810 mtx_unlock_spin(&pcicfg_mtx);
811 return (data);
812 }
813
814 static void
815 mv_pcib_hw_cfgwrite(struct mv_pcib_softc *sc, u_int bus, u_int slot,
816 u_int func, u_int reg, uint32_t data, int bytes)
817 {
818 uint32_t addr, ca, cd;
819
820 ca = (sc->sc_type != MV_TYPE_PCI) ?
821 PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR;
822 cd = (sc->sc_type != MV_TYPE_PCI) ?
823 PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA;
824 addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) |
825 PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg);
826
827 mtx_lock_spin(&pcicfg_mtx);
828 bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr);
829
830 switch (bytes) {
831 case 1:
832 bus_space_write_1(sc->sc_bst, sc->sc_bsh,
833 cd + (reg & 3), data);
834 break;
835 case 2:
836 bus_space_write_2(sc->sc_bst, sc->sc_bsh,
837 cd + (reg & 2), htole16(data));
838 break;
839 case 4:
840 bus_space_write_4(sc->sc_bst, sc->sc_bsh,
841 cd, htole32(data));
842 break;
843 }
844 mtx_unlock_spin(&pcicfg_mtx);
845 }
846
847 static int
848 mv_pcib_maxslots(device_t dev)
849 {
850 struct mv_pcib_softc *sc = device_get_softc(dev);
851
852 return ((sc->sc_type != MV_TYPE_PCI) ? 1 : PCI_SLOTMAX);
853 }
854
855 static uint32_t
856 mv_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
857 u_int reg, int bytes)
858 {
859 struct mv_pcib_softc *sc = device_get_softc(dev);
860
861 /* Return ~0 if link is inactive or trying to read from Root */
862 if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) &
863 PCIE_STATUS_LINK_DOWN) || (slot == 0))
864 return (~0U);
865
866 return (mv_pcib_hw_cfgread(sc, bus, slot, func, reg, bytes));
867 }
868
869 static void
870 mv_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
871 u_int reg, uint32_t val, int bytes)
872 {
873 struct mv_pcib_softc *sc = device_get_softc(dev);
874
875 /* Return if link is inactive or trying to write to Root */
876 if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) &
877 PCIE_STATUS_LINK_DOWN) || (slot == 0))
878 return;
879
880 mv_pcib_hw_cfgwrite(sc, bus, slot, func, reg, val, bytes);
881 }
882
883 static int
884 mv_pcib_route_interrupt(device_t pcib, device_t dev, int pin)
885 {
886 struct mv_pcib_softc *sc;
887 int err, interrupt;
888
889 sc = device_get_softc(pcib);
890
891 err = fdt_pci_route_intr(pci_get_bus(dev), pci_get_slot(dev),
892 pci_get_function(dev), pin, &sc->sc_intr_info, &interrupt);
893 if (err == 0)
894 return (interrupt);
895
896 device_printf(pcib, "could not route pin %d for device %d.%d\n",
897 pin, pci_get_slot(dev), pci_get_function(dev));
898 return (PCI_INVALID_IRQ);
899 }
900
901 static int
902 mv_pcib_decode_win(phandle_t node, struct mv_pcib_softc *sc)
903 {
904 struct fdt_pci_range io_space, mem_space;
905 device_t dev;
906 int error;
907
908 dev = sc->sc_dev;
909
910 if ((error = fdt_pci_ranges(node, &io_space, &mem_space)) != 0) {
911 device_printf(dev, "could not retrieve 'ranges' data\n");
912 return (error);
913 }
914
915 /* Configure CPU decoding windows */
916 error = decode_win_cpu_set(sc->sc_win_target,
917 sc->sc_io_win_attr, io_space.base_parent, io_space.len, ~0);
918 if (error < 0) {
919 device_printf(dev, "could not set up CPU decode "
920 "window for PCI IO\n");
921 return (ENXIO);
922 }
923 error = decode_win_cpu_set(sc->sc_win_target,
924 sc->sc_mem_win_attr, mem_space.base_parent, mem_space.len,
925 mem_space.base_parent);
926 if (error < 0) {
927 device_printf(dev, "could not set up CPU decode "
928 "windows for PCI MEM\n");
929 return (ENXIO);
930 }
931
932 sc->sc_io_base = io_space.base_parent;
933 sc->sc_io_size = io_space.len;
934
935 sc->sc_mem_base = mem_space.base_parent;
936 sc->sc_mem_size = mem_space.len;
937
938 return (0);
939 }
940
941 static int
942 mv_pcib_intr_info(phandle_t node, struct mv_pcib_softc *sc)
943 {
944 int error;
945
946 if ((error = fdt_pci_intr_info(node, &sc->sc_intr_info)) != 0)
947 return (error);
948
949 return (0);
950 }
951
952 #if defined(SOC_MV_ARMADAXP)
953 static int
954 mv_pcib_map_msi(device_t dev, device_t child, int irq, uint64_t *addr,
955 uint32_t *data)
956 {
957 struct mv_pcib_softc *sc;
958
959 sc = device_get_softc(dev);
960 irq = irq - MSI_IRQ;
961
962 /* validate parameters */
963 if (isclr(&sc->sc_msi_bitmap, irq)) {
964 device_printf(dev, "invalid MSI 0x%x\n", irq);
965 return (EINVAL);
966 }
967
968 mv_msi_data(irq, addr, data);
969
970 debugf("%s: irq: %d addr: %jx data: %x\n",
971 __func__, irq, *addr, *data);
972
973 return (0);
974 }
975
976 static int
977 mv_pcib_alloc_msi(device_t dev, device_t child, int count,
978 int maxcount __unused, int *irqs)
979 {
980 struct mv_pcib_softc *sc;
981 u_int start = 0, i;
982
983 if (powerof2(count) == 0 || count > MSI_IRQ_NUM)
984 return (EINVAL);
985
986 sc = device_get_softc(dev);
987 mtx_lock(&sc->sc_msi_mtx);
988
989 for (start = 0; (start + count) < MSI_IRQ_NUM; start++) {
990 for (i = start; i < start + count; i++) {
991 if (isset(&sc->sc_msi_bitmap, i))
992 break;
993 }
994 if (i == start + count)
995 break;
996 }
997
998 if ((start + count) == MSI_IRQ_NUM) {
999 mtx_unlock(&sc->sc_msi_mtx);
1000 return (ENXIO);
1001 }
1002
1003 for (i = start; i < start + count; i++) {
1004 setbit(&sc->sc_msi_bitmap, i);
1005 irqs[i] = MSI_IRQ + i;
1006 }
1007 debugf("%s: start: %x count: %x\n", __func__, start, count);
1008
1009 mtx_unlock(&sc->sc_msi_mtx);
1010 return (0);
1011 }
1012
1013 static int
1014 mv_pcib_release_msi(device_t dev, device_t child, int count, int *irqs)
1015 {
1016 struct mv_pcib_softc *sc;
1017 u_int i;
1018
1019 sc = device_get_softc(dev);
1020 mtx_lock(&sc->sc_msi_mtx);
1021
1022 for (i = 0; i < count; i++)
1023 clrbit(&sc->sc_msi_bitmap, irqs[i] - MSI_IRQ);
1024
1025 mtx_unlock(&sc->sc_msi_mtx);
1026 return (0);
1027 }
1028 #endif
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