The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

FreeBSD/Linux Kernel Cross Reference
sys/arm/mv/mv_pci.c

Version: -  FREEBSD  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-2  -  FREEBSD-11-1  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-4  -  FREEBSD-10-3  -  FREEBSD-10-2  -  FREEBSD-10-1  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-3  -  FREEBSD-9-2  -  FREEBSD-9-1  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-4  -  FREEBSD-8-3  -  FREEBSD-8-2  -  FREEBSD-8-1  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-4  -  FREEBSD-7-3  -  FREEBSD-7-2  -  FREEBSD-7-1  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-4  -  FREEBSD-6-3  -  FREEBSD-6-2  -  FREEBSD-6-1  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-5  -  FREEBSD-5-4  -  FREEBSD-5-3  -  FREEBSD-5-2  -  FREEBSD-5-1  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  linux-2.6  -  linux-2.4.22  -  MK83  -  MK84  -  PLAN9  -  DFBSD  -  NETBSD  -  NETBSD5  -  NETBSD4  -  NETBSD3  -  NETBSD20  -  OPENBSD  -  xnu-517  -  xnu-792  -  xnu-792.6.70  -  xnu-1228  -  xnu-1456.1.26  -  xnu-1699.24.8  -  xnu-2050.18.24  -  OPENSOLARIS  -  minix-3-1-1 
SearchContext: -  none  -  3  -  10 

    1 /*-
    2  * Copyright (c) 2008 MARVELL INTERNATIONAL LTD.
    3  * Copyright (c) 2010 The FreeBSD Foundation
    4  * Copyright (c) 2010-2015 Semihalf
    5  * All rights reserved.
    6  *
    7  * Developed by Semihalf.
    8  *
    9  * Portions of this software were developed by Semihalf
   10  * under sponsorship from the FreeBSD Foundation.
   11  *
   12  * Redistribution and use in source and binary forms, with or without
   13  * modification, are permitted provided that the following conditions
   14  * are met:
   15  * 1. Redistributions of source code must retain the above copyright
   16  *    notice, this list of conditions and the following disclaimer.
   17  * 2. Redistributions in binary form must reproduce the above copyright
   18  *    notice, this list of conditions and the following disclaimer in the
   19  *    documentation and/or other materials provided with the distribution.
   20  * 3. Neither the name of MARVELL nor the names of contributors
   21  *    may be used to endorse or promote products derived from this software
   22  *    without specific prior written permission.
   23  *
   24  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   27  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
   28  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   29  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   30  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   32  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   33  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   34  * SUCH DAMAGE.
   35  */
   36 
   37 /*
   38  * Marvell integrated PCI/PCI-Express controller driver.
   39  */
   40 
   41 #include <sys/cdefs.h>
   42 __FBSDID("$FreeBSD: releng/11.1/sys/arm/mv/mv_pci.c 298627 2016-04-26 11:53:37Z br $");
   43 
   44 #include <sys/param.h>
   45 #include <sys/systm.h>
   46 #include <sys/kernel.h>
   47 #include <sys/lock.h>
   48 #include <sys/malloc.h>
   49 #include <sys/module.h>
   50 #include <sys/mutex.h>
   51 #include <sys/queue.h>
   52 #include <sys/bus.h>
   53 #include <sys/rman.h>
   54 #include <sys/endian.h>
   55 #include <sys/devmap.h>
   56 
   57 #include <machine/fdt.h>
   58 #include <machine/intr.h>
   59 
   60 #include <vm/vm.h>
   61 #include <vm/pmap.h>
   62 
   63 #include <dev/fdt/fdt_common.h>
   64 #include <dev/ofw/ofw_bus.h>
   65 #include <dev/ofw/ofw_bus_subr.h>
   66 #include <dev/ofw/ofw_pci.h>
   67 #include <dev/pci/pcivar.h>
   68 #include <dev/pci/pcireg.h>
   69 #include <dev/pci/pcib_private.h>
   70 
   71 #include "ofw_bus_if.h"
   72 #include "pcib_if.h"
   73 
   74 #include <machine/resource.h>
   75 #include <machine/bus.h>
   76 
   77 #include <arm/mv/mvreg.h>
   78 #include <arm/mv/mvvar.h>
   79 #include <arm/mv/mvwin.h>
   80 
   81 #ifdef DEBUG
   82 #define debugf(fmt, args...) do { printf(fmt,##args); } while (0)
   83 #else
   84 #define debugf(fmt, args...)
   85 #endif
   86 
   87 /*
   88  * Code and data related to fdt-based PCI configuration.
   89  *
   90  * This stuff used to be in dev/fdt/fdt_pci.c and fdt_common.h, but it was
   91  * always Marvell-specific so that was deleted and the code now lives here.
   92  */
   93 
   94 struct mv_pci_range {
   95         u_long  base_pci;
   96         u_long  base_parent;
   97         u_long  len;
   98 };
   99 
  100 #define FDT_RANGES_CELLS        ((3 + 3 + 2) * 2)
  101 
  102 static void
  103 mv_pci_range_dump(struct mv_pci_range *range)
  104 {
  105 #ifdef DEBUG
  106         printf("\n");
  107         printf("  base_pci = 0x%08lx\n", range->base_pci);
  108         printf("  base_par = 0x%08lx\n", range->base_parent);
  109         printf("  len      = 0x%08lx\n", range->len);
  110 #endif
  111 }
  112 
  113 static int
  114 mv_pci_ranges_decode(phandle_t node, struct mv_pci_range *io_space,
  115     struct mv_pci_range *mem_space)
  116 {
  117         pcell_t ranges[FDT_RANGES_CELLS];
  118         struct mv_pci_range *pci_space;
  119         pcell_t addr_cells, size_cells, par_addr_cells;
  120         pcell_t *rangesptr;
  121         pcell_t cell0, cell1, cell2;
  122         int tuple_size, tuples, i, rv, offset_cells, len;
  123 
  124         /*
  125          * Retrieve 'ranges' property.
  126          */
  127         if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0)
  128                 return (EINVAL);
  129         if (addr_cells != 3 || size_cells != 2)
  130                 return (ERANGE);
  131 
  132         par_addr_cells = fdt_parent_addr_cells(node);
  133         if (par_addr_cells > 3)
  134                 return (ERANGE);
  135 
  136         len = OF_getproplen(node, "ranges");
  137         if (len > sizeof(ranges))
  138                 return (ENOMEM);
  139 
  140         if (OF_getprop(node, "ranges", ranges, sizeof(ranges)) <= 0)
  141                 return (EINVAL);
  142 
  143         tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells +
  144             size_cells);
  145         tuples = len / tuple_size;
  146 
  147         /*
  148          * Initialize the ranges so that we don't have to worry about
  149          * having them all defined in the FDT. In particular, it is
  150          * perfectly fine not to want I/O space on PCI busses.
  151          */
  152         bzero(io_space, sizeof(*io_space));
  153         bzero(mem_space, sizeof(*mem_space));
  154 
  155         rangesptr = &ranges[0];
  156         offset_cells = 0;
  157         for (i = 0; i < tuples; i++) {
  158                 cell0 = fdt_data_get((void *)rangesptr, 1);
  159                 rangesptr++;
  160                 cell1 = fdt_data_get((void *)rangesptr, 1);
  161                 rangesptr++;
  162                 cell2 = fdt_data_get((void *)rangesptr, 1);
  163                 rangesptr++;
  164 
  165                 if (cell0 & 0x02000000) {
  166                         pci_space = mem_space;
  167                 } else if (cell0 & 0x01000000) {
  168                         pci_space = io_space;
  169                 } else {
  170                         rv = ERANGE;
  171                         goto out;
  172                 }
  173 
  174                 if (par_addr_cells == 3) {
  175                         /*
  176                          * This is a PCI subnode 'ranges'. Skip cell0 and
  177                          * cell1 of this entry and only use cell2.
  178                          */
  179                         offset_cells = 2;
  180                         rangesptr += offset_cells;
  181                 }
  182 
  183                 if ((par_addr_cells - offset_cells) > 2) {
  184                         rv = ERANGE;
  185                         goto out;
  186                 }
  187                 pci_space->base_parent = fdt_data_get((void *)rangesptr,
  188                     par_addr_cells - offset_cells);
  189                 rangesptr += par_addr_cells - offset_cells;
  190 
  191                 if (size_cells > 2) {
  192                         rv = ERANGE;
  193                         goto out;
  194                 }
  195                 pci_space->len = fdt_data_get((void *)rangesptr, size_cells);
  196                 rangesptr += size_cells;
  197 
  198                 pci_space->base_pci = cell2;
  199         }
  200         rv = 0;
  201 out:
  202         return (rv);
  203 }
  204 
  205 static int
  206 mv_pci_ranges(phandle_t node, struct mv_pci_range *io_space,
  207     struct mv_pci_range *mem_space)
  208 {
  209         int err;
  210 
  211         debugf("Processing PCI node: %x\n", node);
  212         if ((err = mv_pci_ranges_decode(node, io_space, mem_space)) != 0) {
  213                 debugf("could not decode parent PCI node 'ranges'\n");
  214                 return (err);
  215         }
  216 
  217         debugf("Post fixup dump:\n");
  218         mv_pci_range_dump(io_space);
  219         mv_pci_range_dump(mem_space);
  220         return (0);
  221 }
  222 
  223 int
  224 mv_pci_devmap(phandle_t node, struct devmap_entry *devmap, vm_offset_t io_va,
  225     vm_offset_t mem_va)
  226 {
  227         struct mv_pci_range io_space, mem_space;
  228         int error;
  229 
  230         if ((error = mv_pci_ranges_decode(node, &io_space, &mem_space)) != 0)
  231                 return (error);
  232 
  233         devmap->pd_va = (io_va ? io_va : io_space.base_parent);
  234         devmap->pd_pa = io_space.base_parent;
  235         devmap->pd_size = io_space.len;
  236         devmap++;
  237 
  238         devmap->pd_va = (mem_va ? mem_va : mem_space.base_parent);
  239         devmap->pd_pa = mem_space.base_parent;
  240         devmap->pd_size = mem_space.len;
  241         return (0);
  242 }
  243 
  244 /*
  245  * Code and data related to the Marvell pcib driver.
  246  */
  247 
  248 #define PCI_CFG_ENA             (1U << 31)
  249 #define PCI_CFG_BUS(bus)        (((bus) & 0xff) << 16)
  250 #define PCI_CFG_DEV(dev)        (((dev) & 0x1f) << 11)
  251 #define PCI_CFG_FUN(fun)        (((fun) & 0x7) << 8)
  252 #define PCI_CFG_PCIE_REG(reg)   ((reg) & 0xfc)
  253 
  254 #define PCI_REG_CFG_ADDR        0x0C78
  255 #define PCI_REG_CFG_DATA        0x0C7C
  256 
  257 #define PCIE_REG_CFG_ADDR       0x18F8
  258 #define PCIE_REG_CFG_DATA       0x18FC
  259 #define PCIE_REG_CONTROL        0x1A00
  260 #define   PCIE_CTRL_LINK1X      0x00000001
  261 #define PCIE_REG_STATUS         0x1A04
  262 #define PCIE_REG_IRQ_MASK       0x1910
  263 
  264 #define PCIE_CONTROL_ROOT_CMPLX (1 << 1)
  265 #define PCIE_CONTROL_HOT_RESET  (1 << 24)
  266 
  267 #define PCIE_LINK_TIMEOUT       1000000
  268 
  269 #define PCIE_STATUS_LINK_DOWN   1
  270 #define PCIE_STATUS_DEV_OFFS    16
  271 
  272 /* Minimum PCI Memory and I/O allocations taken from PCI spec (in bytes) */
  273 #define PCI_MIN_IO_ALLOC        4
  274 #define PCI_MIN_MEM_ALLOC       16
  275 
  276 #define BITS_PER_UINT32         (NBBY * sizeof(uint32_t))
  277 
  278 struct mv_pcib_softc {
  279         device_t        sc_dev;
  280 
  281         struct rman     sc_mem_rman;
  282         bus_addr_t      sc_mem_base;
  283         bus_addr_t      sc_mem_size;
  284         uint32_t        sc_mem_map[MV_PCI_MEM_SLICE_SIZE /
  285             (PCI_MIN_MEM_ALLOC * BITS_PER_UINT32)];
  286         int             sc_win_target;
  287         int             sc_mem_win_attr;
  288 
  289         struct rman     sc_io_rman;
  290         bus_addr_t      sc_io_base;
  291         bus_addr_t      sc_io_size;
  292         uint32_t        sc_io_map[MV_PCI_IO_SLICE_SIZE /
  293             (PCI_MIN_IO_ALLOC * BITS_PER_UINT32)];
  294         int             sc_io_win_attr;
  295 
  296         struct resource *sc_res;
  297         bus_space_handle_t sc_bsh;
  298         bus_space_tag_t sc_bst;
  299         int             sc_rid;
  300 
  301         struct mtx      sc_msi_mtx;
  302         uint32_t        sc_msi_bitmap;
  303 
  304         int             sc_busnr;               /* Host bridge bus number */
  305         int             sc_devnr;               /* Host bridge device number */
  306         int             sc_type;
  307         int             sc_mode;                /* Endpoint / Root Complex */
  308 
  309         struct ofw_bus_iinfo    sc_pci_iinfo;
  310 };
  311 
  312 /* Local forward prototypes */
  313 static int mv_pcib_decode_win(phandle_t, struct mv_pcib_softc *);
  314 static void mv_pcib_hw_cfginit(void);
  315 static uint32_t mv_pcib_hw_cfgread(struct mv_pcib_softc *, u_int, u_int,
  316     u_int, u_int, int);
  317 static void mv_pcib_hw_cfgwrite(struct mv_pcib_softc *, u_int, u_int,
  318     u_int, u_int, uint32_t, int);
  319 static int mv_pcib_init(struct mv_pcib_softc *, int, int);
  320 static int mv_pcib_init_all_bars(struct mv_pcib_softc *, int, int, int, int);
  321 static void mv_pcib_init_bridge(struct mv_pcib_softc *, int, int, int);
  322 static inline void pcib_write_irq_mask(struct mv_pcib_softc *, uint32_t);
  323 static void mv_pcib_enable(struct mv_pcib_softc *, uint32_t);
  324 static int mv_pcib_mem_init(struct mv_pcib_softc *);
  325 
  326 /* Forward prototypes */
  327 static int mv_pcib_probe(device_t);
  328 static int mv_pcib_attach(device_t);
  329 
  330 static struct resource *mv_pcib_alloc_resource(device_t, device_t, int, int *,
  331     rman_res_t, rman_res_t, rman_res_t, u_int);
  332 static int mv_pcib_release_resource(device_t, device_t, int, int,
  333     struct resource *);
  334 static int mv_pcib_read_ivar(device_t, device_t, int, uintptr_t *);
  335 static int mv_pcib_write_ivar(device_t, device_t, int, uintptr_t);
  336 
  337 static int mv_pcib_maxslots(device_t);
  338 static uint32_t mv_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int);
  339 static void mv_pcib_write_config(device_t, u_int, u_int, u_int, u_int,
  340     uint32_t, int);
  341 static int mv_pcib_route_interrupt(device_t, device_t, int);
  342 #if defined(SOC_MV_ARMADAXP)
  343 static int mv_pcib_alloc_msi(device_t, device_t, int, int, int *);
  344 static int mv_pcib_map_msi(device_t, device_t, int, uint64_t *, uint32_t *);
  345 static int mv_pcib_release_msi(device_t, device_t, int, int *);
  346 #endif
  347 
  348 /*
  349  * Bus interface definitions.
  350  */
  351 static device_method_t mv_pcib_methods[] = {
  352         /* Device interface */
  353         DEVMETHOD(device_probe,                 mv_pcib_probe),
  354         DEVMETHOD(device_attach,                mv_pcib_attach),
  355 
  356         /* Bus interface */
  357         DEVMETHOD(bus_read_ivar,                mv_pcib_read_ivar),
  358         DEVMETHOD(bus_write_ivar,               mv_pcib_write_ivar),
  359         DEVMETHOD(bus_alloc_resource,           mv_pcib_alloc_resource),
  360         DEVMETHOD(bus_release_resource,         mv_pcib_release_resource),
  361         DEVMETHOD(bus_activate_resource,        bus_generic_activate_resource),
  362         DEVMETHOD(bus_deactivate_resource,      bus_generic_deactivate_resource),
  363         DEVMETHOD(bus_setup_intr,               bus_generic_setup_intr),
  364         DEVMETHOD(bus_teardown_intr,            bus_generic_teardown_intr),
  365 
  366         /* pcib interface */
  367         DEVMETHOD(pcib_maxslots,                mv_pcib_maxslots),
  368         DEVMETHOD(pcib_read_config,             mv_pcib_read_config),
  369         DEVMETHOD(pcib_write_config,            mv_pcib_write_config),
  370         DEVMETHOD(pcib_route_interrupt,         mv_pcib_route_interrupt),
  371 
  372 #if defined(SOC_MV_ARMADAXP)
  373         DEVMETHOD(pcib_alloc_msi,               mv_pcib_alloc_msi),
  374         DEVMETHOD(pcib_release_msi,             mv_pcib_release_msi),
  375         DEVMETHOD(pcib_map_msi,                 mv_pcib_map_msi),
  376 #endif
  377 
  378         /* OFW bus interface */
  379         DEVMETHOD(ofw_bus_get_compat,   ofw_bus_gen_get_compat),
  380         DEVMETHOD(ofw_bus_get_model,    ofw_bus_gen_get_model),
  381         DEVMETHOD(ofw_bus_get_name,     ofw_bus_gen_get_name),
  382         DEVMETHOD(ofw_bus_get_node,     ofw_bus_gen_get_node),
  383         DEVMETHOD(ofw_bus_get_type,     ofw_bus_gen_get_type),
  384 
  385         DEVMETHOD_END
  386 };
  387 
  388 static driver_t mv_pcib_driver = {
  389         "pcib",
  390         mv_pcib_methods,
  391         sizeof(struct mv_pcib_softc),
  392 };
  393 
  394 devclass_t pcib_devclass;
  395 
  396 DRIVER_MODULE(pcib, ofwbus, mv_pcib_driver, pcib_devclass, 0, 0);
  397 
  398 static struct mtx pcicfg_mtx;
  399 
  400 static int
  401 mv_pcib_probe(device_t self)
  402 {
  403         phandle_t node;
  404 
  405         node = ofw_bus_get_node(self);
  406         if (!fdt_is_type(node, "pci"))
  407                 return (ENXIO);
  408 
  409         if (!(ofw_bus_is_compatible(self, "mrvl,pcie") ||
  410             ofw_bus_is_compatible(self, "mrvl,pci")))
  411                 return (ENXIO);
  412 
  413         device_set_desc(self, "Marvell Integrated PCI/PCI-E Controller");
  414         return (BUS_PROBE_DEFAULT);
  415 }
  416 
  417 static int
  418 mv_pcib_attach(device_t self)
  419 {
  420         struct mv_pcib_softc *sc;
  421         phandle_t node, parnode;
  422         uint32_t val, unit;
  423         int err;
  424 
  425         sc = device_get_softc(self);
  426         sc->sc_dev = self;
  427         unit = fdt_get_unit(self);
  428 
  429 
  430         node = ofw_bus_get_node(self);
  431         parnode = OF_parent(node);
  432         if (fdt_is_compatible(node, "mrvl,pcie")) {
  433                 sc->sc_type = MV_TYPE_PCIE;
  434                 sc->sc_win_target = MV_WIN_PCIE_TARGET(unit);
  435                 sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR(unit);
  436                 sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR(unit);
  437         } else if (fdt_is_compatible(node, "mrvl,pci")) {
  438                 sc->sc_type = MV_TYPE_PCI;
  439                 sc->sc_win_target = MV_WIN_PCI_TARGET;
  440                 sc->sc_mem_win_attr = MV_WIN_PCI_MEM_ATTR;
  441                 sc->sc_io_win_attr = MV_WIN_PCI_IO_ATTR;
  442         } else
  443                 return (ENXIO);
  444 
  445         /*
  446          * Retrieve our mem-mapped registers range.
  447          */
  448         sc->sc_rid = 0;
  449         sc->sc_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &sc->sc_rid,
  450             RF_ACTIVE);
  451         if (sc->sc_res == NULL) {
  452                 device_printf(self, "could not map memory\n");
  453                 return (ENXIO);
  454         }
  455         sc->sc_bst = rman_get_bustag(sc->sc_res);
  456         sc->sc_bsh = rman_get_bushandle(sc->sc_res);
  457 
  458         val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_CONTROL);
  459         sc->sc_mode = (val & PCIE_CONTROL_ROOT_CMPLX ? MV_MODE_ROOT :
  460             MV_MODE_ENDPOINT);
  461 
  462         /*
  463          * Get PCI interrupt info.
  464          */
  465         if (sc->sc_mode == MV_MODE_ROOT)
  466                 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(pcell_t));
  467 
  468         /*
  469          * Configure decode windows for PCI(E) access.
  470          */
  471         if (mv_pcib_decode_win(node, sc) != 0)
  472                 return (ENXIO);
  473 
  474         mv_pcib_hw_cfginit();
  475 
  476         /*
  477          * Enable PCIE device.
  478          */
  479         mv_pcib_enable(sc, unit);
  480 
  481         /*
  482          * Memory management.
  483          */
  484         err = mv_pcib_mem_init(sc);
  485         if (err)
  486                 return (err);
  487 
  488         if (sc->sc_mode == MV_MODE_ROOT) {
  489                 err = mv_pcib_init(sc, sc->sc_busnr,
  490                     mv_pcib_maxslots(sc->sc_dev));
  491                 if (err)
  492                         goto error;
  493 
  494                 device_add_child(self, "pci", -1);
  495         } else {
  496                 sc->sc_devnr = 1;
  497                 bus_space_write_4(sc->sc_bst, sc->sc_bsh,
  498                     PCIE_REG_STATUS, 1 << PCIE_STATUS_DEV_OFFS);
  499                 device_add_child(self, "pci_ep", -1);
  500         }
  501 
  502         mtx_init(&sc->sc_msi_mtx, "msi_mtx", NULL, MTX_DEF);
  503         return (bus_generic_attach(self));
  504 
  505 error:
  506         /* XXX SYS_RES_ should be released here */
  507         rman_fini(&sc->sc_mem_rman);
  508         rman_fini(&sc->sc_io_rman);
  509 
  510         return (err);
  511 }
  512 
  513 static void
  514 mv_pcib_enable(struct mv_pcib_softc *sc, uint32_t unit)
  515 {
  516         uint32_t val;
  517 #if !defined(SOC_MV_ARMADAXP)
  518         int timeout;
  519 
  520         /*
  521          * Check if PCIE device is enabled.
  522          */
  523         if (read_cpu_ctrl(CPU_CONTROL) & CPU_CONTROL_PCIE_DISABLE(unit)) {
  524                 write_cpu_ctrl(CPU_CONTROL, read_cpu_ctrl(CPU_CONTROL) &
  525                     ~(CPU_CONTROL_PCIE_DISABLE(unit)));
  526 
  527                 timeout = PCIE_LINK_TIMEOUT;
  528                 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
  529                     PCIE_REG_STATUS);
  530                 while (((val & PCIE_STATUS_LINK_DOWN) == 1) && (timeout > 0)) {
  531                         DELAY(1000);
  532                         timeout -= 1000;
  533                         val = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
  534                             PCIE_REG_STATUS);
  535                 }
  536         }
  537 #endif
  538 
  539 
  540         if (sc->sc_mode == MV_MODE_ROOT) {
  541                 /*
  542                  * Enable PCI bridge.
  543                  */
  544                 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND);
  545                 val |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN |
  546                     PCIM_CMD_MEMEN | PCIM_CMD_PORTEN;
  547                 bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND, val);
  548         }
  549 }
  550 
  551 static int
  552 mv_pcib_mem_init(struct mv_pcib_softc *sc)
  553 {
  554         int err;
  555 
  556         /*
  557          * Memory management.
  558          */
  559         sc->sc_mem_rman.rm_type = RMAN_ARRAY;
  560         err = rman_init(&sc->sc_mem_rman);
  561         if (err)
  562                 return (err);
  563 
  564         sc->sc_io_rman.rm_type = RMAN_ARRAY;
  565         err = rman_init(&sc->sc_io_rman);
  566         if (err) {
  567                 rman_fini(&sc->sc_mem_rman);
  568                 return (err);
  569         }
  570 
  571         err = rman_manage_region(&sc->sc_mem_rman, sc->sc_mem_base,
  572             sc->sc_mem_base + sc->sc_mem_size - 1);
  573         if (err)
  574                 goto error;
  575 
  576         err = rman_manage_region(&sc->sc_io_rman, sc->sc_io_base,
  577             sc->sc_io_base + sc->sc_io_size - 1);
  578         if (err)
  579                 goto error;
  580 
  581         return (0);
  582 
  583 error:
  584         rman_fini(&sc->sc_mem_rman);
  585         rman_fini(&sc->sc_io_rman);
  586 
  587         return (err);
  588 }
  589 
  590 static inline uint32_t
  591 pcib_bit_get(uint32_t *map, uint32_t bit)
  592 {
  593         uint32_t n = bit / BITS_PER_UINT32;
  594 
  595         bit = bit % BITS_PER_UINT32;
  596         return (map[n] & (1 << bit));
  597 }
  598 
  599 static inline void
  600 pcib_bit_set(uint32_t *map, uint32_t bit)
  601 {
  602         uint32_t n = bit / BITS_PER_UINT32;
  603 
  604         bit = bit % BITS_PER_UINT32;
  605         map[n] |= (1 << bit);
  606 }
  607 
  608 static inline uint32_t
  609 pcib_map_check(uint32_t *map, uint32_t start, uint32_t bits)
  610 {
  611         uint32_t i;
  612 
  613         for (i = start; i < start + bits; i++)
  614                 if (pcib_bit_get(map, i))
  615                         return (0);
  616 
  617         return (1);
  618 }
  619 
  620 static inline void
  621 pcib_map_set(uint32_t *map, uint32_t start, uint32_t bits)
  622 {
  623         uint32_t i;
  624 
  625         for (i = start; i < start + bits; i++)
  626                 pcib_bit_set(map, i);
  627 }
  628 
  629 /*
  630  * The idea of this allocator is taken from ARM No-Cache memory
  631  * management code (sys/arm/arm/vm_machdep.c).
  632  */
  633 static bus_addr_t
  634 pcib_alloc(struct mv_pcib_softc *sc, uint32_t smask)
  635 {
  636         uint32_t bits, bits_limit, i, *map, min_alloc, size;
  637         bus_addr_t addr = 0;
  638         bus_addr_t base;
  639 
  640         if (smask & 1) {
  641                 base = sc->sc_io_base;
  642                 min_alloc = PCI_MIN_IO_ALLOC;
  643                 bits_limit = sc->sc_io_size / min_alloc;
  644                 map = sc->sc_io_map;
  645                 smask &= ~0x3;
  646         } else {
  647                 base = sc->sc_mem_base;
  648                 min_alloc = PCI_MIN_MEM_ALLOC;
  649                 bits_limit = sc->sc_mem_size / min_alloc;
  650                 map = sc->sc_mem_map;
  651                 smask &= ~0xF;
  652         }
  653 
  654         size = ~smask + 1;
  655         bits = size / min_alloc;
  656 
  657         for (i = 0; i + bits <= bits_limit; i += bits)
  658                 if (pcib_map_check(map, i, bits)) {
  659                         pcib_map_set(map, i, bits);
  660                         addr = base + (i * min_alloc);
  661                         return (addr);
  662                 }
  663 
  664         return (addr);
  665 }
  666 
  667 static int
  668 mv_pcib_init_bar(struct mv_pcib_softc *sc, int bus, int slot, int func,
  669     int barno)
  670 {
  671         uint32_t addr, bar;
  672         int reg, width;
  673 
  674         reg = PCIR_BAR(barno);
  675 
  676         /*
  677          * Need to init the BAR register with 0xffffffff before correct
  678          * value can be read.
  679          */
  680         mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4);
  681         bar = mv_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4);
  682         if (bar == 0)
  683                 return (1);
  684 
  685         /* Calculate BAR size: 64 or 32 bit (in 32-bit units) */
  686         width = ((bar & 7) == 4) ? 2 : 1;
  687 
  688         addr = pcib_alloc(sc, bar);
  689         if (!addr)
  690                 return (-1);
  691 
  692         if (bootverbose)
  693                 printf("PCI %u:%u:%u: reg %x: smask=%08x: addr=%08x\n",
  694                     bus, slot, func, reg, bar, addr);
  695 
  696         mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4);
  697         if (width == 2)
  698                 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg + 4,
  699                     0, 4);
  700 
  701         return (width);
  702 }
  703 
  704 static void
  705 mv_pcib_init_bridge(struct mv_pcib_softc *sc, int bus, int slot, int func)
  706 {
  707         bus_addr_t io_base, mem_base;
  708         uint32_t io_limit, mem_limit;
  709         int secbus;
  710 
  711         io_base = sc->sc_io_base;
  712         io_limit = io_base + sc->sc_io_size - 1;
  713         mem_base = sc->sc_mem_base;
  714         mem_limit = mem_base + sc->sc_mem_size - 1;
  715 
  716         /* Configure I/O decode registers */
  717         mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEL_1,
  718             io_base >> 8, 1);
  719         mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEH_1,
  720             io_base >> 16, 2);
  721         mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITL_1,
  722             io_limit >> 8, 1);
  723         mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITH_1,
  724             io_limit >> 16, 2);
  725 
  726         /* Configure memory decode registers */
  727         mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMBASE_1,
  728             mem_base >> 16, 2);
  729         mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMLIMIT_1,
  730             mem_limit >> 16, 2);
  731 
  732         /* Disable memory prefetch decode */
  733         mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEL_1,
  734             0x10, 2);
  735         mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEH_1,
  736             0x0, 4);
  737         mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITL_1,
  738             0xF, 2);
  739         mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITH_1,
  740             0x0, 4);
  741 
  742         secbus = mv_pcib_read_config(sc->sc_dev, bus, slot, func,
  743             PCIR_SECBUS_1, 1);
  744 
  745         /* Configure buses behind the bridge */
  746         mv_pcib_init(sc, secbus, PCI_SLOTMAX);
  747 }
  748 
  749 static int
  750 mv_pcib_init(struct mv_pcib_softc *sc, int bus, int maxslot)
  751 {
  752         int slot, func, maxfunc, error;
  753         uint8_t hdrtype, command, class, subclass;
  754 
  755         for (slot = 0; slot <= maxslot; slot++) {
  756                 maxfunc = 0;
  757                 for (func = 0; func <= maxfunc; func++) {
  758                         hdrtype = mv_pcib_read_config(sc->sc_dev, bus, slot,
  759                             func, PCIR_HDRTYPE, 1);
  760 
  761                         if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
  762                                 continue;
  763 
  764                         if (func == 0 && (hdrtype & PCIM_MFDEV))
  765                                 maxfunc = PCI_FUNCMAX;
  766 
  767                         command = mv_pcib_read_config(sc->sc_dev, bus, slot,
  768                             func, PCIR_COMMAND, 1);
  769                         command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN);
  770                         mv_pcib_write_config(sc->sc_dev, bus, slot, func,
  771                             PCIR_COMMAND, command, 1);
  772 
  773                         error = mv_pcib_init_all_bars(sc, bus, slot, func,
  774                             hdrtype);
  775 
  776                         if (error)
  777                                 return (error);
  778 
  779                         command |= PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN |
  780                             PCIM_CMD_PORTEN;
  781                         mv_pcib_write_config(sc->sc_dev, bus, slot, func,
  782                             PCIR_COMMAND, command, 1);
  783 
  784                         /* Handle PCI-PCI bridges */
  785                         class = mv_pcib_read_config(sc->sc_dev, bus, slot,
  786                             func, PCIR_CLASS, 1);
  787                         subclass = mv_pcib_read_config(sc->sc_dev, bus, slot,
  788                             func, PCIR_SUBCLASS, 1);
  789 
  790                         if (class != PCIC_BRIDGE ||
  791                             subclass != PCIS_BRIDGE_PCI)
  792                                 continue;
  793 
  794                         mv_pcib_init_bridge(sc, bus, slot, func);
  795                 }
  796         }
  797 
  798         /* Enable all ABCD interrupts */
  799         pcib_write_irq_mask(sc, (0xF << 24));
  800 
  801         return (0);
  802 }
  803 
  804 static int
  805 mv_pcib_init_all_bars(struct mv_pcib_softc *sc, int bus, int slot,
  806     int func, int hdrtype)
  807 {
  808         int maxbar, bar, i;
  809 
  810         maxbar = (hdrtype & PCIM_HDRTYPE) ? 0 : 6;
  811         bar = 0;
  812 
  813         /* Program the base address registers */
  814         while (bar < maxbar) {
  815                 i = mv_pcib_init_bar(sc, bus, slot, func, bar);
  816                 bar += i;
  817                 if (i < 0) {
  818                         device_printf(sc->sc_dev,
  819                             "PCI IO/Memory space exhausted\n");
  820                         return (ENOMEM);
  821                 }
  822         }
  823 
  824         return (0);
  825 }
  826 
  827 static struct resource *
  828 mv_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
  829     rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
  830 {
  831         struct mv_pcib_softc *sc = device_get_softc(dev);
  832         struct rman *rm = NULL;
  833         struct resource *res;
  834 
  835         switch (type) {
  836         case SYS_RES_IOPORT:
  837                 rm = &sc->sc_io_rman;
  838                 break;
  839         case SYS_RES_MEMORY:
  840                 rm = &sc->sc_mem_rman;
  841                 break;
  842         default:
  843                 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
  844                     type, rid, start, end, count, flags));
  845         }
  846 
  847         if (RMAN_IS_DEFAULT_RANGE(start, end)) {
  848                 start = sc->sc_mem_base;
  849                 end = sc->sc_mem_base + sc->sc_mem_size - 1;
  850                 count = sc->sc_mem_size;
  851         }
  852 
  853         if ((start < sc->sc_mem_base) || (start + count - 1 != end) ||
  854             (end > sc->sc_mem_base + sc->sc_mem_size - 1))
  855                 return (NULL);
  856 
  857         res = rman_reserve_resource(rm, start, end, count, flags, child);
  858         if (res == NULL)
  859                 return (NULL);
  860 
  861         rman_set_rid(res, *rid);
  862         rman_set_bustag(res, fdtbus_bs_tag);
  863         rman_set_bushandle(res, start);
  864 
  865         if (flags & RF_ACTIVE)
  866                 if (bus_activate_resource(child, type, *rid, res)) {
  867                         rman_release_resource(res);
  868                         return (NULL);
  869                 }
  870 
  871         return (res);
  872 }
  873 
  874 static int
  875 mv_pcib_release_resource(device_t dev, device_t child, int type, int rid,
  876     struct resource *res)
  877 {
  878 
  879         if (type != SYS_RES_IOPORT && type != SYS_RES_MEMORY)
  880                 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
  881                     type, rid, res));
  882 
  883         return (rman_release_resource(res));
  884 }
  885 
  886 static int
  887 mv_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
  888 {
  889         struct mv_pcib_softc *sc = device_get_softc(dev);
  890 
  891         switch (which) {
  892         case PCIB_IVAR_BUS:
  893                 *result = sc->sc_busnr;
  894                 return (0);
  895         case PCIB_IVAR_DOMAIN:
  896                 *result = device_get_unit(dev);
  897                 return (0);
  898         }
  899 
  900         return (ENOENT);
  901 }
  902 
  903 static int
  904 mv_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
  905 {
  906         struct mv_pcib_softc *sc = device_get_softc(dev);
  907 
  908         switch (which) {
  909         case PCIB_IVAR_BUS:
  910                 sc->sc_busnr = value;
  911                 return (0);
  912         }
  913 
  914         return (ENOENT);
  915 }
  916 
  917 static inline void
  918 pcib_write_irq_mask(struct mv_pcib_softc *sc, uint32_t mask)
  919 {
  920 
  921         if (sc->sc_type != MV_TYPE_PCI)
  922                 return;
  923 
  924         bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_IRQ_MASK, mask);
  925 }
  926 
  927 static void
  928 mv_pcib_hw_cfginit(void)
  929 {
  930         static int opened = 0;
  931 
  932         if (opened)
  933                 return;
  934 
  935         mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
  936         opened = 1;
  937 }
  938 
  939 static uint32_t
  940 mv_pcib_hw_cfgread(struct mv_pcib_softc *sc, u_int bus, u_int slot,
  941     u_int func, u_int reg, int bytes)
  942 {
  943         uint32_t addr, data, ca, cd;
  944 
  945         ca = (sc->sc_type != MV_TYPE_PCI) ?
  946             PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR;
  947         cd = (sc->sc_type != MV_TYPE_PCI) ?
  948             PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA;
  949         addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) |
  950             PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg);
  951 
  952         mtx_lock_spin(&pcicfg_mtx);
  953         bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr);
  954 
  955         data = ~0;
  956         switch (bytes) {
  957         case 1:
  958                 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh,
  959                     cd + (reg & 3));
  960                 break;
  961         case 2:
  962                 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh,
  963                     cd + (reg & 2)));
  964                 break;
  965         case 4:
  966                 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh,
  967                     cd));
  968                 break;
  969         }
  970         mtx_unlock_spin(&pcicfg_mtx);
  971         return (data);
  972 }
  973 
  974 static void
  975 mv_pcib_hw_cfgwrite(struct mv_pcib_softc *sc, u_int bus, u_int slot,
  976     u_int func, u_int reg, uint32_t data, int bytes)
  977 {
  978         uint32_t addr, ca, cd;
  979 
  980         ca = (sc->sc_type != MV_TYPE_PCI) ?
  981             PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR;
  982         cd = (sc->sc_type != MV_TYPE_PCI) ?
  983             PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA;
  984         addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) |
  985             PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg);
  986 
  987         mtx_lock_spin(&pcicfg_mtx);
  988         bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr);
  989 
  990         switch (bytes) {
  991         case 1:
  992                 bus_space_write_1(sc->sc_bst, sc->sc_bsh,
  993                     cd + (reg & 3), data);
  994                 break;
  995         case 2:
  996                 bus_space_write_2(sc->sc_bst, sc->sc_bsh,
  997                     cd + (reg & 2), htole16(data));
  998                 break;
  999         case 4:
 1000                 bus_space_write_4(sc->sc_bst, sc->sc_bsh,
 1001                     cd, htole32(data));
 1002                 break;
 1003         }
 1004         mtx_unlock_spin(&pcicfg_mtx);
 1005 }
 1006 
 1007 static int
 1008 mv_pcib_maxslots(device_t dev)
 1009 {
 1010         struct mv_pcib_softc *sc = device_get_softc(dev);
 1011 
 1012         return ((sc->sc_type != MV_TYPE_PCI) ? 1 : PCI_SLOTMAX);
 1013 }
 1014 
 1015 static int
 1016 mv_pcib_root_slot(device_t dev, u_int bus, u_int slot, u_int func)
 1017 {
 1018 #if defined(SOC_MV_ARMADA38X)
 1019         struct mv_pcib_softc *sc = device_get_softc(dev);
 1020         uint32_t vendor, device;
 1021 
 1022         vendor = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_VENDOR,
 1023             PCIR_VENDOR_LENGTH);
 1024         device = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_DEVICE,
 1025             PCIR_DEVICE_LENGTH) & MV_DEV_FAMILY_MASK;
 1026 
 1027         return (vendor == PCI_VENDORID_MRVL && device == MV_DEV_ARMADA38X);
 1028 #else
 1029         /* On platforms other than Armada38x, root link is always at slot 0 */
 1030         return (slot == 0);
 1031 #endif
 1032 }
 1033 
 1034 static uint32_t
 1035 mv_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
 1036     u_int reg, int bytes)
 1037 {
 1038         struct mv_pcib_softc *sc = device_get_softc(dev);
 1039 
 1040         /* Return ~0 if link is inactive or trying to read from Root */
 1041         if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) &
 1042             PCIE_STATUS_LINK_DOWN) || mv_pcib_root_slot(dev, bus, slot, func))
 1043                 return (~0U);
 1044 
 1045         return (mv_pcib_hw_cfgread(sc, bus, slot, func, reg, bytes));
 1046 }
 1047 
 1048 static void
 1049 mv_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
 1050     u_int reg, uint32_t val, int bytes)
 1051 {
 1052         struct mv_pcib_softc *sc = device_get_softc(dev);
 1053 
 1054         /* Return if link is inactive or trying to write to Root */
 1055         if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) &
 1056             PCIE_STATUS_LINK_DOWN) || mv_pcib_root_slot(dev, bus, slot, func))
 1057                 return;
 1058 
 1059         mv_pcib_hw_cfgwrite(sc, bus, slot, func, reg, val, bytes);
 1060 }
 1061 
 1062 static int
 1063 mv_pcib_route_interrupt(device_t bus, device_t dev, int pin)
 1064 {
 1065         struct mv_pcib_softc *sc;
 1066         struct ofw_pci_register reg;
 1067         uint32_t pintr, mintr[4];
 1068         int icells;
 1069         phandle_t iparent;
 1070 
 1071         sc = device_get_softc(bus);
 1072         pintr = pin;
 1073 
 1074         /* Fabricate imap information in case this isn't an OFW device */
 1075         bzero(&reg, sizeof(reg));
 1076         reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) |
 1077             (pci_get_slot(dev) << OFW_PCI_PHYS_HI_DEVICESHIFT) |
 1078             (pci_get_function(dev) << OFW_PCI_PHYS_HI_FUNCTIONSHIFT);
 1079 
 1080         icells = ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo,
 1081             &reg, sizeof(reg), &pintr, sizeof(pintr), mintr, sizeof(mintr),
 1082             &iparent);
 1083         if (icells > 0)
 1084                 return (ofw_bus_map_intr(dev, iparent, icells, mintr));
 1085 
 1086         /* Maybe it's a real interrupt, not an intpin */
 1087         if (pin > 4)
 1088                 return (pin);
 1089 
 1090         device_printf(bus, "could not route pin %d for device %d.%d\n",
 1091             pin, pci_get_slot(dev), pci_get_function(dev));
 1092         return (PCI_INVALID_IRQ);
 1093 }
 1094 
 1095 static int
 1096 mv_pcib_decode_win(phandle_t node, struct mv_pcib_softc *sc)
 1097 {
 1098         struct mv_pci_range io_space, mem_space;
 1099         device_t dev;
 1100         int error;
 1101 
 1102         dev = sc->sc_dev;
 1103 
 1104         if ((error = mv_pci_ranges(node, &io_space, &mem_space)) != 0) {
 1105                 device_printf(dev, "could not retrieve 'ranges' data\n");
 1106                 return (error);
 1107         }
 1108 
 1109         /* Configure CPU decoding windows */
 1110         error = decode_win_cpu_set(sc->sc_win_target,
 1111             sc->sc_io_win_attr, io_space.base_parent, io_space.len, ~0);
 1112         if (error < 0) {
 1113                 device_printf(dev, "could not set up CPU decode "
 1114                     "window for PCI IO\n");
 1115                 return (ENXIO);
 1116         }
 1117         error = decode_win_cpu_set(sc->sc_win_target,
 1118             sc->sc_mem_win_attr, mem_space.base_parent, mem_space.len,
 1119             mem_space.base_parent);
 1120         if (error < 0) {
 1121                 device_printf(dev, "could not set up CPU decode "
 1122                     "windows for PCI MEM\n");
 1123                 return (ENXIO);
 1124         }
 1125 
 1126         sc->sc_io_base = io_space.base_parent;
 1127         sc->sc_io_size = io_space.len;
 1128 
 1129         sc->sc_mem_base = mem_space.base_parent;
 1130         sc->sc_mem_size = mem_space.len;
 1131 
 1132         return (0);
 1133 }
 1134 
 1135 #if defined(SOC_MV_ARMADAXP)
 1136 static int
 1137 mv_pcib_map_msi(device_t dev, device_t child, int irq, uint64_t *addr,
 1138     uint32_t *data)
 1139 {
 1140         struct mv_pcib_softc *sc;
 1141 
 1142         sc = device_get_softc(dev);
 1143         irq = irq - MSI_IRQ;
 1144 
 1145         /* validate parameters */
 1146         if (isclr(&sc->sc_msi_bitmap, irq)) {
 1147                 device_printf(dev, "invalid MSI 0x%x\n", irq);
 1148                 return (EINVAL);
 1149         }
 1150 
 1151         mv_msi_data(irq, addr, data);
 1152 
 1153         debugf("%s: irq: %d addr: %jx data: %x\n",
 1154             __func__, irq, *addr, *data);
 1155 
 1156         return (0);
 1157 }
 1158 
 1159 static int
 1160 mv_pcib_alloc_msi(device_t dev, device_t child, int count,
 1161     int maxcount __unused, int *irqs)
 1162 {
 1163         struct mv_pcib_softc *sc;
 1164         u_int start = 0, i;
 1165 
 1166         if (powerof2(count) == 0 || count > MSI_IRQ_NUM)
 1167                 return (EINVAL);
 1168 
 1169         sc = device_get_softc(dev);
 1170         mtx_lock(&sc->sc_msi_mtx);
 1171 
 1172         for (start = 0; (start + count) < MSI_IRQ_NUM; start++) {
 1173                 for (i = start; i < start + count; i++) {
 1174                         if (isset(&sc->sc_msi_bitmap, i))
 1175                                 break;
 1176                 }
 1177                 if (i == start + count)
 1178                         break;
 1179         }
 1180 
 1181         if ((start + count) == MSI_IRQ_NUM) {
 1182                 mtx_unlock(&sc->sc_msi_mtx);
 1183                 return (ENXIO);
 1184         }
 1185 
 1186         for (i = start; i < start + count; i++) {
 1187                 setbit(&sc->sc_msi_bitmap, i);
 1188                 *irqs++ = MSI_IRQ + i;
 1189         }
 1190         debugf("%s: start: %x count: %x\n", __func__, start, count);
 1191 
 1192         mtx_unlock(&sc->sc_msi_mtx);
 1193         return (0);
 1194 }
 1195 
 1196 static int
 1197 mv_pcib_release_msi(device_t dev, device_t child, int count, int *irqs)
 1198 {
 1199         struct mv_pcib_softc *sc;
 1200         u_int i;
 1201 
 1202         sc = device_get_softc(dev);
 1203         mtx_lock(&sc->sc_msi_mtx);
 1204 
 1205         for (i = 0; i < count; i++)
 1206                 clrbit(&sc->sc_msi_bitmap, irqs[i] - MSI_IRQ);
 1207 
 1208         mtx_unlock(&sc->sc_msi_mtx);
 1209         return (0);
 1210 }
 1211 #endif
 1212 

Cache object: e89fbf2b554f27ee808a3025c88b0e38


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]


This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.