FreeBSD/Linux Kernel Cross Reference
sys/arm/mv/mv_pci.c
1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright (c) 2008 MARVELL INTERNATIONAL LTD.
5 * Copyright (c) 2010 The FreeBSD Foundation
6 * Copyright (c) 2010-2015 Semihalf
7 * All rights reserved.
8 *
9 * Developed by Semihalf.
10 *
11 * Portions of this software were developed by Semihalf
12 * under sponsorship from the FreeBSD Foundation.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 * 3. Neither the name of MARVELL nor the names of contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * SUCH DAMAGE.
37 */
38
39 /*
40 * Marvell integrated PCI/PCI-Express controller driver.
41 */
42
43 #include <sys/cdefs.h>
44 __FBSDID("$FreeBSD: releng/12.0/sys/arm/mv/mv_pci.c 332274 2018-04-08 12:20:06Z andrew $");
45
46 #include <sys/param.h>
47 #include <sys/systm.h>
48 #include <sys/kernel.h>
49 #include <sys/lock.h>
50 #include <sys/malloc.h>
51 #include <sys/module.h>
52 #include <sys/mutex.h>
53 #include <sys/queue.h>
54 #include <sys/bus.h>
55 #include <sys/rman.h>
56 #include <sys/endian.h>
57 #include <sys/devmap.h>
58
59 #include <machine/fdt.h>
60 #include <machine/intr.h>
61
62 #include <vm/vm.h>
63 #include <vm/pmap.h>
64
65 #include <dev/fdt/fdt_common.h>
66 #include <dev/ofw/ofw_bus.h>
67 #include <dev/ofw/ofw_bus_subr.h>
68 #include <dev/ofw/ofw_pci.h>
69 #include <dev/pci/pcivar.h>
70 #include <dev/pci/pcireg.h>
71 #include <dev/pci/pcib_private.h>
72
73 #include "ofw_bus_if.h"
74 #include "pcib_if.h"
75
76 #include <machine/resource.h>
77 #include <machine/bus.h>
78
79 #include <arm/mv/mvreg.h>
80 #include <arm/mv/mvvar.h>
81 #include <arm/mv/mvwin.h>
82
83 #ifdef DEBUG
84 #define debugf(fmt, args...) do { printf(fmt,##args); } while (0)
85 #else
86 #define debugf(fmt, args...)
87 #endif
88
89 /*
90 * Code and data related to fdt-based PCI configuration.
91 *
92 * This stuff used to be in dev/fdt/fdt_pci.c and fdt_common.h, but it was
93 * always Marvell-specific so that was deleted and the code now lives here.
94 */
95
96 struct mv_pci_range {
97 u_long base_pci;
98 u_long base_parent;
99 u_long len;
100 };
101
102 #define FDT_RANGES_CELLS ((3 + 3 + 2) * 2)
103 #define PCI_SPACE_LEN 0x00100000
104
105 static void
106 mv_pci_range_dump(struct mv_pci_range *range)
107 {
108 #ifdef DEBUG
109 printf("\n");
110 printf(" base_pci = 0x%08lx\n", range->base_pci);
111 printf(" base_par = 0x%08lx\n", range->base_parent);
112 printf(" len = 0x%08lx\n", range->len);
113 #endif
114 }
115
116 static int
117 mv_pci_ranges_decode(phandle_t node, struct mv_pci_range *io_space,
118 struct mv_pci_range *mem_space)
119 {
120 pcell_t ranges[FDT_RANGES_CELLS];
121 struct mv_pci_range *pci_space;
122 pcell_t addr_cells, size_cells, par_addr_cells;
123 pcell_t *rangesptr;
124 pcell_t cell0, cell1, cell2;
125 int tuple_size, tuples, i, rv, offset_cells, len;
126 int portid, is_io_space;
127
128 /*
129 * Retrieve 'ranges' property.
130 */
131 if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0)
132 return (EINVAL);
133 if (addr_cells != 3 || size_cells != 2)
134 return (ERANGE);
135
136 par_addr_cells = fdt_parent_addr_cells(node);
137 if (par_addr_cells > 3)
138 return (ERANGE);
139
140 len = OF_getproplen(node, "ranges");
141 if (len > sizeof(ranges))
142 return (ENOMEM);
143
144 if (OF_getprop(node, "ranges", ranges, sizeof(ranges)) <= 0)
145 return (EINVAL);
146
147 tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells +
148 size_cells);
149 tuples = len / tuple_size;
150
151 /*
152 * Initialize the ranges so that we don't have to worry about
153 * having them all defined in the FDT. In particular, it is
154 * perfectly fine not to want I/O space on PCI buses.
155 */
156 bzero(io_space, sizeof(*io_space));
157 bzero(mem_space, sizeof(*mem_space));
158
159 rangesptr = &ranges[0];
160 offset_cells = 0;
161 for (i = 0; i < tuples; i++) {
162 cell0 = fdt_data_get((void *)rangesptr, 1);
163 rangesptr++;
164 cell1 = fdt_data_get((void *)rangesptr, 1);
165 rangesptr++;
166 cell2 = fdt_data_get((void *)rangesptr, 1);
167 rangesptr++;
168 portid = fdt_data_get((void *)(rangesptr+1), 1);
169
170 if (cell0 & 0x02000000) {
171 pci_space = mem_space;
172 is_io_space = 0;
173 } else if (cell0 & 0x01000000) {
174 pci_space = io_space;
175 is_io_space = 1;
176 } else {
177 rv = ERANGE;
178 goto out;
179 }
180
181 if (par_addr_cells == 3) {
182 /*
183 * This is a PCI subnode 'ranges'. Skip cell0 and
184 * cell1 of this entry and only use cell2.
185 */
186 offset_cells = 2;
187 rangesptr += offset_cells;
188 }
189
190 if ((par_addr_cells - offset_cells) > 2) {
191 rv = ERANGE;
192 goto out;
193 }
194 pci_space->base_parent = fdt_data_get((void *)rangesptr,
195 par_addr_cells - offset_cells);
196 rangesptr += par_addr_cells - offset_cells;
197
198 if (size_cells > 2) {
199 rv = ERANGE;
200 goto out;
201 }
202 pci_space->len = fdt_data_get((void *)rangesptr, size_cells);
203 rangesptr += size_cells;
204
205 pci_space->base_pci = cell2;
206
207 if (pci_space->len == 0) {
208 pci_space->len = PCI_SPACE_LEN;
209 pci_space->base_parent = fdt_immr_va +
210 PCI_SPACE_LEN * ( 2 * portid + is_io_space);
211 }
212 }
213 rv = 0;
214 out:
215 return (rv);
216 }
217
218 static int
219 mv_pci_ranges(phandle_t node, struct mv_pci_range *io_space,
220 struct mv_pci_range *mem_space)
221 {
222 int err;
223
224 debugf("Processing PCI node: %x\n", node);
225 if ((err = mv_pci_ranges_decode(node, io_space, mem_space)) != 0) {
226 debugf("could not decode parent PCI node 'ranges'\n");
227 return (err);
228 }
229
230 debugf("Post fixup dump:\n");
231 mv_pci_range_dump(io_space);
232 mv_pci_range_dump(mem_space);
233 return (0);
234 }
235
236 int
237 mv_pci_devmap(phandle_t node, struct devmap_entry *devmap, vm_offset_t io_va,
238 vm_offset_t mem_va)
239 {
240 struct mv_pci_range io_space, mem_space;
241 int error;
242
243 if ((error = mv_pci_ranges_decode(node, &io_space, &mem_space)) != 0)
244 return (error);
245
246 devmap->pd_va = (io_va ? io_va : io_space.base_parent);
247 devmap->pd_pa = io_space.base_parent;
248 devmap->pd_size = io_space.len;
249 devmap++;
250
251 devmap->pd_va = (mem_va ? mem_va : mem_space.base_parent);
252 devmap->pd_pa = mem_space.base_parent;
253 devmap->pd_size = mem_space.len;
254 return (0);
255 }
256
257 /*
258 * Code and data related to the Marvell pcib driver.
259 */
260
261 #define PCI_CFG_ENA (1U << 31)
262 #define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16)
263 #define PCI_CFG_DEV(dev) (((dev) & 0x1f) << 11)
264 #define PCI_CFG_FUN(fun) (((fun) & 0x7) << 8)
265 #define PCI_CFG_PCIE_REG(reg) ((reg) & 0xfc)
266
267 #define PCI_REG_CFG_ADDR 0x0C78
268 #define PCI_REG_CFG_DATA 0x0C7C
269
270 #define PCIE_REG_CFG_ADDR 0x18F8
271 #define PCIE_REG_CFG_DATA 0x18FC
272 #define PCIE_REG_CONTROL 0x1A00
273 #define PCIE_CTRL_LINK1X 0x00000001
274 #define PCIE_REG_STATUS 0x1A04
275 #define PCIE_REG_IRQ_MASK 0x1910
276
277 #define PCIE_CONTROL_ROOT_CMPLX (1 << 1)
278 #define PCIE_CONTROL_HOT_RESET (1 << 24)
279
280 #define PCIE_LINK_TIMEOUT 1000000
281
282 #define PCIE_STATUS_LINK_DOWN 1
283 #define PCIE_STATUS_DEV_OFFS 16
284
285 /* Minimum PCI Memory and I/O allocations taken from PCI spec (in bytes) */
286 #define PCI_MIN_IO_ALLOC 4
287 #define PCI_MIN_MEM_ALLOC 16
288
289 #define BITS_PER_UINT32 (NBBY * sizeof(uint32_t))
290
291 struct mv_pcib_softc {
292 device_t sc_dev;
293
294 struct rman sc_mem_rman;
295 bus_addr_t sc_mem_base;
296 bus_addr_t sc_mem_size;
297 uint32_t sc_mem_map[MV_PCI_MEM_SLICE_SIZE /
298 (PCI_MIN_MEM_ALLOC * BITS_PER_UINT32)];
299 int sc_win_target;
300 int sc_mem_win_attr;
301
302 struct rman sc_io_rman;
303 bus_addr_t sc_io_base;
304 bus_addr_t sc_io_size;
305 uint32_t sc_io_map[MV_PCI_IO_SLICE_SIZE /
306 (PCI_MIN_IO_ALLOC * BITS_PER_UINT32)];
307 int sc_io_win_attr;
308
309 struct resource *sc_res;
310 bus_space_handle_t sc_bsh;
311 bus_space_tag_t sc_bst;
312 int sc_rid;
313
314 struct mtx sc_msi_mtx;
315 uint32_t sc_msi_bitmap;
316
317 int sc_busnr; /* Host bridge bus number */
318 int sc_devnr; /* Host bridge device number */
319 int sc_type;
320 int sc_mode; /* Endpoint / Root Complex */
321
322 int sc_msi_supported;
323 int sc_skip_enable_procedure;
324 int sc_enable_find_root_slot;
325 struct ofw_bus_iinfo sc_pci_iinfo;
326
327 int ap_segment; /* PCI domain */
328 };
329
330 /* Local forward prototypes */
331 static int mv_pcib_decode_win(phandle_t, struct mv_pcib_softc *);
332 static void mv_pcib_hw_cfginit(void);
333 static uint32_t mv_pcib_hw_cfgread(struct mv_pcib_softc *, u_int, u_int,
334 u_int, u_int, int);
335 static void mv_pcib_hw_cfgwrite(struct mv_pcib_softc *, u_int, u_int,
336 u_int, u_int, uint32_t, int);
337 static int mv_pcib_init(struct mv_pcib_softc *, int, int);
338 static int mv_pcib_init_all_bars(struct mv_pcib_softc *, int, int, int, int);
339 static void mv_pcib_init_bridge(struct mv_pcib_softc *, int, int, int);
340 static inline void pcib_write_irq_mask(struct mv_pcib_softc *, uint32_t);
341 static void mv_pcib_enable(struct mv_pcib_softc *, uint32_t);
342 static int mv_pcib_mem_init(struct mv_pcib_softc *);
343
344 /* Forward prototypes */
345 static int mv_pcib_probe(device_t);
346 static int mv_pcib_attach(device_t);
347
348 static struct resource *mv_pcib_alloc_resource(device_t, device_t, int, int *,
349 rman_res_t, rman_res_t, rman_res_t, u_int);
350 static int mv_pcib_release_resource(device_t, device_t, int, int,
351 struct resource *);
352 static int mv_pcib_read_ivar(device_t, device_t, int, uintptr_t *);
353 static int mv_pcib_write_ivar(device_t, device_t, int, uintptr_t);
354
355 static int mv_pcib_maxslots(device_t);
356 static uint32_t mv_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int);
357 static void mv_pcib_write_config(device_t, u_int, u_int, u_int, u_int,
358 uint32_t, int);
359 static int mv_pcib_route_interrupt(device_t, device_t, int);
360
361 static int mv_pcib_alloc_msi(device_t, device_t, int, int, int *);
362 static int mv_pcib_map_msi(device_t, device_t, int, uint64_t *, uint32_t *);
363 static int mv_pcib_release_msi(device_t, device_t, int, int *);
364
365 /*
366 * Bus interface definitions.
367 */
368 static device_method_t mv_pcib_methods[] = {
369 /* Device interface */
370 DEVMETHOD(device_probe, mv_pcib_probe),
371 DEVMETHOD(device_attach, mv_pcib_attach),
372
373 /* Bus interface */
374 DEVMETHOD(bus_read_ivar, mv_pcib_read_ivar),
375 DEVMETHOD(bus_write_ivar, mv_pcib_write_ivar),
376 DEVMETHOD(bus_alloc_resource, mv_pcib_alloc_resource),
377 DEVMETHOD(bus_release_resource, mv_pcib_release_resource),
378 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
379 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
380 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
381 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
382
383 /* pcib interface */
384 DEVMETHOD(pcib_maxslots, mv_pcib_maxslots),
385 DEVMETHOD(pcib_read_config, mv_pcib_read_config),
386 DEVMETHOD(pcib_write_config, mv_pcib_write_config),
387 DEVMETHOD(pcib_route_interrupt, mv_pcib_route_interrupt),
388 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow),
389
390 DEVMETHOD(pcib_alloc_msi, mv_pcib_alloc_msi),
391 DEVMETHOD(pcib_release_msi, mv_pcib_release_msi),
392 DEVMETHOD(pcib_map_msi, mv_pcib_map_msi),
393
394 /* OFW bus interface */
395 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
396 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
397 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
398 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
399 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
400
401 DEVMETHOD_END
402 };
403
404 static driver_t mv_pcib_driver = {
405 "pcib",
406 mv_pcib_methods,
407 sizeof(struct mv_pcib_softc),
408 };
409
410 devclass_t pcib_devclass;
411
412 DRIVER_MODULE(pcib, ofwbus, mv_pcib_driver, pcib_devclass, 0, 0);
413 DRIVER_MODULE(pcib, pcib_ctrl, mv_pcib_driver, pcib_devclass, 0, 0);
414
415 static struct mtx pcicfg_mtx;
416
417 static int
418 mv_pcib_probe(device_t self)
419 {
420 phandle_t node;
421
422 node = ofw_bus_get_node(self);
423 if (!mv_fdt_is_type(node, "pci"))
424 return (ENXIO);
425
426 if (!(ofw_bus_is_compatible(self, "mrvl,pcie") ||
427 ofw_bus_is_compatible(self, "mrvl,pci") ||
428 ofw_bus_node_is_compatible(
429 OF_parent(node), "marvell,armada-370-pcie")))
430 return (ENXIO);
431
432 device_set_desc(self, "Marvell Integrated PCI/PCI-E Controller");
433 return (BUS_PROBE_DEFAULT);
434 }
435
436 static int
437 mv_pcib_attach(device_t self)
438 {
439 struct mv_pcib_softc *sc;
440 phandle_t node, parnode;
441 uint32_t val, reg0;
442 int err, bus, devfn, port_id;
443
444 sc = device_get_softc(self);
445 sc->sc_dev = self;
446
447 node = ofw_bus_get_node(self);
448 parnode = OF_parent(node);
449
450 if (OF_getencprop(node, "marvell,pcie-port", &(port_id),
451 sizeof(port_id)) <= 0) {
452 /* If port ID does not exist in the FDT set value to 0 */
453 if (!OF_hasprop(node, "marvell,pcie-port"))
454 port_id = 0;
455 else
456 return(ENXIO);
457 }
458
459 sc->ap_segment = port_id;
460
461 if (ofw_bus_node_is_compatible(node, "mrvl,pcie")) {
462 sc->sc_type = MV_TYPE_PCIE;
463 sc->sc_win_target = MV_WIN_PCIE_TARGET(port_id);
464 sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR(port_id);
465 sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR(port_id);
466 #if __ARM_ARCH >= 6
467 sc->sc_skip_enable_procedure = 1;
468 #endif
469 } else if (ofw_bus_node_is_compatible(parnode, "marvell,armada-370-pcie")) {
470 sc->sc_type = MV_TYPE_PCIE;
471 sc->sc_win_target = MV_WIN_PCIE_TARGET_ARMADA38X(port_id);
472 sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR_ARMADA38X(port_id);
473 sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR_ARMADA38X(port_id);
474 sc->sc_enable_find_root_slot = 1;
475 } else if (ofw_bus_node_is_compatible(node, "mrvl,pci")) {
476 sc->sc_type = MV_TYPE_PCI;
477 sc->sc_win_target = MV_WIN_PCI_TARGET;
478 sc->sc_mem_win_attr = MV_WIN_PCI_MEM_ATTR;
479 sc->sc_io_win_attr = MV_WIN_PCI_IO_ATTR;
480 } else
481 return (ENXIO);
482
483 /*
484 * Retrieve our mem-mapped registers range.
485 */
486 sc->sc_rid = 0;
487 sc->sc_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &sc->sc_rid,
488 RF_ACTIVE);
489 if (sc->sc_res == NULL) {
490 device_printf(self, "could not map memory\n");
491 return (ENXIO);
492 }
493 sc->sc_bst = rman_get_bustag(sc->sc_res);
494 sc->sc_bsh = rman_get_bushandle(sc->sc_res);
495
496 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_CONTROL);
497 sc->sc_mode = (val & PCIE_CONTROL_ROOT_CMPLX ? MV_MODE_ROOT :
498 MV_MODE_ENDPOINT);
499
500 /*
501 * Get PCI interrupt info.
502 */
503 if (sc->sc_mode == MV_MODE_ROOT)
504 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(pcell_t));
505
506 /*
507 * Configure decode windows for PCI(E) access.
508 */
509 if (mv_pcib_decode_win(node, sc) != 0)
510 return (ENXIO);
511
512 mv_pcib_hw_cfginit();
513
514 /*
515 * Enable PCIE device.
516 */
517 mv_pcib_enable(sc, port_id);
518
519 /*
520 * Memory management.
521 */
522 err = mv_pcib_mem_init(sc);
523 if (err)
524 return (err);
525
526 /*
527 * Preliminary bus enumeration to find first linked devices and set
528 * appropriate bus number from which should start the actual enumeration
529 */
530 for (bus = 0; bus < PCI_BUSMAX; bus++) {
531 for (devfn = 0; devfn < mv_pcib_maxslots(self); devfn++) {
532 reg0 = mv_pcib_read_config(self, bus, devfn, devfn & 0x7, 0x0, 4);
533 if (reg0 == (~0U))
534 continue; /* no device */
535 else {
536 sc->sc_busnr = bus; /* update bus number */
537 break;
538 }
539 }
540 }
541
542 if (sc->sc_mode == MV_MODE_ROOT) {
543 err = mv_pcib_init(sc, sc->sc_busnr,
544 mv_pcib_maxslots(sc->sc_dev));
545 if (err)
546 goto error;
547
548 device_add_child(self, "pci", -1);
549 } else {
550 sc->sc_devnr = 1;
551 bus_space_write_4(sc->sc_bst, sc->sc_bsh,
552 PCIE_REG_STATUS, 1 << PCIE_STATUS_DEV_OFFS);
553 device_add_child(self, "pci_ep", -1);
554 }
555
556 mtx_init(&sc->sc_msi_mtx, "msi_mtx", NULL, MTX_DEF);
557 return (bus_generic_attach(self));
558
559 error:
560 /* XXX SYS_RES_ should be released here */
561 rman_fini(&sc->sc_mem_rman);
562 rman_fini(&sc->sc_io_rman);
563
564 return (err);
565 }
566
567 static void
568 mv_pcib_enable(struct mv_pcib_softc *sc, uint32_t unit)
569 {
570 uint32_t val;
571 int timeout;
572
573 if (sc->sc_skip_enable_procedure)
574 goto pcib_enable_root_mode;
575
576 /*
577 * Check if PCIE device is enabled.
578 */
579 if ((sc->sc_skip_enable_procedure == 0) &&
580 (read_cpu_ctrl(CPU_CONTROL) & CPU_CONTROL_PCIE_DISABLE(unit))) {
581 write_cpu_ctrl(CPU_CONTROL, read_cpu_ctrl(CPU_CONTROL) &
582 ~(CPU_CONTROL_PCIE_DISABLE(unit)));
583
584 timeout = PCIE_LINK_TIMEOUT;
585 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
586 PCIE_REG_STATUS);
587 while (((val & PCIE_STATUS_LINK_DOWN) == 1) && (timeout > 0)) {
588 DELAY(1000);
589 timeout -= 1000;
590 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
591 PCIE_REG_STATUS);
592 }
593 }
594
595 pcib_enable_root_mode:
596 if (sc->sc_mode == MV_MODE_ROOT) {
597 /*
598 * Enable PCI bridge.
599 */
600 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND);
601 val |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN |
602 PCIM_CMD_MEMEN | PCIM_CMD_PORTEN;
603 bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND, val);
604 }
605 }
606
607 static int
608 mv_pcib_mem_init(struct mv_pcib_softc *sc)
609 {
610 int err;
611
612 /*
613 * Memory management.
614 */
615 sc->sc_mem_rman.rm_type = RMAN_ARRAY;
616 err = rman_init(&sc->sc_mem_rman);
617 if (err)
618 return (err);
619
620 sc->sc_io_rman.rm_type = RMAN_ARRAY;
621 err = rman_init(&sc->sc_io_rman);
622 if (err) {
623 rman_fini(&sc->sc_mem_rman);
624 return (err);
625 }
626
627 err = rman_manage_region(&sc->sc_mem_rman, sc->sc_mem_base,
628 sc->sc_mem_base + sc->sc_mem_size - 1);
629 if (err)
630 goto error;
631
632 err = rman_manage_region(&sc->sc_io_rman, sc->sc_io_base,
633 sc->sc_io_base + sc->sc_io_size - 1);
634 if (err)
635 goto error;
636
637 return (0);
638
639 error:
640 rman_fini(&sc->sc_mem_rman);
641 rman_fini(&sc->sc_io_rman);
642
643 return (err);
644 }
645
646 static inline uint32_t
647 pcib_bit_get(uint32_t *map, uint32_t bit)
648 {
649 uint32_t n = bit / BITS_PER_UINT32;
650
651 bit = bit % BITS_PER_UINT32;
652 return (map[n] & (1 << bit));
653 }
654
655 static inline void
656 pcib_bit_set(uint32_t *map, uint32_t bit)
657 {
658 uint32_t n = bit / BITS_PER_UINT32;
659
660 bit = bit % BITS_PER_UINT32;
661 map[n] |= (1 << bit);
662 }
663
664 static inline uint32_t
665 pcib_map_check(uint32_t *map, uint32_t start, uint32_t bits)
666 {
667 uint32_t i;
668
669 for (i = start; i < start + bits; i++)
670 if (pcib_bit_get(map, i))
671 return (0);
672
673 return (1);
674 }
675
676 static inline void
677 pcib_map_set(uint32_t *map, uint32_t start, uint32_t bits)
678 {
679 uint32_t i;
680
681 for (i = start; i < start + bits; i++)
682 pcib_bit_set(map, i);
683 }
684
685 /*
686 * The idea of this allocator is taken from ARM No-Cache memory
687 * management code (sys/arm/arm/vm_machdep.c).
688 */
689 static bus_addr_t
690 pcib_alloc(struct mv_pcib_softc *sc, uint32_t smask)
691 {
692 uint32_t bits, bits_limit, i, *map, min_alloc, size;
693 bus_addr_t addr = 0;
694 bus_addr_t base;
695
696 if (smask & 1) {
697 base = sc->sc_io_base;
698 min_alloc = PCI_MIN_IO_ALLOC;
699 bits_limit = sc->sc_io_size / min_alloc;
700 map = sc->sc_io_map;
701 smask &= ~0x3;
702 } else {
703 base = sc->sc_mem_base;
704 min_alloc = PCI_MIN_MEM_ALLOC;
705 bits_limit = sc->sc_mem_size / min_alloc;
706 map = sc->sc_mem_map;
707 smask &= ~0xF;
708 }
709
710 size = ~smask + 1;
711 bits = size / min_alloc;
712
713 for (i = 0; i + bits <= bits_limit; i += bits)
714 if (pcib_map_check(map, i, bits)) {
715 pcib_map_set(map, i, bits);
716 addr = base + (i * min_alloc);
717 return (addr);
718 }
719
720 return (addr);
721 }
722
723 static int
724 mv_pcib_init_bar(struct mv_pcib_softc *sc, int bus, int slot, int func,
725 int barno)
726 {
727 uint32_t addr, bar;
728 int reg, width;
729
730 reg = PCIR_BAR(barno);
731
732 /*
733 * Need to init the BAR register with 0xffffffff before correct
734 * value can be read.
735 */
736 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4);
737 bar = mv_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4);
738 if (bar == 0)
739 return (1);
740
741 /* Calculate BAR size: 64 or 32 bit (in 32-bit units) */
742 width = ((bar & 7) == 4) ? 2 : 1;
743
744 addr = pcib_alloc(sc, bar);
745 if (!addr)
746 return (-1);
747
748 if (bootverbose)
749 printf("PCI %u:%u:%u: reg %x: smask=%08x: addr=%08x\n",
750 bus, slot, func, reg, bar, addr);
751
752 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4);
753 if (width == 2)
754 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg + 4,
755 0, 4);
756
757 return (width);
758 }
759
760 static void
761 mv_pcib_init_bridge(struct mv_pcib_softc *sc, int bus, int slot, int func)
762 {
763 bus_addr_t io_base, mem_base;
764 uint32_t io_limit, mem_limit;
765 int secbus;
766
767 io_base = sc->sc_io_base;
768 io_limit = io_base + sc->sc_io_size - 1;
769 mem_base = sc->sc_mem_base;
770 mem_limit = mem_base + sc->sc_mem_size - 1;
771
772 /* Configure I/O decode registers */
773 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEL_1,
774 io_base >> 8, 1);
775 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEH_1,
776 io_base >> 16, 2);
777 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITL_1,
778 io_limit >> 8, 1);
779 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITH_1,
780 io_limit >> 16, 2);
781
782 /* Configure memory decode registers */
783 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMBASE_1,
784 mem_base >> 16, 2);
785 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMLIMIT_1,
786 mem_limit >> 16, 2);
787
788 /* Disable memory prefetch decode */
789 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEL_1,
790 0x10, 2);
791 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEH_1,
792 0x0, 4);
793 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITL_1,
794 0xF, 2);
795 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITH_1,
796 0x0, 4);
797
798 secbus = mv_pcib_read_config(sc->sc_dev, bus, slot, func,
799 PCIR_SECBUS_1, 1);
800
801 /* Configure buses behind the bridge */
802 mv_pcib_init(sc, secbus, PCI_SLOTMAX);
803 }
804
805 static int
806 mv_pcib_init(struct mv_pcib_softc *sc, int bus, int maxslot)
807 {
808 int slot, func, maxfunc, error;
809 uint8_t hdrtype, command, class, subclass;
810
811 for (slot = 0; slot <= maxslot; slot++) {
812 maxfunc = 0;
813 for (func = 0; func <= maxfunc; func++) {
814 hdrtype = mv_pcib_read_config(sc->sc_dev, bus, slot,
815 func, PCIR_HDRTYPE, 1);
816
817 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
818 continue;
819
820 if (func == 0 && (hdrtype & PCIM_MFDEV))
821 maxfunc = PCI_FUNCMAX;
822
823 command = mv_pcib_read_config(sc->sc_dev, bus, slot,
824 func, PCIR_COMMAND, 1);
825 command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN);
826 mv_pcib_write_config(sc->sc_dev, bus, slot, func,
827 PCIR_COMMAND, command, 1);
828
829 error = mv_pcib_init_all_bars(sc, bus, slot, func,
830 hdrtype);
831
832 if (error)
833 return (error);
834
835 command |= PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN |
836 PCIM_CMD_PORTEN;
837 mv_pcib_write_config(sc->sc_dev, bus, slot, func,
838 PCIR_COMMAND, command, 1);
839
840 /* Handle PCI-PCI bridges */
841 class = mv_pcib_read_config(sc->sc_dev, bus, slot,
842 func, PCIR_CLASS, 1);
843 subclass = mv_pcib_read_config(sc->sc_dev, bus, slot,
844 func, PCIR_SUBCLASS, 1);
845
846 if (class != PCIC_BRIDGE ||
847 subclass != PCIS_BRIDGE_PCI)
848 continue;
849
850 mv_pcib_init_bridge(sc, bus, slot, func);
851 }
852 }
853
854 /* Enable all ABCD interrupts */
855 pcib_write_irq_mask(sc, (0xF << 24));
856
857 return (0);
858 }
859
860 static int
861 mv_pcib_init_all_bars(struct mv_pcib_softc *sc, int bus, int slot,
862 int func, int hdrtype)
863 {
864 int maxbar, bar, i;
865
866 maxbar = (hdrtype & PCIM_HDRTYPE) ? 0 : 6;
867 bar = 0;
868
869 /* Program the base address registers */
870 while (bar < maxbar) {
871 i = mv_pcib_init_bar(sc, bus, slot, func, bar);
872 bar += i;
873 if (i < 0) {
874 device_printf(sc->sc_dev,
875 "PCI IO/Memory space exhausted\n");
876 return (ENOMEM);
877 }
878 }
879
880 return (0);
881 }
882
883 static struct resource *
884 mv_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
885 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
886 {
887 struct mv_pcib_softc *sc = device_get_softc(dev);
888 struct rman *rm = NULL;
889 struct resource *res;
890
891 switch (type) {
892 case SYS_RES_IOPORT:
893 rm = &sc->sc_io_rman;
894 break;
895 case SYS_RES_MEMORY:
896 rm = &sc->sc_mem_rman;
897 break;
898 #ifdef PCI_RES_BUS
899 case PCI_RES_BUS:
900 return (pci_domain_alloc_bus(sc->ap_segment, child, rid, start,
901 end, count, flags));
902 #endif
903 default:
904 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
905 type, rid, start, end, count, flags));
906 }
907
908 if (RMAN_IS_DEFAULT_RANGE(start, end)) {
909 start = sc->sc_mem_base;
910 end = sc->sc_mem_base + sc->sc_mem_size - 1;
911 count = sc->sc_mem_size;
912 }
913
914 if ((start < sc->sc_mem_base) || (start + count - 1 != end) ||
915 (end > sc->sc_mem_base + sc->sc_mem_size - 1))
916 return (NULL);
917
918 res = rman_reserve_resource(rm, start, end, count, flags, child);
919 if (res == NULL)
920 return (NULL);
921
922 rman_set_rid(res, *rid);
923 rman_set_bustag(res, fdtbus_bs_tag);
924 rman_set_bushandle(res, start);
925
926 if (flags & RF_ACTIVE)
927 if (bus_activate_resource(child, type, *rid, res)) {
928 rman_release_resource(res);
929 return (NULL);
930 }
931
932 return (res);
933 }
934
935 static int
936 mv_pcib_release_resource(device_t dev, device_t child, int type, int rid,
937 struct resource *res)
938 {
939 #ifdef PCI_RES_BUS
940 struct mv_pcib_softc *sc = device_get_softc(dev);
941
942 if (type == PCI_RES_BUS)
943 return (pci_domain_release_bus(sc->ap_segment, child, rid, res));
944 #endif
945 if (type != SYS_RES_IOPORT && type != SYS_RES_MEMORY)
946 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
947 type, rid, res));
948
949 return (rman_release_resource(res));
950 }
951
952 static int
953 mv_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
954 {
955 struct mv_pcib_softc *sc = device_get_softc(dev);
956
957 switch (which) {
958 case PCIB_IVAR_BUS:
959 *result = sc->sc_busnr;
960 return (0);
961 case PCIB_IVAR_DOMAIN:
962 *result = device_get_unit(dev);
963 return (0);
964 }
965
966 return (ENOENT);
967 }
968
969 static int
970 mv_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
971 {
972 struct mv_pcib_softc *sc = device_get_softc(dev);
973
974 switch (which) {
975 case PCIB_IVAR_BUS:
976 sc->sc_busnr = value;
977 return (0);
978 }
979
980 return (ENOENT);
981 }
982
983 static inline void
984 pcib_write_irq_mask(struct mv_pcib_softc *sc, uint32_t mask)
985 {
986
987 if (sc->sc_type != MV_TYPE_PCIE)
988 return;
989
990 bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_IRQ_MASK, mask);
991 }
992
993 static void
994 mv_pcib_hw_cfginit(void)
995 {
996 static int opened = 0;
997
998 if (opened)
999 return;
1000
1001 mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
1002 opened = 1;
1003 }
1004
1005 static uint32_t
1006 mv_pcib_hw_cfgread(struct mv_pcib_softc *sc, u_int bus, u_int slot,
1007 u_int func, u_int reg, int bytes)
1008 {
1009 uint32_t addr, data, ca, cd;
1010
1011 ca = (sc->sc_type != MV_TYPE_PCI) ?
1012 PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR;
1013 cd = (sc->sc_type != MV_TYPE_PCI) ?
1014 PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA;
1015 addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) |
1016 PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg);
1017
1018 mtx_lock_spin(&pcicfg_mtx);
1019 bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr);
1020
1021 data = ~0;
1022 switch (bytes) {
1023 case 1:
1024 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh,
1025 cd + (reg & 3));
1026 break;
1027 case 2:
1028 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh,
1029 cd + (reg & 2)));
1030 break;
1031 case 4:
1032 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh,
1033 cd));
1034 break;
1035 }
1036 mtx_unlock_spin(&pcicfg_mtx);
1037 return (data);
1038 }
1039
1040 static void
1041 mv_pcib_hw_cfgwrite(struct mv_pcib_softc *sc, u_int bus, u_int slot,
1042 u_int func, u_int reg, uint32_t data, int bytes)
1043 {
1044 uint32_t addr, ca, cd;
1045
1046 ca = (sc->sc_type != MV_TYPE_PCI) ?
1047 PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR;
1048 cd = (sc->sc_type != MV_TYPE_PCI) ?
1049 PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA;
1050 addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) |
1051 PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg);
1052
1053 mtx_lock_spin(&pcicfg_mtx);
1054 bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr);
1055
1056 switch (bytes) {
1057 case 1:
1058 bus_space_write_1(sc->sc_bst, sc->sc_bsh,
1059 cd + (reg & 3), data);
1060 break;
1061 case 2:
1062 bus_space_write_2(sc->sc_bst, sc->sc_bsh,
1063 cd + (reg & 2), htole16(data));
1064 break;
1065 case 4:
1066 bus_space_write_4(sc->sc_bst, sc->sc_bsh,
1067 cd, htole32(data));
1068 break;
1069 }
1070 mtx_unlock_spin(&pcicfg_mtx);
1071 }
1072
1073 static int
1074 mv_pcib_maxslots(device_t dev)
1075 {
1076 struct mv_pcib_softc *sc = device_get_softc(dev);
1077
1078 return ((sc->sc_type != MV_TYPE_PCI) ? 1 : PCI_SLOTMAX);
1079 }
1080
1081 static int
1082 mv_pcib_root_slot(device_t dev, u_int bus, u_int slot, u_int func)
1083 {
1084 struct mv_pcib_softc *sc = device_get_softc(dev);
1085 uint32_t vendor, device;
1086
1087 /* On platforms other than Armada38x, root link is always at slot 0 */
1088 if (!sc->sc_enable_find_root_slot)
1089 return (slot == 0);
1090
1091 vendor = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_VENDOR,
1092 PCIR_VENDOR_LENGTH);
1093 device = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_DEVICE,
1094 PCIR_DEVICE_LENGTH) & MV_DEV_FAMILY_MASK;
1095
1096 return (vendor == PCI_VENDORID_MRVL && device == MV_DEV_ARMADA38X);
1097 }
1098
1099 static uint32_t
1100 mv_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
1101 u_int reg, int bytes)
1102 {
1103 struct mv_pcib_softc *sc = device_get_softc(dev);
1104
1105 /* Return ~0 if link is inactive or trying to read from Root */
1106 if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) &
1107 PCIE_STATUS_LINK_DOWN) || mv_pcib_root_slot(dev, bus, slot, func))
1108 return (~0U);
1109
1110 return (mv_pcib_hw_cfgread(sc, bus, slot, func, reg, bytes));
1111 }
1112
1113 static void
1114 mv_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
1115 u_int reg, uint32_t val, int bytes)
1116 {
1117 struct mv_pcib_softc *sc = device_get_softc(dev);
1118
1119 /* Return if link is inactive or trying to write to Root */
1120 if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) &
1121 PCIE_STATUS_LINK_DOWN) || mv_pcib_root_slot(dev, bus, slot, func))
1122 return;
1123
1124 mv_pcib_hw_cfgwrite(sc, bus, slot, func, reg, val, bytes);
1125 }
1126
1127 static int
1128 mv_pcib_route_interrupt(device_t bus, device_t dev, int pin)
1129 {
1130 struct mv_pcib_softc *sc;
1131 struct ofw_pci_register reg;
1132 uint32_t pintr, mintr[4];
1133 int icells;
1134 phandle_t iparent;
1135
1136 sc = device_get_softc(bus);
1137 pintr = pin;
1138
1139 /* Fabricate imap information in case this isn't an OFW device */
1140 bzero(®, sizeof(reg));
1141 reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) |
1142 (pci_get_slot(dev) << OFW_PCI_PHYS_HI_DEVICESHIFT) |
1143 (pci_get_function(dev) << OFW_PCI_PHYS_HI_FUNCTIONSHIFT);
1144
1145 icells = ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo,
1146 ®, sizeof(reg), &pintr, sizeof(pintr), mintr, sizeof(mintr),
1147 &iparent);
1148 if (icells > 0)
1149 return (ofw_bus_map_intr(dev, iparent, icells, mintr));
1150
1151 /* Maybe it's a real interrupt, not an intpin */
1152 if (pin > 4)
1153 return (pin);
1154
1155 device_printf(bus, "could not route pin %d for device %d.%d\n",
1156 pin, pci_get_slot(dev), pci_get_function(dev));
1157 return (PCI_INVALID_IRQ);
1158 }
1159
1160 static int
1161 mv_pcib_decode_win(phandle_t node, struct mv_pcib_softc *sc)
1162 {
1163 struct mv_pci_range io_space, mem_space;
1164 device_t dev;
1165 int error;
1166
1167 dev = sc->sc_dev;
1168
1169 if ((error = mv_pci_ranges(node, &io_space, &mem_space)) != 0) {
1170 device_printf(dev, "could not retrieve 'ranges' data\n");
1171 return (error);
1172 }
1173
1174 /* Configure CPU decoding windows */
1175 error = decode_win_cpu_set(sc->sc_win_target,
1176 sc->sc_io_win_attr, io_space.base_parent, io_space.len, ~0);
1177 if (error < 0) {
1178 device_printf(dev, "could not set up CPU decode "
1179 "window for PCI IO\n");
1180 return (ENXIO);
1181 }
1182 error = decode_win_cpu_set(sc->sc_win_target,
1183 sc->sc_mem_win_attr, mem_space.base_parent, mem_space.len,
1184 mem_space.base_parent);
1185 if (error < 0) {
1186 device_printf(dev, "could not set up CPU decode "
1187 "windows for PCI MEM\n");
1188 return (ENXIO);
1189 }
1190
1191 sc->sc_io_base = io_space.base_parent;
1192 sc->sc_io_size = io_space.len;
1193
1194 sc->sc_mem_base = mem_space.base_parent;
1195 sc->sc_mem_size = mem_space.len;
1196
1197 return (0);
1198 }
1199
1200 static int
1201 mv_pcib_map_msi(device_t dev, device_t child, int irq, uint64_t *addr,
1202 uint32_t *data)
1203 {
1204 struct mv_pcib_softc *sc;
1205
1206 sc = device_get_softc(dev);
1207 if (!sc->sc_msi_supported)
1208 return (ENOTSUP);
1209
1210 irq = irq - MSI_IRQ;
1211
1212 /* validate parameters */
1213 if (isclr(&sc->sc_msi_bitmap, irq)) {
1214 device_printf(dev, "invalid MSI 0x%x\n", irq);
1215 return (EINVAL);
1216 }
1217
1218 #if __ARM_ARCH >= 6
1219 mv_msi_data(irq, addr, data);
1220 #endif
1221
1222 debugf("%s: irq: %d addr: %jx data: %x\n",
1223 __func__, irq, *addr, *data);
1224
1225 return (0);
1226 }
1227
1228 static int
1229 mv_pcib_alloc_msi(device_t dev, device_t child, int count,
1230 int maxcount __unused, int *irqs)
1231 {
1232 struct mv_pcib_softc *sc;
1233 u_int start = 0, i;
1234
1235 sc = device_get_softc(dev);
1236 if (!sc->sc_msi_supported)
1237 return (ENOTSUP);
1238
1239 if (powerof2(count) == 0 || count > MSI_IRQ_NUM)
1240 return (EINVAL);
1241
1242 mtx_lock(&sc->sc_msi_mtx);
1243
1244 for (start = 0; (start + count) < MSI_IRQ_NUM; start++) {
1245 for (i = start; i < start + count; i++) {
1246 if (isset(&sc->sc_msi_bitmap, i))
1247 break;
1248 }
1249 if (i == start + count)
1250 break;
1251 }
1252
1253 if ((start + count) == MSI_IRQ_NUM) {
1254 mtx_unlock(&sc->sc_msi_mtx);
1255 return (ENXIO);
1256 }
1257
1258 for (i = start; i < start + count; i++) {
1259 setbit(&sc->sc_msi_bitmap, i);
1260 *irqs++ = MSI_IRQ + i;
1261 }
1262 debugf("%s: start: %x count: %x\n", __func__, start, count);
1263
1264 mtx_unlock(&sc->sc_msi_mtx);
1265 return (0);
1266 }
1267
1268 static int
1269 mv_pcib_release_msi(device_t dev, device_t child, int count, int *irqs)
1270 {
1271 struct mv_pcib_softc *sc;
1272 u_int i;
1273
1274 sc = device_get_softc(dev);
1275 if(!sc->sc_msi_supported)
1276 return (ENOTSUP);
1277
1278 mtx_lock(&sc->sc_msi_mtx);
1279
1280 for (i = 0; i < count; i++)
1281 clrbit(&sc->sc_msi_bitmap, irqs[i] - MSI_IRQ);
1282
1283 mtx_unlock(&sc->sc_msi_mtx);
1284 return (0);
1285 }
Cache object: 00b970c84ca0739993ec68714046aa28
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