The Design and Implementation of the FreeBSD Operating System, Second Edition
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sys/arm/mv/mv_pci.c

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    1 /*-
    2  * SPDX-License-Identifier: BSD-3-Clause
    3  *
    4  * Copyright (c) 2008 MARVELL INTERNATIONAL LTD.
    5  * Copyright (c) 2010 The FreeBSD Foundation
    6  * Copyright (c) 2010-2015 Semihalf
    7  * All rights reserved.
    8  *
    9  * Developed by Semihalf.
   10  *
   11  * Portions of this software were developed by Semihalf
   12  * under sponsorship from the FreeBSD Foundation.
   13  *
   14  * Redistribution and use in source and binary forms, with or without
   15  * modification, are permitted provided that the following conditions
   16  * are met:
   17  * 1. Redistributions of source code must retain the above copyright
   18  *    notice, this list of conditions and the following disclaimer.
   19  * 2. Redistributions in binary form must reproduce the above copyright
   20  *    notice, this list of conditions and the following disclaimer in the
   21  *    documentation and/or other materials provided with the distribution.
   22  * 3. Neither the name of MARVELL nor the names of contributors
   23  *    may be used to endorse or promote products derived from this software
   24  *    without specific prior written permission.
   25  *
   26  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   29  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
   30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   36  * SUCH DAMAGE.
   37  */
   38 
   39 /*
   40  * Marvell integrated PCI/PCI-Express controller driver.
   41  */
   42 
   43 #include <sys/cdefs.h>
   44 __FBSDID("$FreeBSD$");
   45 
   46 #include <sys/param.h>
   47 #include <sys/systm.h>
   48 #include <sys/kernel.h>
   49 #include <sys/lock.h>
   50 #include <sys/malloc.h>
   51 #include <sys/module.h>
   52 #include <sys/mutex.h>
   53 #include <sys/queue.h>
   54 #include <sys/bus.h>
   55 #include <sys/rman.h>
   56 #include <sys/endian.h>
   57 #include <sys/devmap.h>
   58 
   59 #include <machine/fdt.h>
   60 #include <machine/intr.h>
   61 
   62 #include <vm/vm.h>
   63 #include <vm/pmap.h>
   64 
   65 #include <dev/fdt/fdt_common.h>
   66 #include <dev/ofw/ofw_bus.h>
   67 #include <dev/ofw/ofw_bus_subr.h>
   68 #include <dev/ofw/ofw_pci.h>
   69 #include <dev/pci/pcivar.h>
   70 #include <dev/pci/pcireg.h>
   71 #include <dev/pci/pcib_private.h>
   72 
   73 #include "ofw_bus_if.h"
   74 #include "pcib_if.h"
   75 
   76 #include <machine/resource.h>
   77 #include <machine/bus.h>
   78 
   79 #include <arm/mv/mvreg.h>
   80 #include <arm/mv/mvvar.h>
   81 #include <arm/mv/mvwin.h>
   82 
   83 #ifdef DEBUG
   84 #define debugf(fmt, args...) do { printf(fmt,##args); } while (0)
   85 #else
   86 #define debugf(fmt, args...)
   87 #endif
   88 
   89 /*
   90  * Code and data related to fdt-based PCI configuration.
   91  *
   92  * This stuff used to be in dev/fdt/fdt_pci.c and fdt_common.h, but it was
   93  * always Marvell-specific so that was deleted and the code now lives here.
   94  */
   95 
   96 struct mv_pci_range {
   97         u_long  base_pci;
   98         u_long  base_parent;
   99         u_long  len;
  100 };
  101 
  102 #define FDT_RANGES_CELLS        ((3 + 3 + 2) * 2)
  103 #define PCI_SPACE_LEN           0x00400000
  104 
  105 static void
  106 mv_pci_range_dump(struct mv_pci_range *range)
  107 {
  108 #ifdef DEBUG
  109         printf("\n");
  110         printf("  base_pci = 0x%08lx\n", range->base_pci);
  111         printf("  base_par = 0x%08lx\n", range->base_parent);
  112         printf("  len      = 0x%08lx\n", range->len);
  113 #endif
  114 }
  115 
  116 static int
  117 mv_pci_ranges_decode(phandle_t node, struct mv_pci_range *io_space,
  118     struct mv_pci_range *mem_space)
  119 {
  120         pcell_t ranges[FDT_RANGES_CELLS];
  121         struct mv_pci_range *pci_space;
  122         pcell_t addr_cells, size_cells, par_addr_cells;
  123         pcell_t *rangesptr;
  124         pcell_t cell0, cell1, cell2;
  125         int tuple_size, tuples, i, rv, offset_cells, len;
  126         int  portid, is_io_space;
  127 
  128         /*
  129          * Retrieve 'ranges' property.
  130          */
  131         if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0)
  132                 return (EINVAL);
  133         if (addr_cells != 3 || size_cells != 2)
  134                 return (ERANGE);
  135 
  136         par_addr_cells = fdt_parent_addr_cells(node);
  137         if (par_addr_cells > 3)
  138                 return (ERANGE);
  139 
  140         len = OF_getproplen(node, "ranges");
  141         if (len > sizeof(ranges))
  142                 return (ENOMEM);
  143 
  144         if (OF_getprop(node, "ranges", ranges, sizeof(ranges)) <= 0)
  145                 return (EINVAL);
  146 
  147         tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells +
  148             size_cells);
  149         tuples = len / tuple_size;
  150 
  151         /*
  152          * Initialize the ranges so that we don't have to worry about
  153          * having them all defined in the FDT. In particular, it is
  154          * perfectly fine not to want I/O space on PCI buses.
  155          */
  156         bzero(io_space, sizeof(*io_space));
  157         bzero(mem_space, sizeof(*mem_space));
  158 
  159         rangesptr = &ranges[0];
  160         offset_cells = 0;
  161         for (i = 0; i < tuples; i++) {
  162                 cell0 = fdt_data_get((void *)rangesptr, 1);
  163                 rangesptr++;
  164                 cell1 = fdt_data_get((void *)rangesptr, 1);
  165                 rangesptr++;
  166                 cell2 = fdt_data_get((void *)rangesptr, 1);
  167                 rangesptr++;
  168                 portid = fdt_data_get((void *)(rangesptr+1), 1);
  169 
  170                 if (cell0 & 0x02000000) {
  171                         pci_space = mem_space;
  172                         is_io_space = 0;
  173                 } else if (cell0 & 0x01000000) {
  174                         pci_space = io_space;
  175                         is_io_space = 1;
  176                 } else {
  177                         rv = ERANGE;
  178                         goto out;
  179                 }
  180 
  181                 if (par_addr_cells == 3) {
  182                         /*
  183                          * This is a PCI subnode 'ranges'. Skip cell0 and
  184                          * cell1 of this entry and only use cell2.
  185                          */
  186                         offset_cells = 2;
  187                         rangesptr += offset_cells;
  188                 }
  189 
  190                 if ((par_addr_cells - offset_cells) > 2) {
  191                         rv = ERANGE;
  192                         goto out;
  193                 }
  194                 pci_space->base_parent = fdt_data_get((void *)rangesptr,
  195                     par_addr_cells - offset_cells);
  196                 rangesptr += par_addr_cells - offset_cells;
  197 
  198                 if (size_cells > 2) {
  199                         rv = ERANGE;
  200                         goto out;
  201                 }
  202                 pci_space->len = fdt_data_get((void *)rangesptr, size_cells);
  203                 rangesptr += size_cells;
  204 
  205                 pci_space->base_pci = cell2;
  206 
  207                 if (pci_space->len == 0) {
  208                         pci_space->len = PCI_SPACE_LEN;
  209                         pci_space->base_parent = fdt_immr_va +
  210                             PCI_SPACE_LEN * ( 2 * portid + is_io_space);
  211                 }
  212         }
  213         rv = 0;
  214 out:
  215         return (rv);
  216 }
  217 
  218 static int
  219 mv_pci_ranges(phandle_t node, struct mv_pci_range *io_space,
  220     struct mv_pci_range *mem_space)
  221 {
  222         int err;
  223 
  224         debugf("Processing PCI node: %x\n", node);
  225         if ((err = mv_pci_ranges_decode(node, io_space, mem_space)) != 0) {
  226                 debugf("could not decode parent PCI node 'ranges'\n");
  227                 return (err);
  228         }
  229 
  230         debugf("Post fixup dump:\n");
  231         mv_pci_range_dump(io_space);
  232         mv_pci_range_dump(mem_space);
  233         return (0);
  234 }
  235 
  236 int
  237 mv_pci_devmap(phandle_t node, struct devmap_entry *devmap, vm_offset_t io_va,
  238     vm_offset_t mem_va)
  239 {
  240         struct mv_pci_range io_space, mem_space;
  241         int error;
  242 
  243         if ((error = mv_pci_ranges_decode(node, &io_space, &mem_space)) != 0)
  244                 return (error);
  245 
  246         devmap->pd_va = (io_va ? io_va : io_space.base_parent);
  247         devmap->pd_pa = io_space.base_parent;
  248         devmap->pd_size = io_space.len;
  249         devmap++;
  250 
  251         devmap->pd_va = (mem_va ? mem_va : mem_space.base_parent);
  252         devmap->pd_pa = mem_space.base_parent;
  253         devmap->pd_size = mem_space.len;
  254         return (0);
  255 }
  256 
  257 /*
  258  * Code and data related to the Marvell pcib driver.
  259  */
  260 
  261 #define PCI_CFG_ENA             (1U << 31)
  262 #define PCI_CFG_BUS(bus)        (((bus) & 0xff) << 16)
  263 #define PCI_CFG_DEV(dev)        (((dev) & 0x1f) << 11)
  264 #define PCI_CFG_FUN(fun)        (((fun) & 0x7) << 8)
  265 #define PCI_CFG_PCIE_REG(reg)   ((reg) & 0xfc)
  266 
  267 #define PCI_REG_CFG_ADDR        0x0C78
  268 #define PCI_REG_CFG_DATA        0x0C7C
  269 
  270 #define PCIE_REG_CFG_ADDR       0x18F8
  271 #define PCIE_REG_CFG_DATA       0x18FC
  272 #define PCIE_REG_CONTROL        0x1A00
  273 #define   PCIE_CTRL_LINK1X      0x00000001
  274 #define PCIE_REG_STATUS         0x1A04
  275 #define PCIE_REG_IRQ_MASK       0x1910
  276 
  277 #define PCIE_CONTROL_ROOT_CMPLX (1 << 1)
  278 #define PCIE_CONTROL_HOT_RESET  (1 << 24)
  279 
  280 #define PCIE_LINK_TIMEOUT       1000000
  281 
  282 #define PCIE_STATUS_LINK_DOWN   1
  283 #define PCIE_STATUS_DEV_OFFS    16
  284 
  285 /* Minimum PCI Memory and I/O allocations taken from PCI spec (in bytes) */
  286 #define PCI_MIN_IO_ALLOC        4
  287 #define PCI_MIN_MEM_ALLOC       16
  288 
  289 #define BITS_PER_UINT32         (NBBY * sizeof(uint32_t))
  290 
  291 struct mv_pcib_softc {
  292         device_t        sc_dev;
  293 
  294         struct rman     sc_mem_rman;
  295         bus_addr_t      sc_mem_base;
  296         bus_addr_t      sc_mem_size;
  297         uint32_t        sc_mem_map[MV_PCI_MEM_SLICE_SIZE /
  298             (PCI_MIN_MEM_ALLOC * BITS_PER_UINT32)];
  299         int             sc_win_target;
  300         int             sc_mem_win_attr;
  301 
  302         struct rman     sc_io_rman;
  303         bus_addr_t      sc_io_base;
  304         bus_addr_t      sc_io_size;
  305         uint32_t        sc_io_map[MV_PCI_IO_SLICE_SIZE /
  306             (PCI_MIN_IO_ALLOC * BITS_PER_UINT32)];
  307         int             sc_io_win_attr;
  308 
  309         struct resource *sc_res;
  310         bus_space_handle_t sc_bsh;
  311         bus_space_tag_t sc_bst;
  312         int             sc_rid;
  313 
  314         struct mtx      sc_msi_mtx;
  315         uint32_t        sc_msi_bitmap;
  316 
  317         int             sc_busnr;               /* Host bridge bus number */
  318         int             sc_devnr;               /* Host bridge device number */
  319         int             sc_type;
  320         int             sc_mode;                /* Endpoint / Root Complex */
  321 
  322         int             sc_msi_supported;
  323         int             sc_skip_enable_procedure;
  324         int             sc_enable_find_root_slot;
  325         struct ofw_bus_iinfo    sc_pci_iinfo;
  326 
  327         int             ap_segment;             /* PCI domain */
  328 };
  329 
  330 /* Local forward prototypes */
  331 static int mv_pcib_decode_win(phandle_t, struct mv_pcib_softc *);
  332 static void mv_pcib_hw_cfginit(void);
  333 static uint32_t mv_pcib_hw_cfgread(struct mv_pcib_softc *, u_int, u_int,
  334     u_int, u_int, int);
  335 static void mv_pcib_hw_cfgwrite(struct mv_pcib_softc *, u_int, u_int,
  336     u_int, u_int, uint32_t, int);
  337 static int mv_pcib_init(struct mv_pcib_softc *, int, int);
  338 static int mv_pcib_init_all_bars(struct mv_pcib_softc *, int, int, int, int);
  339 static void mv_pcib_init_bridge(struct mv_pcib_softc *, int, int, int);
  340 static inline void pcib_write_irq_mask(struct mv_pcib_softc *, uint32_t);
  341 static void mv_pcib_enable(struct mv_pcib_softc *, uint32_t);
  342 static int mv_pcib_mem_init(struct mv_pcib_softc *);
  343 
  344 /* Forward prototypes */
  345 static int mv_pcib_probe(device_t);
  346 static int mv_pcib_attach(device_t);
  347 
  348 static struct resource *mv_pcib_alloc_resource(device_t, device_t, int, int *,
  349     rman_res_t, rman_res_t, rman_res_t, u_int);
  350 static int mv_pcib_release_resource(device_t, device_t, int, int,
  351     struct resource *);
  352 static int mv_pcib_read_ivar(device_t, device_t, int, uintptr_t *);
  353 static int mv_pcib_write_ivar(device_t, device_t, int, uintptr_t);
  354 
  355 static int mv_pcib_maxslots(device_t);
  356 static uint32_t mv_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int);
  357 static void mv_pcib_write_config(device_t, u_int, u_int, u_int, u_int,
  358     uint32_t, int);
  359 static int mv_pcib_route_interrupt(device_t, device_t, int);
  360 
  361 static int mv_pcib_alloc_msi(device_t, device_t, int, int, int *);
  362 static int mv_pcib_map_msi(device_t, device_t, int, uint64_t *, uint32_t *);
  363 static int mv_pcib_release_msi(device_t, device_t, int, int *);
  364 
  365 /*
  366  * Bus interface definitions.
  367  */
  368 static device_method_t mv_pcib_methods[] = {
  369         /* Device interface */
  370         DEVMETHOD(device_probe,                 mv_pcib_probe),
  371         DEVMETHOD(device_attach,                mv_pcib_attach),
  372 
  373         /* Bus interface */
  374         DEVMETHOD(bus_read_ivar,                mv_pcib_read_ivar),
  375         DEVMETHOD(bus_write_ivar,               mv_pcib_write_ivar),
  376         DEVMETHOD(bus_alloc_resource,           mv_pcib_alloc_resource),
  377         DEVMETHOD(bus_release_resource,         mv_pcib_release_resource),
  378         DEVMETHOD(bus_activate_resource,        bus_generic_activate_resource),
  379         DEVMETHOD(bus_deactivate_resource,      bus_generic_deactivate_resource),
  380         DEVMETHOD(bus_setup_intr,               bus_generic_setup_intr),
  381         DEVMETHOD(bus_teardown_intr,            bus_generic_teardown_intr),
  382 
  383         /* pcib interface */
  384         DEVMETHOD(pcib_maxslots,                mv_pcib_maxslots),
  385         DEVMETHOD(pcib_read_config,             mv_pcib_read_config),
  386         DEVMETHOD(pcib_write_config,            mv_pcib_write_config),
  387         DEVMETHOD(pcib_route_interrupt,         mv_pcib_route_interrupt),
  388         DEVMETHOD(pcib_request_feature,         pcib_request_feature_allow),
  389 
  390         DEVMETHOD(pcib_alloc_msi,               mv_pcib_alloc_msi),
  391         DEVMETHOD(pcib_release_msi,             mv_pcib_release_msi),
  392         DEVMETHOD(pcib_map_msi,                 mv_pcib_map_msi),
  393 
  394         /* OFW bus interface */
  395         DEVMETHOD(ofw_bus_get_compat,   ofw_bus_gen_get_compat),
  396         DEVMETHOD(ofw_bus_get_model,    ofw_bus_gen_get_model),
  397         DEVMETHOD(ofw_bus_get_name,     ofw_bus_gen_get_name),
  398         DEVMETHOD(ofw_bus_get_node,     ofw_bus_gen_get_node),
  399         DEVMETHOD(ofw_bus_get_type,     ofw_bus_gen_get_type),
  400 
  401         DEVMETHOD_END
  402 };
  403 
  404 static driver_t mv_pcib_driver = {
  405         "pcib",
  406         mv_pcib_methods,
  407         sizeof(struct mv_pcib_softc),
  408 };
  409 
  410 devclass_t pcib_devclass;
  411 
  412 DRIVER_MODULE(mv_pcib, ofwbus, mv_pcib_driver, pcib_devclass, 0, 0);
  413 DRIVER_MODULE(mv_pcib, pcib_ctrl, mv_pcib_driver, pcib_devclass, 0, 0);
  414 
  415 static struct mtx pcicfg_mtx;
  416 
  417 static int
  418 mv_pcib_probe(device_t self)
  419 {
  420         phandle_t node;
  421 
  422         node = ofw_bus_get_node(self);
  423         if (!mv_fdt_is_type(node, "pci"))
  424                 return (ENXIO);
  425 
  426         if (!(ofw_bus_is_compatible(self, "mrvl,pcie") ||
  427             ofw_bus_is_compatible(self, "mrvl,pci") ||
  428             ofw_bus_node_is_compatible(
  429             OF_parent(node), "marvell,armada-370-pcie")))
  430                 return (ENXIO);
  431 
  432         if (!ofw_bus_status_okay(self))
  433                 return (ENXIO);
  434 
  435         device_set_desc(self, "Marvell Integrated PCI/PCI-E Controller");
  436         return (BUS_PROBE_DEFAULT);
  437 }
  438 
  439 static int
  440 mv_pcib_attach(device_t self)
  441 {
  442         struct mv_pcib_softc *sc;
  443         phandle_t node, parnode;
  444         uint32_t val, reg0;
  445         int err, bus, devfn, port_id;
  446 
  447         sc = device_get_softc(self);
  448         sc->sc_dev = self;
  449 
  450         node = ofw_bus_get_node(self);
  451         parnode = OF_parent(node);
  452 
  453         if (OF_getencprop(node, "marvell,pcie-port", &(port_id),
  454             sizeof(port_id)) <= 0) {
  455                 /* If port ID does not exist in the FDT set value to 0 */
  456                 if (!OF_hasprop(node, "marvell,pcie-port"))
  457                         port_id = 0;
  458                 else
  459                         return(ENXIO);
  460         }
  461 
  462         sc->ap_segment = port_id;
  463 
  464         if (ofw_bus_node_is_compatible(node, "mrvl,pcie")) {
  465                 sc->sc_type = MV_TYPE_PCIE;
  466                 sc->sc_win_target = MV_WIN_PCIE_TARGET(port_id);
  467                 sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR(port_id);
  468                 sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR(port_id);
  469 #if __ARM_ARCH >= 6
  470                 sc->sc_skip_enable_procedure = 1;
  471 #endif
  472         } else if (ofw_bus_node_is_compatible(parnode, "marvell,armada-370-pcie")) {
  473                 sc->sc_type = MV_TYPE_PCIE;
  474                 sc->sc_win_target = MV_WIN_PCIE_TARGET_ARMADA38X(port_id);
  475                 sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR_ARMADA38X(port_id);
  476                 sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR_ARMADA38X(port_id);
  477                 sc->sc_enable_find_root_slot = 1;
  478         } else if (ofw_bus_node_is_compatible(node, "mrvl,pci")) {
  479                 sc->sc_type = MV_TYPE_PCI;
  480                 sc->sc_win_target = MV_WIN_PCI_TARGET;
  481                 sc->sc_mem_win_attr = MV_WIN_PCI_MEM_ATTR;
  482                 sc->sc_io_win_attr = MV_WIN_PCI_IO_ATTR;
  483         } else
  484                 return (ENXIO);
  485 
  486         /*
  487          * Retrieve our mem-mapped registers range.
  488          */
  489         sc->sc_rid = 0;
  490         sc->sc_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &sc->sc_rid,
  491             RF_ACTIVE);
  492         if (sc->sc_res == NULL) {
  493                 device_printf(self, "could not map memory\n");
  494                 return (ENXIO);
  495         }
  496         sc->sc_bst = rman_get_bustag(sc->sc_res);
  497         sc->sc_bsh = rman_get_bushandle(sc->sc_res);
  498 
  499         val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_CONTROL);
  500         sc->sc_mode = (val & PCIE_CONTROL_ROOT_CMPLX ? MV_MODE_ROOT :
  501             MV_MODE_ENDPOINT);
  502 
  503         /*
  504          * Get PCI interrupt info.
  505          */
  506         if (sc->sc_mode == MV_MODE_ROOT)
  507                 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(pcell_t));
  508 
  509         /*
  510          * Configure decode windows for PCI(E) access.
  511          */
  512         if (mv_pcib_decode_win(node, sc) != 0)
  513                 return (ENXIO);
  514 
  515         mv_pcib_hw_cfginit();
  516 
  517         /*
  518          * Enable PCIE device.
  519          */
  520         mv_pcib_enable(sc, port_id);
  521 
  522         /*
  523          * Memory management.
  524          */
  525         err = mv_pcib_mem_init(sc);
  526         if (err)
  527                 return (err);
  528 
  529         /*
  530          * Preliminary bus enumeration to find first linked devices and set
  531          * appropriate bus number from which should start the actual enumeration
  532          */
  533         for (bus = 0; bus < PCI_BUSMAX; bus++) {
  534                 for (devfn = 0; devfn < mv_pcib_maxslots(self); devfn++) {
  535                         reg0 = mv_pcib_read_config(self, bus, devfn, devfn & 0x7, 0x0, 4);
  536                         if (reg0 == (~0U))
  537                                 continue; /* no device */
  538                         else {
  539                                 sc->sc_busnr = bus; /* update bus number */
  540                                 break;
  541                         }
  542                 }
  543         }
  544 
  545         if (sc->sc_mode == MV_MODE_ROOT) {
  546                 err = mv_pcib_init(sc, sc->sc_busnr,
  547                     mv_pcib_maxslots(sc->sc_dev));
  548                 if (err)
  549                         goto error;
  550 
  551                 device_add_child(self, "pci", -1);
  552         } else {
  553                 sc->sc_devnr = 1;
  554                 bus_space_write_4(sc->sc_bst, sc->sc_bsh,
  555                     PCIE_REG_STATUS, 1 << PCIE_STATUS_DEV_OFFS);
  556                 device_add_child(self, "pci_ep", -1);
  557         }
  558 
  559         mtx_init(&sc->sc_msi_mtx, "msi_mtx", NULL, MTX_DEF);
  560         return (bus_generic_attach(self));
  561 
  562 error:
  563         /* XXX SYS_RES_ should be released here */
  564         rman_fini(&sc->sc_mem_rman);
  565         rman_fini(&sc->sc_io_rman);
  566 
  567         return (err);
  568 }
  569 
  570 static void
  571 mv_pcib_enable(struct mv_pcib_softc *sc, uint32_t unit)
  572 {
  573         uint32_t val;
  574         int timeout;
  575 
  576         if (sc->sc_skip_enable_procedure)
  577                 goto pcib_enable_root_mode;
  578 
  579         /*
  580          * Check if PCIE device is enabled.
  581          */
  582         if ((sc->sc_skip_enable_procedure == 0) &&
  583             (read_cpu_ctrl(CPU_CONTROL) & CPU_CONTROL_PCIE_DISABLE(unit))) {
  584                 write_cpu_ctrl(CPU_CONTROL, read_cpu_ctrl(CPU_CONTROL) &
  585                     ~(CPU_CONTROL_PCIE_DISABLE(unit)));
  586 
  587                 timeout = PCIE_LINK_TIMEOUT;
  588                 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
  589                     PCIE_REG_STATUS);
  590                 while (((val & PCIE_STATUS_LINK_DOWN) == 1) && (timeout > 0)) {
  591                         DELAY(1000);
  592                         timeout -= 1000;
  593                         val = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
  594                             PCIE_REG_STATUS);
  595                 }
  596         }
  597 
  598 pcib_enable_root_mode:
  599         if (sc->sc_mode == MV_MODE_ROOT) {
  600                 /*
  601                  * Enable PCI bridge.
  602                  */
  603                 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND);
  604                 val |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN |
  605                     PCIM_CMD_MEMEN | PCIM_CMD_PORTEN;
  606                 bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND, val);
  607         }
  608 }
  609 
  610 static int
  611 mv_pcib_mem_init(struct mv_pcib_softc *sc)
  612 {
  613         int err;
  614 
  615         /*
  616          * Memory management.
  617          */
  618         sc->sc_mem_rman.rm_type = RMAN_ARRAY;
  619         err = rman_init(&sc->sc_mem_rman);
  620         if (err)
  621                 return (err);
  622 
  623         sc->sc_io_rman.rm_type = RMAN_ARRAY;
  624         err = rman_init(&sc->sc_io_rman);
  625         if (err) {
  626                 rman_fini(&sc->sc_mem_rman);
  627                 return (err);
  628         }
  629 
  630         err = rman_manage_region(&sc->sc_mem_rman, sc->sc_mem_base,
  631             sc->sc_mem_base + sc->sc_mem_size - 1);
  632         if (err)
  633                 goto error;
  634 
  635         err = rman_manage_region(&sc->sc_io_rman, sc->sc_io_base,
  636             sc->sc_io_base + sc->sc_io_size - 1);
  637         if (err)
  638                 goto error;
  639 
  640         return (0);
  641 
  642 error:
  643         rman_fini(&sc->sc_mem_rman);
  644         rman_fini(&sc->sc_io_rman);
  645 
  646         return (err);
  647 }
  648 
  649 static inline uint32_t
  650 pcib_bit_get(uint32_t *map, uint32_t bit)
  651 {
  652         uint32_t n = bit / BITS_PER_UINT32;
  653 
  654         bit = bit % BITS_PER_UINT32;
  655         return (map[n] & (1 << bit));
  656 }
  657 
  658 static inline void
  659 pcib_bit_set(uint32_t *map, uint32_t bit)
  660 {
  661         uint32_t n = bit / BITS_PER_UINT32;
  662 
  663         bit = bit % BITS_PER_UINT32;
  664         map[n] |= (1 << bit);
  665 }
  666 
  667 static inline uint32_t
  668 pcib_map_check(uint32_t *map, uint32_t start, uint32_t bits)
  669 {
  670         uint32_t i;
  671 
  672         for (i = start; i < start + bits; i++)
  673                 if (pcib_bit_get(map, i))
  674                         return (0);
  675 
  676         return (1);
  677 }
  678 
  679 static inline void
  680 pcib_map_set(uint32_t *map, uint32_t start, uint32_t bits)
  681 {
  682         uint32_t i;
  683 
  684         for (i = start; i < start + bits; i++)
  685                 pcib_bit_set(map, i);
  686 }
  687 
  688 /*
  689  * The idea of this allocator is taken from ARM No-Cache memory
  690  * management code (sys/arm/arm/vm_machdep.c).
  691  */
  692 static bus_addr_t
  693 pcib_alloc(struct mv_pcib_softc *sc, uint32_t smask)
  694 {
  695         uint32_t bits, bits_limit, i, *map, min_alloc, size;
  696         bus_addr_t addr = 0;
  697         bus_addr_t base;
  698 
  699         if (smask & 1) {
  700                 base = sc->sc_io_base;
  701                 min_alloc = PCI_MIN_IO_ALLOC;
  702                 bits_limit = sc->sc_io_size / min_alloc;
  703                 map = sc->sc_io_map;
  704                 smask &= ~0x3;
  705         } else {
  706                 base = sc->sc_mem_base;
  707                 min_alloc = PCI_MIN_MEM_ALLOC;
  708                 bits_limit = sc->sc_mem_size / min_alloc;
  709                 map = sc->sc_mem_map;
  710                 smask &= ~0xF;
  711         }
  712 
  713         size = ~smask + 1;
  714         bits = size / min_alloc;
  715 
  716         for (i = 0; i + bits <= bits_limit; i += bits)
  717                 if (pcib_map_check(map, i, bits)) {
  718                         pcib_map_set(map, i, bits);
  719                         addr = base + (i * min_alloc);
  720                         return (addr);
  721                 }
  722 
  723         return (addr);
  724 }
  725 
  726 static int
  727 mv_pcib_init_bar(struct mv_pcib_softc *sc, int bus, int slot, int func,
  728     int barno)
  729 {
  730         uint32_t addr, bar;
  731         int reg, width;
  732 
  733         reg = PCIR_BAR(barno);
  734 
  735         /*
  736          * Need to init the BAR register with 0xffffffff before correct
  737          * value can be read.
  738          */
  739         mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4);
  740         bar = mv_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4);
  741         if (bar == 0)
  742                 return (1);
  743 
  744         /* Calculate BAR size: 64 or 32 bit (in 32-bit units) */
  745         width = ((bar & 7) == 4) ? 2 : 1;
  746 
  747         addr = pcib_alloc(sc, bar);
  748         if (!addr)
  749                 return (-1);
  750 
  751         if (bootverbose)
  752                 printf("PCI %u:%u:%u: reg %x: smask=%08x: addr=%08x\n",
  753                     bus, slot, func, reg, bar, addr);
  754 
  755         mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4);
  756         if (width == 2)
  757                 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg + 4,
  758                     0, 4);
  759 
  760         return (width);
  761 }
  762 
  763 static void
  764 mv_pcib_init_bridge(struct mv_pcib_softc *sc, int bus, int slot, int func)
  765 {
  766         bus_addr_t io_base, mem_base;
  767         uint32_t io_limit, mem_limit;
  768         int secbus;
  769 
  770         io_base = sc->sc_io_base;
  771         io_limit = io_base + sc->sc_io_size - 1;
  772         mem_base = sc->sc_mem_base;
  773         mem_limit = mem_base + sc->sc_mem_size - 1;
  774 
  775         /* Configure I/O decode registers */
  776         mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEL_1,
  777             io_base >> 8, 1);
  778         mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEH_1,
  779             io_base >> 16, 2);
  780         mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITL_1,
  781             io_limit >> 8, 1);
  782         mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITH_1,
  783             io_limit >> 16, 2);
  784 
  785         /* Configure memory decode registers */
  786         mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMBASE_1,
  787             mem_base >> 16, 2);
  788         mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMLIMIT_1,
  789             mem_limit >> 16, 2);
  790 
  791         /* Disable memory prefetch decode */
  792         mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEL_1,
  793             0x10, 2);
  794         mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEH_1,
  795             0x0, 4);
  796         mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITL_1,
  797             0xF, 2);
  798         mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITH_1,
  799             0x0, 4);
  800 
  801         secbus = mv_pcib_read_config(sc->sc_dev, bus, slot, func,
  802             PCIR_SECBUS_1, 1);
  803 
  804         /* Configure buses behind the bridge */
  805         mv_pcib_init(sc, secbus, PCI_SLOTMAX);
  806 }
  807 
  808 static int
  809 mv_pcib_init(struct mv_pcib_softc *sc, int bus, int maxslot)
  810 {
  811         int slot, func, maxfunc, error;
  812         uint8_t hdrtype, command, class, subclass;
  813 
  814         for (slot = 0; slot <= maxslot; slot++) {
  815                 maxfunc = 0;
  816                 for (func = 0; func <= maxfunc; func++) {
  817                         hdrtype = mv_pcib_read_config(sc->sc_dev, bus, slot,
  818                             func, PCIR_HDRTYPE, 1);
  819 
  820                         if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
  821                                 continue;
  822 
  823                         if (func == 0 && (hdrtype & PCIM_MFDEV))
  824                                 maxfunc = PCI_FUNCMAX;
  825 
  826                         command = mv_pcib_read_config(sc->sc_dev, bus, slot,
  827                             func, PCIR_COMMAND, 1);
  828                         command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN);
  829                         mv_pcib_write_config(sc->sc_dev, bus, slot, func,
  830                             PCIR_COMMAND, command, 1);
  831 
  832                         error = mv_pcib_init_all_bars(sc, bus, slot, func,
  833                             hdrtype);
  834 
  835                         if (error)
  836                                 return (error);
  837 
  838                         command |= PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN |
  839                             PCIM_CMD_PORTEN;
  840                         mv_pcib_write_config(sc->sc_dev, bus, slot, func,
  841                             PCIR_COMMAND, command, 1);
  842 
  843                         /* Handle PCI-PCI bridges */
  844                         class = mv_pcib_read_config(sc->sc_dev, bus, slot,
  845                             func, PCIR_CLASS, 1);
  846                         subclass = mv_pcib_read_config(sc->sc_dev, bus, slot,
  847                             func, PCIR_SUBCLASS, 1);
  848 
  849                         if (class != PCIC_BRIDGE ||
  850                             subclass != PCIS_BRIDGE_PCI)
  851                                 continue;
  852 
  853                         mv_pcib_init_bridge(sc, bus, slot, func);
  854                 }
  855         }
  856 
  857         /* Enable all ABCD interrupts */
  858         pcib_write_irq_mask(sc, (0xF << 24));
  859 
  860         return (0);
  861 }
  862 
  863 static int
  864 mv_pcib_init_all_bars(struct mv_pcib_softc *sc, int bus, int slot,
  865     int func, int hdrtype)
  866 {
  867         int maxbar, bar, i;
  868 
  869         maxbar = (hdrtype & PCIM_HDRTYPE) ? 0 : 6;
  870         bar = 0;
  871 
  872         /* Program the base address registers */
  873         while (bar < maxbar) {
  874                 i = mv_pcib_init_bar(sc, bus, slot, func, bar);
  875                 bar += i;
  876                 if (i < 0) {
  877                         device_printf(sc->sc_dev,
  878                             "PCI IO/Memory space exhausted\n");
  879                         return (ENOMEM);
  880                 }
  881         }
  882 
  883         return (0);
  884 }
  885 
  886 static struct resource *
  887 mv_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
  888     rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
  889 {
  890         struct mv_pcib_softc *sc = device_get_softc(dev);
  891         struct rman *rm = NULL;
  892         struct resource *res;
  893 
  894         switch (type) {
  895         case SYS_RES_IOPORT:
  896                 rm = &sc->sc_io_rman;
  897                 break;
  898         case SYS_RES_MEMORY:
  899                 rm = &sc->sc_mem_rman;
  900                 break;
  901 #ifdef PCI_RES_BUS
  902         case PCI_RES_BUS:
  903                 return (pci_domain_alloc_bus(sc->ap_segment, child, rid, start,
  904                     end, count, flags));
  905 #endif
  906         default:
  907                 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
  908                     type, rid, start, end, count, flags));
  909         }
  910 
  911         if (RMAN_IS_DEFAULT_RANGE(start, end)) {
  912                 start = sc->sc_mem_base;
  913                 end = sc->sc_mem_base + sc->sc_mem_size - 1;
  914                 count = sc->sc_mem_size;
  915         }
  916 
  917         if ((start < sc->sc_mem_base) || (start + count - 1 != end) ||
  918             (end > sc->sc_mem_base + sc->sc_mem_size - 1))
  919                 return (NULL);
  920 
  921         res = rman_reserve_resource(rm, start, end, count, flags, child);
  922         if (res == NULL)
  923                 return (NULL);
  924 
  925         rman_set_rid(res, *rid);
  926         rman_set_bustag(res, fdtbus_bs_tag);
  927         rman_set_bushandle(res, start);
  928 
  929         if (flags & RF_ACTIVE)
  930                 if (bus_activate_resource(child, type, *rid, res)) {
  931                         rman_release_resource(res);
  932                         return (NULL);
  933                 }
  934 
  935         return (res);
  936 }
  937 
  938 static int
  939 mv_pcib_release_resource(device_t dev, device_t child, int type, int rid,
  940     struct resource *res)
  941 {
  942 #ifdef PCI_RES_BUS
  943         struct mv_pcib_softc *sc = device_get_softc(dev);
  944 
  945         if (type == PCI_RES_BUS)
  946                 return (pci_domain_release_bus(sc->ap_segment, child, rid, res));
  947 #endif
  948         if (type != SYS_RES_IOPORT && type != SYS_RES_MEMORY)
  949                 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
  950                     type, rid, res));
  951 
  952         return (rman_release_resource(res));
  953 }
  954 
  955 static int
  956 mv_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
  957 {
  958         struct mv_pcib_softc *sc = device_get_softc(dev);
  959 
  960         switch (which) {
  961         case PCIB_IVAR_BUS:
  962                 *result = sc->sc_busnr;
  963                 return (0);
  964         case PCIB_IVAR_DOMAIN:
  965                 *result = device_get_unit(dev);
  966                 return (0);
  967         }
  968 
  969         return (ENOENT);
  970 }
  971 
  972 static int
  973 mv_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
  974 {
  975         struct mv_pcib_softc *sc = device_get_softc(dev);
  976 
  977         switch (which) {
  978         case PCIB_IVAR_BUS:
  979                 sc->sc_busnr = value;
  980                 return (0);
  981         }
  982 
  983         return (ENOENT);
  984 }
  985 
  986 static inline void
  987 pcib_write_irq_mask(struct mv_pcib_softc *sc, uint32_t mask)
  988 {
  989 
  990         if (sc->sc_type != MV_TYPE_PCIE)
  991                 return;
  992 
  993         bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_IRQ_MASK, mask);
  994 }
  995 
  996 static void
  997 mv_pcib_hw_cfginit(void)
  998 {
  999         static int opened = 0;
 1000 
 1001         if (opened)
 1002                 return;
 1003 
 1004         mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
 1005         opened = 1;
 1006 }
 1007 
 1008 static uint32_t
 1009 mv_pcib_hw_cfgread(struct mv_pcib_softc *sc, u_int bus, u_int slot,
 1010     u_int func, u_int reg, int bytes)
 1011 {
 1012         uint32_t addr, data, ca, cd;
 1013 
 1014         ca = (sc->sc_type != MV_TYPE_PCI) ?
 1015             PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR;
 1016         cd = (sc->sc_type != MV_TYPE_PCI) ?
 1017             PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA;
 1018         addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) |
 1019             PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg);
 1020 
 1021         mtx_lock_spin(&pcicfg_mtx);
 1022         bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr);
 1023 
 1024         data = ~0;
 1025         switch (bytes) {
 1026         case 1:
 1027                 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh,
 1028                     cd + (reg & 3));
 1029                 break;
 1030         case 2:
 1031                 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh,
 1032                     cd + (reg & 2)));
 1033                 break;
 1034         case 4:
 1035                 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh,
 1036                     cd));
 1037                 break;
 1038         }
 1039         mtx_unlock_spin(&pcicfg_mtx);
 1040         return (data);
 1041 }
 1042 
 1043 static void
 1044 mv_pcib_hw_cfgwrite(struct mv_pcib_softc *sc, u_int bus, u_int slot,
 1045     u_int func, u_int reg, uint32_t data, int bytes)
 1046 {
 1047         uint32_t addr, ca, cd;
 1048 
 1049         ca = (sc->sc_type != MV_TYPE_PCI) ?
 1050             PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR;
 1051         cd = (sc->sc_type != MV_TYPE_PCI) ?
 1052             PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA;
 1053         addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) |
 1054             PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg);
 1055 
 1056         mtx_lock_spin(&pcicfg_mtx);
 1057         bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr);
 1058 
 1059         switch (bytes) {
 1060         case 1:
 1061                 bus_space_write_1(sc->sc_bst, sc->sc_bsh,
 1062                     cd + (reg & 3), data);
 1063                 break;
 1064         case 2:
 1065                 bus_space_write_2(sc->sc_bst, sc->sc_bsh,
 1066                     cd + (reg & 2), htole16(data));
 1067                 break;
 1068         case 4:
 1069                 bus_space_write_4(sc->sc_bst, sc->sc_bsh,
 1070                     cd, htole32(data));
 1071                 break;
 1072         }
 1073         mtx_unlock_spin(&pcicfg_mtx);
 1074 }
 1075 
 1076 static int
 1077 mv_pcib_maxslots(device_t dev)
 1078 {
 1079         struct mv_pcib_softc *sc = device_get_softc(dev);
 1080 
 1081         return ((sc->sc_type != MV_TYPE_PCI) ? 1 : PCI_SLOTMAX);
 1082 }
 1083 
 1084 static int
 1085 mv_pcib_root_slot(device_t dev, u_int bus, u_int slot, u_int func)
 1086 {
 1087         struct mv_pcib_softc *sc = device_get_softc(dev);
 1088         uint32_t vendor, device;
 1089 
 1090         /* On platforms other than Armada38x, root link is always at slot 0 */
 1091         if (!sc->sc_enable_find_root_slot)
 1092                 return (slot == 0);
 1093 
 1094         vendor = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_VENDOR,
 1095             PCIR_VENDOR_LENGTH);
 1096         device = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_DEVICE,
 1097             PCIR_DEVICE_LENGTH) & MV_DEV_FAMILY_MASK;
 1098 
 1099         return (vendor == PCI_VENDORID_MRVL && device == MV_DEV_ARMADA38X);
 1100 }
 1101 
 1102 static uint32_t
 1103 mv_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
 1104     u_int reg, int bytes)
 1105 {
 1106         struct mv_pcib_softc *sc = device_get_softc(dev);
 1107 
 1108         /* Return ~0 if link is inactive or trying to read from Root */
 1109         if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) &
 1110             PCIE_STATUS_LINK_DOWN) || mv_pcib_root_slot(dev, bus, slot, func))
 1111                 return (~0U);
 1112 
 1113         return (mv_pcib_hw_cfgread(sc, bus, slot, func, reg, bytes));
 1114 }
 1115 
 1116 static void
 1117 mv_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
 1118     u_int reg, uint32_t val, int bytes)
 1119 {
 1120         struct mv_pcib_softc *sc = device_get_softc(dev);
 1121 
 1122         /* Return if link is inactive or trying to write to Root */
 1123         if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) &
 1124             PCIE_STATUS_LINK_DOWN) || mv_pcib_root_slot(dev, bus, slot, func))
 1125                 return;
 1126 
 1127         mv_pcib_hw_cfgwrite(sc, bus, slot, func, reg, val, bytes);
 1128 }
 1129 
 1130 static int
 1131 mv_pcib_route_interrupt(device_t bus, device_t dev, int pin)
 1132 {
 1133         struct mv_pcib_softc *sc;
 1134         struct ofw_pci_register reg;
 1135         uint32_t pintr, mintr[4];
 1136         int icells;
 1137         phandle_t iparent;
 1138 
 1139         sc = device_get_softc(bus);
 1140         pintr = pin;
 1141 
 1142         /* Fabricate imap information in case this isn't an OFW device */
 1143         bzero(&reg, sizeof(reg));
 1144         reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) |
 1145             (pci_get_slot(dev) << OFW_PCI_PHYS_HI_DEVICESHIFT) |
 1146             (pci_get_function(dev) << OFW_PCI_PHYS_HI_FUNCTIONSHIFT);
 1147 
 1148         icells = ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo,
 1149             &reg, sizeof(reg), &pintr, sizeof(pintr), mintr, sizeof(mintr),
 1150             &iparent);
 1151         if (icells > 0)
 1152                 return (ofw_bus_map_intr(dev, iparent, icells, mintr));
 1153 
 1154         /* Maybe it's a real interrupt, not an intpin */
 1155         if (pin > 4)
 1156                 return (pin);
 1157 
 1158         device_printf(bus, "could not route pin %d for device %d.%d\n",
 1159             pin, pci_get_slot(dev), pci_get_function(dev));
 1160         return (PCI_INVALID_IRQ);
 1161 }
 1162 
 1163 static int
 1164 mv_pcib_decode_win(phandle_t node, struct mv_pcib_softc *sc)
 1165 {
 1166         struct mv_pci_range io_space, mem_space;
 1167         device_t dev;
 1168         int error;
 1169 
 1170         dev = sc->sc_dev;
 1171 
 1172         if ((error = mv_pci_ranges(node, &io_space, &mem_space)) != 0) {
 1173                 device_printf(dev, "could not retrieve 'ranges' data\n");
 1174                 return (error);
 1175         }
 1176 
 1177         /* Configure CPU decoding windows */
 1178         error = decode_win_cpu_set(sc->sc_win_target,
 1179             sc->sc_io_win_attr, io_space.base_parent, io_space.len, ~0);
 1180         if (error < 0) {
 1181                 device_printf(dev, "could not set up CPU decode "
 1182                     "window for PCI IO\n");
 1183                 return (ENXIO);
 1184         }
 1185         error = decode_win_cpu_set(sc->sc_win_target,
 1186             sc->sc_mem_win_attr, mem_space.base_parent, mem_space.len,
 1187             mem_space.base_parent);
 1188         if (error < 0) {
 1189                 device_printf(dev, "could not set up CPU decode "
 1190                     "windows for PCI MEM\n");
 1191                 return (ENXIO);
 1192         }
 1193 
 1194         sc->sc_io_base = io_space.base_parent;
 1195         sc->sc_io_size = io_space.len;
 1196 
 1197         sc->sc_mem_base = mem_space.base_parent;
 1198         sc->sc_mem_size = mem_space.len;
 1199 
 1200         return (0);
 1201 }
 1202 
 1203 static int
 1204 mv_pcib_map_msi(device_t dev, device_t child, int irq, uint64_t *addr,
 1205     uint32_t *data)
 1206 {
 1207         struct mv_pcib_softc *sc;
 1208 
 1209         sc = device_get_softc(dev);
 1210         if (!sc->sc_msi_supported)
 1211                 return (ENOTSUP);
 1212 
 1213         irq = irq - MSI_IRQ;
 1214 
 1215         /* validate parameters */
 1216         if (isclr(&sc->sc_msi_bitmap, irq)) {
 1217                 device_printf(dev, "invalid MSI 0x%x\n", irq);
 1218                 return (EINVAL);
 1219         }
 1220 
 1221 #if __ARM_ARCH >= 6 
 1222         mv_msi_data(irq, addr, data);
 1223 #endif
 1224 
 1225         debugf("%s: irq: %d addr: %jx data: %x\n",
 1226             __func__, irq, *addr, *data);
 1227 
 1228         return (0);
 1229 }
 1230 
 1231 static int
 1232 mv_pcib_alloc_msi(device_t dev, device_t child, int count,
 1233     int maxcount __unused, int *irqs)
 1234 {
 1235         struct mv_pcib_softc *sc;
 1236         u_int start = 0, i;
 1237 
 1238         sc = device_get_softc(dev);
 1239         if (!sc->sc_msi_supported)
 1240                 return (ENOTSUP);
 1241 
 1242         if (powerof2(count) == 0 || count > MSI_IRQ_NUM)
 1243                 return (EINVAL);
 1244 
 1245         mtx_lock(&sc->sc_msi_mtx);
 1246 
 1247         for (start = 0; (start + count) < MSI_IRQ_NUM; start++) {
 1248                 for (i = start; i < start + count; i++) {
 1249                         if (isset(&sc->sc_msi_bitmap, i))
 1250                                 break;
 1251                 }
 1252                 if (i == start + count)
 1253                         break;
 1254         }
 1255 
 1256         if ((start + count) == MSI_IRQ_NUM) {
 1257                 mtx_unlock(&sc->sc_msi_mtx);
 1258                 return (ENXIO);
 1259         }
 1260 
 1261         for (i = start; i < start + count; i++) {
 1262                 setbit(&sc->sc_msi_bitmap, i);
 1263                 *irqs++ = MSI_IRQ + i;
 1264         }
 1265         debugf("%s: start: %x count: %x\n", __func__, start, count);
 1266 
 1267         mtx_unlock(&sc->sc_msi_mtx);
 1268         return (0);
 1269 }
 1270 
 1271 static int
 1272 mv_pcib_release_msi(device_t dev, device_t child, int count, int *irqs)
 1273 {
 1274         struct mv_pcib_softc *sc;
 1275         u_int i;
 1276 
 1277         sc = device_get_softc(dev);
 1278         if(!sc->sc_msi_supported)
 1279                 return (ENOTSUP);
 1280 
 1281         mtx_lock(&sc->sc_msi_mtx);
 1282 
 1283         for (i = 0; i < count; i++)
 1284                 clrbit(&sc->sc_msi_bitmap, irqs[i] - MSI_IRQ);
 1285 
 1286         mtx_unlock(&sc->sc_msi_mtx);
 1287         return (0);
 1288 }

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