FreeBSD/Linux Kernel Cross Reference
sys/arm/mv/mv_pci.c
1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright (c) 2008 MARVELL INTERNATIONAL LTD.
5 * Copyright (c) 2010 The FreeBSD Foundation
6 * Copyright (c) 2010-2015 Semihalf
7 * All rights reserved.
8 *
9 * Developed by Semihalf.
10 *
11 * Portions of this software were developed by Semihalf
12 * under sponsorship from the FreeBSD Foundation.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 * 3. Neither the name of MARVELL nor the names of contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * SUCH DAMAGE.
37 */
38
39 /*
40 * Marvell integrated PCI/PCI-Express controller driver.
41 */
42
43 #include <sys/cdefs.h>
44 __FBSDID("$FreeBSD$");
45
46 #include <sys/param.h>
47 #include <sys/systm.h>
48 #include <sys/kernel.h>
49 #include <sys/lock.h>
50 #include <sys/malloc.h>
51 #include <sys/module.h>
52 #include <sys/mutex.h>
53 #include <sys/queue.h>
54 #include <sys/bus.h>
55 #include <sys/rman.h>
56 #include <sys/endian.h>
57 #include <sys/devmap.h>
58
59 #include <machine/fdt.h>
60 #include <machine/intr.h>
61
62 #include <vm/vm.h>
63 #include <vm/pmap.h>
64
65 #include <dev/fdt/fdt_common.h>
66 #include <dev/ofw/ofw_bus.h>
67 #include <dev/ofw/ofw_bus_subr.h>
68 #include <dev/ofw/ofw_pci.h>
69 #include <dev/pci/pcivar.h>
70 #include <dev/pci/pcireg.h>
71 #include <dev/pci/pcib_private.h>
72
73 #include "ofw_bus_if.h"
74 #include "pcib_if.h"
75
76 #include <machine/resource.h>
77 #include <machine/bus.h>
78
79 #include <arm/mv/mvreg.h>
80 #include <arm/mv/mvvar.h>
81 #include <arm/mv/mvwin.h>
82
83 #ifdef DEBUG
84 #define debugf(fmt, args...) do { printf(fmt,##args); } while (0)
85 #else
86 #define debugf(fmt, args...)
87 #endif
88
89 /*
90 * Code and data related to fdt-based PCI configuration.
91 *
92 * This stuff used to be in dev/fdt/fdt_pci.c and fdt_common.h, but it was
93 * always Marvell-specific so that was deleted and the code now lives here.
94 */
95
96 struct mv_pci_range {
97 u_long base_pci;
98 u_long base_parent;
99 u_long len;
100 };
101
102 #define FDT_RANGES_CELLS ((3 + 3 + 2) * 2)
103 #define PCI_SPACE_LEN 0x00400000
104
105 static void
106 mv_pci_range_dump(struct mv_pci_range *range)
107 {
108 #ifdef DEBUG
109 printf("\n");
110 printf(" base_pci = 0x%08lx\n", range->base_pci);
111 printf(" base_par = 0x%08lx\n", range->base_parent);
112 printf(" len = 0x%08lx\n", range->len);
113 #endif
114 }
115
116 static int
117 mv_pci_ranges_decode(phandle_t node, struct mv_pci_range *io_space,
118 struct mv_pci_range *mem_space)
119 {
120 pcell_t ranges[FDT_RANGES_CELLS];
121 struct mv_pci_range *pci_space;
122 pcell_t addr_cells, size_cells, par_addr_cells;
123 pcell_t *rangesptr;
124 pcell_t cell0, cell1, cell2;
125 int tuple_size, tuples, i, rv, offset_cells, len;
126 int portid, is_io_space;
127
128 /*
129 * Retrieve 'ranges' property.
130 */
131 if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0)
132 return (EINVAL);
133 if (addr_cells != 3 || size_cells != 2)
134 return (ERANGE);
135
136 par_addr_cells = fdt_parent_addr_cells(node);
137 if (par_addr_cells > 3)
138 return (ERANGE);
139
140 len = OF_getproplen(node, "ranges");
141 if (len > sizeof(ranges))
142 return (ENOMEM);
143
144 if (OF_getprop(node, "ranges", ranges, sizeof(ranges)) <= 0)
145 return (EINVAL);
146
147 tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells +
148 size_cells);
149 tuples = len / tuple_size;
150
151 /*
152 * Initialize the ranges so that we don't have to worry about
153 * having them all defined in the FDT. In particular, it is
154 * perfectly fine not to want I/O space on PCI buses.
155 */
156 bzero(io_space, sizeof(*io_space));
157 bzero(mem_space, sizeof(*mem_space));
158
159 rangesptr = &ranges[0];
160 offset_cells = 0;
161 for (i = 0; i < tuples; i++) {
162 cell0 = fdt_data_get((void *)rangesptr, 1);
163 rangesptr++;
164 cell1 = fdt_data_get((void *)rangesptr, 1);
165 rangesptr++;
166 cell2 = fdt_data_get((void *)rangesptr, 1);
167 rangesptr++;
168 portid = fdt_data_get((void *)(rangesptr+1), 1);
169
170 if (cell0 & 0x02000000) {
171 pci_space = mem_space;
172 is_io_space = 0;
173 } else if (cell0 & 0x01000000) {
174 pci_space = io_space;
175 is_io_space = 1;
176 } else {
177 rv = ERANGE;
178 goto out;
179 }
180
181 if (par_addr_cells == 3) {
182 /*
183 * This is a PCI subnode 'ranges'. Skip cell0 and
184 * cell1 of this entry and only use cell2.
185 */
186 offset_cells = 2;
187 rangesptr += offset_cells;
188 }
189
190 if ((par_addr_cells - offset_cells) > 2) {
191 rv = ERANGE;
192 goto out;
193 }
194 pci_space->base_parent = fdt_data_get((void *)rangesptr,
195 par_addr_cells - offset_cells);
196 rangesptr += par_addr_cells - offset_cells;
197
198 if (size_cells > 2) {
199 rv = ERANGE;
200 goto out;
201 }
202 pci_space->len = fdt_data_get((void *)rangesptr, size_cells);
203 rangesptr += size_cells;
204
205 pci_space->base_pci = cell2;
206
207 if (pci_space->len == 0) {
208 pci_space->len = PCI_SPACE_LEN;
209 pci_space->base_parent = fdt_immr_va +
210 PCI_SPACE_LEN * ( 2 * portid + is_io_space);
211 }
212 }
213 rv = 0;
214 out:
215 return (rv);
216 }
217
218 static int
219 mv_pci_ranges(phandle_t node, struct mv_pci_range *io_space,
220 struct mv_pci_range *mem_space)
221 {
222 int err;
223
224 debugf("Processing PCI node: %x\n", node);
225 if ((err = mv_pci_ranges_decode(node, io_space, mem_space)) != 0) {
226 debugf("could not decode parent PCI node 'ranges'\n");
227 return (err);
228 }
229
230 debugf("Post fixup dump:\n");
231 mv_pci_range_dump(io_space);
232 mv_pci_range_dump(mem_space);
233 return (0);
234 }
235
236 int
237 mv_pci_devmap(phandle_t node, struct devmap_entry *devmap, vm_offset_t io_va,
238 vm_offset_t mem_va)
239 {
240 struct mv_pci_range io_space, mem_space;
241 int error;
242
243 if ((error = mv_pci_ranges_decode(node, &io_space, &mem_space)) != 0)
244 return (error);
245
246 devmap->pd_va = (io_va ? io_va : io_space.base_parent);
247 devmap->pd_pa = io_space.base_parent;
248 devmap->pd_size = io_space.len;
249 devmap++;
250
251 devmap->pd_va = (mem_va ? mem_va : mem_space.base_parent);
252 devmap->pd_pa = mem_space.base_parent;
253 devmap->pd_size = mem_space.len;
254 return (0);
255 }
256
257 /*
258 * Code and data related to the Marvell pcib driver.
259 */
260
261 #define PCI_CFG_ENA (1U << 31)
262 #define PCI_CFG_BUS(bus) (((bus) & 0xff) << 16)
263 #define PCI_CFG_DEV(dev) (((dev) & 0x1f) << 11)
264 #define PCI_CFG_FUN(fun) (((fun) & 0x7) << 8)
265 #define PCI_CFG_PCIE_REG(reg) ((reg) & 0xfc)
266
267 #define PCI_REG_CFG_ADDR 0x0C78
268 #define PCI_REG_CFG_DATA 0x0C7C
269
270 #define PCIE_REG_CFG_ADDR 0x18F8
271 #define PCIE_REG_CFG_DATA 0x18FC
272 #define PCIE_REG_CONTROL 0x1A00
273 #define PCIE_CTRL_LINK1X 0x00000001
274 #define PCIE_REG_STATUS 0x1A04
275 #define PCIE_REG_IRQ_MASK 0x1910
276
277 #define PCIE_CONTROL_ROOT_CMPLX (1 << 1)
278 #define PCIE_CONTROL_HOT_RESET (1 << 24)
279
280 #define PCIE_LINK_TIMEOUT 1000000
281
282 #define PCIE_STATUS_LINK_DOWN 1
283 #define PCIE_STATUS_DEV_OFFS 16
284
285 /* Minimum PCI Memory and I/O allocations taken from PCI spec (in bytes) */
286 #define PCI_MIN_IO_ALLOC 4
287 #define PCI_MIN_MEM_ALLOC 16
288
289 #define BITS_PER_UINT32 (NBBY * sizeof(uint32_t))
290
291 struct mv_pcib_softc {
292 device_t sc_dev;
293
294 struct rman sc_mem_rman;
295 bus_addr_t sc_mem_base;
296 bus_addr_t sc_mem_size;
297 uint32_t sc_mem_map[MV_PCI_MEM_SLICE_SIZE /
298 (PCI_MIN_MEM_ALLOC * BITS_PER_UINT32)];
299 int sc_win_target;
300 int sc_mem_win_attr;
301
302 struct rman sc_io_rman;
303 bus_addr_t sc_io_base;
304 bus_addr_t sc_io_size;
305 uint32_t sc_io_map[MV_PCI_IO_SLICE_SIZE /
306 (PCI_MIN_IO_ALLOC * BITS_PER_UINT32)];
307 int sc_io_win_attr;
308
309 struct resource *sc_res;
310 bus_space_handle_t sc_bsh;
311 bus_space_tag_t sc_bst;
312 int sc_rid;
313
314 struct mtx sc_msi_mtx;
315 uint32_t sc_msi_bitmap;
316
317 int sc_busnr; /* Host bridge bus number */
318 int sc_devnr; /* Host bridge device number */
319 int sc_type;
320 int sc_mode; /* Endpoint / Root Complex */
321
322 int sc_msi_supported;
323 int sc_skip_enable_procedure;
324 int sc_enable_find_root_slot;
325 struct ofw_bus_iinfo sc_pci_iinfo;
326
327 int ap_segment; /* PCI domain */
328 };
329
330 /* Local forward prototypes */
331 static int mv_pcib_decode_win(phandle_t, struct mv_pcib_softc *);
332 static void mv_pcib_hw_cfginit(void);
333 static uint32_t mv_pcib_hw_cfgread(struct mv_pcib_softc *, u_int, u_int,
334 u_int, u_int, int);
335 static void mv_pcib_hw_cfgwrite(struct mv_pcib_softc *, u_int, u_int,
336 u_int, u_int, uint32_t, int);
337 static int mv_pcib_init(struct mv_pcib_softc *, int, int);
338 static int mv_pcib_init_all_bars(struct mv_pcib_softc *, int, int, int, int);
339 static void mv_pcib_init_bridge(struct mv_pcib_softc *, int, int, int);
340 static inline void pcib_write_irq_mask(struct mv_pcib_softc *, uint32_t);
341 static void mv_pcib_enable(struct mv_pcib_softc *, uint32_t);
342 static int mv_pcib_mem_init(struct mv_pcib_softc *);
343
344 /* Forward prototypes */
345 static int mv_pcib_probe(device_t);
346 static int mv_pcib_attach(device_t);
347
348 static struct resource *mv_pcib_alloc_resource(device_t, device_t, int, int *,
349 rman_res_t, rman_res_t, rman_res_t, u_int);
350 static int mv_pcib_release_resource(device_t, device_t, int, int,
351 struct resource *);
352 static int mv_pcib_read_ivar(device_t, device_t, int, uintptr_t *);
353 static int mv_pcib_write_ivar(device_t, device_t, int, uintptr_t);
354
355 static int mv_pcib_maxslots(device_t);
356 static uint32_t mv_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int);
357 static void mv_pcib_write_config(device_t, u_int, u_int, u_int, u_int,
358 uint32_t, int);
359 static int mv_pcib_route_interrupt(device_t, device_t, int);
360
361 static int mv_pcib_alloc_msi(device_t, device_t, int, int, int *);
362 static int mv_pcib_map_msi(device_t, device_t, int, uint64_t *, uint32_t *);
363 static int mv_pcib_release_msi(device_t, device_t, int, int *);
364
365 /*
366 * Bus interface definitions.
367 */
368 static device_method_t mv_pcib_methods[] = {
369 /* Device interface */
370 DEVMETHOD(device_probe, mv_pcib_probe),
371 DEVMETHOD(device_attach, mv_pcib_attach),
372
373 /* Bus interface */
374 DEVMETHOD(bus_read_ivar, mv_pcib_read_ivar),
375 DEVMETHOD(bus_write_ivar, mv_pcib_write_ivar),
376 DEVMETHOD(bus_alloc_resource, mv_pcib_alloc_resource),
377 DEVMETHOD(bus_release_resource, mv_pcib_release_resource),
378 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
379 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
380 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
381 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
382
383 /* pcib interface */
384 DEVMETHOD(pcib_maxslots, mv_pcib_maxslots),
385 DEVMETHOD(pcib_read_config, mv_pcib_read_config),
386 DEVMETHOD(pcib_write_config, mv_pcib_write_config),
387 DEVMETHOD(pcib_route_interrupt, mv_pcib_route_interrupt),
388 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow),
389
390 DEVMETHOD(pcib_alloc_msi, mv_pcib_alloc_msi),
391 DEVMETHOD(pcib_release_msi, mv_pcib_release_msi),
392 DEVMETHOD(pcib_map_msi, mv_pcib_map_msi),
393
394 /* OFW bus interface */
395 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat),
396 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model),
397 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name),
398 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node),
399 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type),
400
401 DEVMETHOD_END
402 };
403
404 static driver_t mv_pcib_driver = {
405 "pcib",
406 mv_pcib_methods,
407 sizeof(struct mv_pcib_softc),
408 };
409
410 devclass_t pcib_devclass;
411
412 DRIVER_MODULE(mv_pcib, ofwbus, mv_pcib_driver, pcib_devclass, 0, 0);
413 DRIVER_MODULE(mv_pcib, pcib_ctrl, mv_pcib_driver, pcib_devclass, 0, 0);
414
415 static struct mtx pcicfg_mtx;
416
417 static int
418 mv_pcib_probe(device_t self)
419 {
420 phandle_t node;
421
422 node = ofw_bus_get_node(self);
423 if (!mv_fdt_is_type(node, "pci"))
424 return (ENXIO);
425
426 if (!(ofw_bus_is_compatible(self, "mrvl,pcie") ||
427 ofw_bus_is_compatible(self, "mrvl,pci") ||
428 ofw_bus_node_is_compatible(
429 OF_parent(node), "marvell,armada-370-pcie")))
430 return (ENXIO);
431
432 if (!ofw_bus_status_okay(self))
433 return (ENXIO);
434
435 device_set_desc(self, "Marvell Integrated PCI/PCI-E Controller");
436 return (BUS_PROBE_DEFAULT);
437 }
438
439 static int
440 mv_pcib_attach(device_t self)
441 {
442 struct mv_pcib_softc *sc;
443 phandle_t node, parnode;
444 uint32_t val, reg0;
445 int err, bus, devfn, port_id;
446
447 sc = device_get_softc(self);
448 sc->sc_dev = self;
449
450 node = ofw_bus_get_node(self);
451 parnode = OF_parent(node);
452
453 if (OF_getencprop(node, "marvell,pcie-port", &(port_id),
454 sizeof(port_id)) <= 0) {
455 /* If port ID does not exist in the FDT set value to 0 */
456 if (!OF_hasprop(node, "marvell,pcie-port"))
457 port_id = 0;
458 else
459 return(ENXIO);
460 }
461
462 sc->ap_segment = port_id;
463
464 if (ofw_bus_node_is_compatible(node, "mrvl,pcie")) {
465 sc->sc_type = MV_TYPE_PCIE;
466 sc->sc_win_target = MV_WIN_PCIE_TARGET(port_id);
467 sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR(port_id);
468 sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR(port_id);
469 sc->sc_skip_enable_procedure = 1;
470 } else if (ofw_bus_node_is_compatible(parnode, "marvell,armada-370-pcie")) {
471 sc->sc_type = MV_TYPE_PCIE;
472 sc->sc_win_target = MV_WIN_PCIE_TARGET_ARMADA38X(port_id);
473 sc->sc_mem_win_attr = MV_WIN_PCIE_MEM_ATTR_ARMADA38X(port_id);
474 sc->sc_io_win_attr = MV_WIN_PCIE_IO_ATTR_ARMADA38X(port_id);
475 sc->sc_enable_find_root_slot = 1;
476 } else if (ofw_bus_node_is_compatible(node, "mrvl,pci")) {
477 sc->sc_type = MV_TYPE_PCI;
478 sc->sc_win_target = MV_WIN_PCI_TARGET;
479 sc->sc_mem_win_attr = MV_WIN_PCI_MEM_ATTR;
480 sc->sc_io_win_attr = MV_WIN_PCI_IO_ATTR;
481 } else
482 return (ENXIO);
483
484 /*
485 * Retrieve our mem-mapped registers range.
486 */
487 sc->sc_rid = 0;
488 sc->sc_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &sc->sc_rid,
489 RF_ACTIVE);
490 if (sc->sc_res == NULL) {
491 device_printf(self, "could not map memory\n");
492 return (ENXIO);
493 }
494 sc->sc_bst = rman_get_bustag(sc->sc_res);
495 sc->sc_bsh = rman_get_bushandle(sc->sc_res);
496
497 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_CONTROL);
498 sc->sc_mode = (val & PCIE_CONTROL_ROOT_CMPLX ? MV_MODE_ROOT :
499 MV_MODE_ENDPOINT);
500
501 /*
502 * Get PCI interrupt info.
503 */
504 if (sc->sc_mode == MV_MODE_ROOT)
505 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(pcell_t));
506
507 /*
508 * Configure decode windows for PCI(E) access.
509 */
510 if (mv_pcib_decode_win(node, sc) != 0)
511 return (ENXIO);
512
513 mv_pcib_hw_cfginit();
514
515 /*
516 * Enable PCIE device.
517 */
518 mv_pcib_enable(sc, port_id);
519
520 /*
521 * Memory management.
522 */
523 err = mv_pcib_mem_init(sc);
524 if (err)
525 return (err);
526
527 /*
528 * Preliminary bus enumeration to find first linked devices and set
529 * appropriate bus number from which should start the actual enumeration
530 */
531 for (bus = 0; bus < PCI_BUSMAX; bus++) {
532 for (devfn = 0; devfn < mv_pcib_maxslots(self); devfn++) {
533 reg0 = mv_pcib_read_config(self, bus, devfn, devfn & 0x7, 0x0, 4);
534 if (reg0 == (~0U))
535 continue; /* no device */
536 else {
537 sc->sc_busnr = bus; /* update bus number */
538 break;
539 }
540 }
541 }
542
543 if (sc->sc_mode == MV_MODE_ROOT) {
544 err = mv_pcib_init(sc, sc->sc_busnr,
545 mv_pcib_maxslots(sc->sc_dev));
546 if (err)
547 goto error;
548
549 device_add_child(self, "pci", -1);
550 } else {
551 sc->sc_devnr = 1;
552 bus_space_write_4(sc->sc_bst, sc->sc_bsh,
553 PCIE_REG_STATUS, 1 << PCIE_STATUS_DEV_OFFS);
554 device_add_child(self, "pci_ep", -1);
555 }
556
557 mtx_init(&sc->sc_msi_mtx, "msi_mtx", NULL, MTX_DEF);
558 return (bus_generic_attach(self));
559
560 error:
561 /* XXX SYS_RES_ should be released here */
562 rman_fini(&sc->sc_mem_rman);
563 rman_fini(&sc->sc_io_rman);
564
565 return (err);
566 }
567
568 static void
569 mv_pcib_enable(struct mv_pcib_softc *sc, uint32_t unit)
570 {
571 uint32_t val;
572 int timeout;
573
574 if (sc->sc_skip_enable_procedure)
575 goto pcib_enable_root_mode;
576
577 /*
578 * Check if PCIE device is enabled.
579 */
580 if ((sc->sc_skip_enable_procedure == 0) &&
581 (read_cpu_ctrl(CPU_CONTROL) & CPU_CONTROL_PCIE_DISABLE(unit))) {
582 write_cpu_ctrl(CPU_CONTROL, read_cpu_ctrl(CPU_CONTROL) &
583 ~(CPU_CONTROL_PCIE_DISABLE(unit)));
584
585 timeout = PCIE_LINK_TIMEOUT;
586 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
587 PCIE_REG_STATUS);
588 while (((val & PCIE_STATUS_LINK_DOWN) == 1) && (timeout > 0)) {
589 DELAY(1000);
590 timeout -= 1000;
591 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh,
592 PCIE_REG_STATUS);
593 }
594 }
595
596 pcib_enable_root_mode:
597 if (sc->sc_mode == MV_MODE_ROOT) {
598 /*
599 * Enable PCI bridge.
600 */
601 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND);
602 val |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN |
603 PCIM_CMD_MEMEN | PCIM_CMD_PORTEN;
604 bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIR_COMMAND, val);
605 }
606 }
607
608 static int
609 mv_pcib_mem_init(struct mv_pcib_softc *sc)
610 {
611 int err;
612
613 /*
614 * Memory management.
615 */
616 sc->sc_mem_rman.rm_type = RMAN_ARRAY;
617 err = rman_init(&sc->sc_mem_rman);
618 if (err)
619 return (err);
620
621 sc->sc_io_rman.rm_type = RMAN_ARRAY;
622 err = rman_init(&sc->sc_io_rman);
623 if (err) {
624 rman_fini(&sc->sc_mem_rman);
625 return (err);
626 }
627
628 err = rman_manage_region(&sc->sc_mem_rman, sc->sc_mem_base,
629 sc->sc_mem_base + sc->sc_mem_size - 1);
630 if (err)
631 goto error;
632
633 err = rman_manage_region(&sc->sc_io_rman, sc->sc_io_base,
634 sc->sc_io_base + sc->sc_io_size - 1);
635 if (err)
636 goto error;
637
638 return (0);
639
640 error:
641 rman_fini(&sc->sc_mem_rman);
642 rman_fini(&sc->sc_io_rman);
643
644 return (err);
645 }
646
647 static inline uint32_t
648 pcib_bit_get(uint32_t *map, uint32_t bit)
649 {
650 uint32_t n = bit / BITS_PER_UINT32;
651
652 bit = bit % BITS_PER_UINT32;
653 return (map[n] & (1 << bit));
654 }
655
656 static inline void
657 pcib_bit_set(uint32_t *map, uint32_t bit)
658 {
659 uint32_t n = bit / BITS_PER_UINT32;
660
661 bit = bit % BITS_PER_UINT32;
662 map[n] |= (1 << bit);
663 }
664
665 static inline uint32_t
666 pcib_map_check(uint32_t *map, uint32_t start, uint32_t bits)
667 {
668 uint32_t i;
669
670 for (i = start; i < start + bits; i++)
671 if (pcib_bit_get(map, i))
672 return (0);
673
674 return (1);
675 }
676
677 static inline void
678 pcib_map_set(uint32_t *map, uint32_t start, uint32_t bits)
679 {
680 uint32_t i;
681
682 for (i = start; i < start + bits; i++)
683 pcib_bit_set(map, i);
684 }
685
686 /*
687 * The idea of this allocator is taken from ARM No-Cache memory
688 * management code (sys/arm/arm/vm_machdep.c).
689 */
690 static bus_addr_t
691 pcib_alloc(struct mv_pcib_softc *sc, uint32_t smask)
692 {
693 uint32_t bits, bits_limit, i, *map, min_alloc, size;
694 bus_addr_t addr = 0;
695 bus_addr_t base;
696
697 if (smask & 1) {
698 base = sc->sc_io_base;
699 min_alloc = PCI_MIN_IO_ALLOC;
700 bits_limit = sc->sc_io_size / min_alloc;
701 map = sc->sc_io_map;
702 smask &= ~0x3;
703 } else {
704 base = sc->sc_mem_base;
705 min_alloc = PCI_MIN_MEM_ALLOC;
706 bits_limit = sc->sc_mem_size / min_alloc;
707 map = sc->sc_mem_map;
708 smask &= ~0xF;
709 }
710
711 size = ~smask + 1;
712 bits = size / min_alloc;
713
714 for (i = 0; i + bits <= bits_limit; i += bits)
715 if (pcib_map_check(map, i, bits)) {
716 pcib_map_set(map, i, bits);
717 addr = base + (i * min_alloc);
718 return (addr);
719 }
720
721 return (addr);
722 }
723
724 static int
725 mv_pcib_init_bar(struct mv_pcib_softc *sc, int bus, int slot, int func,
726 int barno)
727 {
728 uint32_t addr, bar;
729 int reg, width;
730
731 reg = PCIR_BAR(barno);
732
733 /*
734 * Need to init the BAR register with 0xffffffff before correct
735 * value can be read.
736 */
737 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4);
738 bar = mv_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4);
739 if (bar == 0)
740 return (1);
741
742 /* Calculate BAR size: 64 or 32 bit (in 32-bit units) */
743 width = ((bar & 7) == 4) ? 2 : 1;
744
745 addr = pcib_alloc(sc, bar);
746 if (!addr)
747 return (-1);
748
749 if (bootverbose)
750 printf("PCI %u:%u:%u: reg %x: smask=%08x: addr=%08x\n",
751 bus, slot, func, reg, bar, addr);
752
753 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4);
754 if (width == 2)
755 mv_pcib_write_config(sc->sc_dev, bus, slot, func, reg + 4,
756 0, 4);
757
758 return (width);
759 }
760
761 static void
762 mv_pcib_init_bridge(struct mv_pcib_softc *sc, int bus, int slot, int func)
763 {
764 bus_addr_t io_base, mem_base;
765 uint32_t io_limit, mem_limit;
766 int secbus;
767
768 io_base = sc->sc_io_base;
769 io_limit = io_base + sc->sc_io_size - 1;
770 mem_base = sc->sc_mem_base;
771 mem_limit = mem_base + sc->sc_mem_size - 1;
772
773 /* Configure I/O decode registers */
774 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEL_1,
775 io_base >> 8, 1);
776 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOBASEH_1,
777 io_base >> 16, 2);
778 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITL_1,
779 io_limit >> 8, 1);
780 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_IOLIMITH_1,
781 io_limit >> 16, 2);
782
783 /* Configure memory decode registers */
784 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMBASE_1,
785 mem_base >> 16, 2);
786 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_MEMLIMIT_1,
787 mem_limit >> 16, 2);
788
789 /* Disable memory prefetch decode */
790 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEL_1,
791 0x10, 2);
792 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMBASEH_1,
793 0x0, 4);
794 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITL_1,
795 0xF, 2);
796 mv_pcib_write_config(sc->sc_dev, bus, slot, func, PCIR_PMLIMITH_1,
797 0x0, 4);
798
799 secbus = mv_pcib_read_config(sc->sc_dev, bus, slot, func,
800 PCIR_SECBUS_1, 1);
801
802 /* Configure buses behind the bridge */
803 mv_pcib_init(sc, secbus, PCI_SLOTMAX);
804 }
805
806 static int
807 mv_pcib_init(struct mv_pcib_softc *sc, int bus, int maxslot)
808 {
809 int slot, func, maxfunc, error;
810 uint8_t hdrtype, command, class, subclass;
811
812 for (slot = 0; slot <= maxslot; slot++) {
813 maxfunc = 0;
814 for (func = 0; func <= maxfunc; func++) {
815 hdrtype = mv_pcib_read_config(sc->sc_dev, bus, slot,
816 func, PCIR_HDRTYPE, 1);
817
818 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
819 continue;
820
821 if (func == 0 && (hdrtype & PCIM_MFDEV))
822 maxfunc = PCI_FUNCMAX;
823
824 command = mv_pcib_read_config(sc->sc_dev, bus, slot,
825 func, PCIR_COMMAND, 1);
826 command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN);
827 mv_pcib_write_config(sc->sc_dev, bus, slot, func,
828 PCIR_COMMAND, command, 1);
829
830 error = mv_pcib_init_all_bars(sc, bus, slot, func,
831 hdrtype);
832
833 if (error)
834 return (error);
835
836 command |= PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN |
837 PCIM_CMD_PORTEN;
838 mv_pcib_write_config(sc->sc_dev, bus, slot, func,
839 PCIR_COMMAND, command, 1);
840
841 /* Handle PCI-PCI bridges */
842 class = mv_pcib_read_config(sc->sc_dev, bus, slot,
843 func, PCIR_CLASS, 1);
844 subclass = mv_pcib_read_config(sc->sc_dev, bus, slot,
845 func, PCIR_SUBCLASS, 1);
846
847 if (class != PCIC_BRIDGE ||
848 subclass != PCIS_BRIDGE_PCI)
849 continue;
850
851 mv_pcib_init_bridge(sc, bus, slot, func);
852 }
853 }
854
855 /* Enable all ABCD interrupts */
856 pcib_write_irq_mask(sc, (0xF << 24));
857
858 return (0);
859 }
860
861 static int
862 mv_pcib_init_all_bars(struct mv_pcib_softc *sc, int bus, int slot,
863 int func, int hdrtype)
864 {
865 int maxbar, bar, i;
866
867 maxbar = (hdrtype & PCIM_HDRTYPE) ? 0 : 6;
868 bar = 0;
869
870 /* Program the base address registers */
871 while (bar < maxbar) {
872 i = mv_pcib_init_bar(sc, bus, slot, func, bar);
873 bar += i;
874 if (i < 0) {
875 device_printf(sc->sc_dev,
876 "PCI IO/Memory space exhausted\n");
877 return (ENOMEM);
878 }
879 }
880
881 return (0);
882 }
883
884 static struct resource *
885 mv_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
886 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
887 {
888 struct mv_pcib_softc *sc = device_get_softc(dev);
889 struct rman *rm = NULL;
890 struct resource *res;
891
892 switch (type) {
893 case SYS_RES_IOPORT:
894 rm = &sc->sc_io_rman;
895 break;
896 case SYS_RES_MEMORY:
897 rm = &sc->sc_mem_rman;
898 break;
899 #ifdef PCI_RES_BUS
900 case PCI_RES_BUS:
901 return (pci_domain_alloc_bus(sc->ap_segment, child, rid, start,
902 end, count, flags));
903 #endif
904 default:
905 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), dev,
906 type, rid, start, end, count, flags));
907 }
908
909 if (RMAN_IS_DEFAULT_RANGE(start, end)) {
910 start = sc->sc_mem_base;
911 end = sc->sc_mem_base + sc->sc_mem_size - 1;
912 count = sc->sc_mem_size;
913 }
914
915 if ((start < sc->sc_mem_base) || (start + count - 1 != end) ||
916 (end > sc->sc_mem_base + sc->sc_mem_size - 1))
917 return (NULL);
918
919 res = rman_reserve_resource(rm, start, end, count, flags, child);
920 if (res == NULL)
921 return (NULL);
922
923 rman_set_rid(res, *rid);
924 rman_set_bustag(res, fdtbus_bs_tag);
925 rman_set_bushandle(res, start);
926
927 if (flags & RF_ACTIVE)
928 if (bus_activate_resource(child, type, *rid, res)) {
929 rman_release_resource(res);
930 return (NULL);
931 }
932
933 return (res);
934 }
935
936 static int
937 mv_pcib_release_resource(device_t dev, device_t child, int type, int rid,
938 struct resource *res)
939 {
940 #ifdef PCI_RES_BUS
941 struct mv_pcib_softc *sc = device_get_softc(dev);
942
943 if (type == PCI_RES_BUS)
944 return (pci_domain_release_bus(sc->ap_segment, child, rid, res));
945 #endif
946 if (type != SYS_RES_IOPORT && type != SYS_RES_MEMORY)
947 return (BUS_RELEASE_RESOURCE(device_get_parent(dev), child,
948 type, rid, res));
949
950 return (rman_release_resource(res));
951 }
952
953 static int
954 mv_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
955 {
956 struct mv_pcib_softc *sc = device_get_softc(dev);
957
958 switch (which) {
959 case PCIB_IVAR_BUS:
960 *result = sc->sc_busnr;
961 return (0);
962 case PCIB_IVAR_DOMAIN:
963 *result = device_get_unit(dev);
964 return (0);
965 }
966
967 return (ENOENT);
968 }
969
970 static int
971 mv_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
972 {
973 struct mv_pcib_softc *sc = device_get_softc(dev);
974
975 switch (which) {
976 case PCIB_IVAR_BUS:
977 sc->sc_busnr = value;
978 return (0);
979 }
980
981 return (ENOENT);
982 }
983
984 static inline void
985 pcib_write_irq_mask(struct mv_pcib_softc *sc, uint32_t mask)
986 {
987
988 if (sc->sc_type != MV_TYPE_PCIE)
989 return;
990
991 bus_space_write_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_IRQ_MASK, mask);
992 }
993
994 static void
995 mv_pcib_hw_cfginit(void)
996 {
997 static int opened = 0;
998
999 if (opened)
1000 return;
1001
1002 mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
1003 opened = 1;
1004 }
1005
1006 static uint32_t
1007 mv_pcib_hw_cfgread(struct mv_pcib_softc *sc, u_int bus, u_int slot,
1008 u_int func, u_int reg, int bytes)
1009 {
1010 uint32_t addr, data, ca, cd;
1011
1012 ca = (sc->sc_type != MV_TYPE_PCI) ?
1013 PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR;
1014 cd = (sc->sc_type != MV_TYPE_PCI) ?
1015 PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA;
1016 addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) |
1017 PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg);
1018
1019 mtx_lock_spin(&pcicfg_mtx);
1020 bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr);
1021
1022 data = ~0;
1023 switch (bytes) {
1024 case 1:
1025 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh,
1026 cd + (reg & 3));
1027 break;
1028 case 2:
1029 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh,
1030 cd + (reg & 2)));
1031 break;
1032 case 4:
1033 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh,
1034 cd));
1035 break;
1036 }
1037 mtx_unlock_spin(&pcicfg_mtx);
1038 return (data);
1039 }
1040
1041 static void
1042 mv_pcib_hw_cfgwrite(struct mv_pcib_softc *sc, u_int bus, u_int slot,
1043 u_int func, u_int reg, uint32_t data, int bytes)
1044 {
1045 uint32_t addr, ca, cd;
1046
1047 ca = (sc->sc_type != MV_TYPE_PCI) ?
1048 PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR;
1049 cd = (sc->sc_type != MV_TYPE_PCI) ?
1050 PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA;
1051 addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) |
1052 PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg);
1053
1054 mtx_lock_spin(&pcicfg_mtx);
1055 bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr);
1056
1057 switch (bytes) {
1058 case 1:
1059 bus_space_write_1(sc->sc_bst, sc->sc_bsh,
1060 cd + (reg & 3), data);
1061 break;
1062 case 2:
1063 bus_space_write_2(sc->sc_bst, sc->sc_bsh,
1064 cd + (reg & 2), htole16(data));
1065 break;
1066 case 4:
1067 bus_space_write_4(sc->sc_bst, sc->sc_bsh,
1068 cd, htole32(data));
1069 break;
1070 }
1071 mtx_unlock_spin(&pcicfg_mtx);
1072 }
1073
1074 static int
1075 mv_pcib_maxslots(device_t dev)
1076 {
1077 struct mv_pcib_softc *sc = device_get_softc(dev);
1078
1079 return ((sc->sc_type != MV_TYPE_PCI) ? 1 : PCI_SLOTMAX);
1080 }
1081
1082 static int
1083 mv_pcib_root_slot(device_t dev, u_int bus, u_int slot, u_int func)
1084 {
1085 struct mv_pcib_softc *sc = device_get_softc(dev);
1086 uint32_t vendor, device;
1087
1088 /* On platforms other than Armada38x, root link is always at slot 0 */
1089 if (!sc->sc_enable_find_root_slot)
1090 return (slot == 0);
1091
1092 vendor = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_VENDOR,
1093 PCIR_VENDOR_LENGTH);
1094 device = mv_pcib_hw_cfgread(sc, bus, slot, func, PCIR_DEVICE,
1095 PCIR_DEVICE_LENGTH) & MV_DEV_FAMILY_MASK;
1096
1097 return (vendor == PCI_VENDORID_MRVL && device == MV_DEV_ARMADA38X);
1098 }
1099
1100 static uint32_t
1101 mv_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
1102 u_int reg, int bytes)
1103 {
1104 struct mv_pcib_softc *sc = device_get_softc(dev);
1105
1106 /* Return ~0 if link is inactive or trying to read from Root */
1107 if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) &
1108 PCIE_STATUS_LINK_DOWN) || mv_pcib_root_slot(dev, bus, slot, func))
1109 return (~0U);
1110
1111 return (mv_pcib_hw_cfgread(sc, bus, slot, func, reg, bytes));
1112 }
1113
1114 static void
1115 mv_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
1116 u_int reg, uint32_t val, int bytes)
1117 {
1118 struct mv_pcib_softc *sc = device_get_softc(dev);
1119
1120 /* Return if link is inactive or trying to write to Root */
1121 if ((bus_space_read_4(sc->sc_bst, sc->sc_bsh, PCIE_REG_STATUS) &
1122 PCIE_STATUS_LINK_DOWN) || mv_pcib_root_slot(dev, bus, slot, func))
1123 return;
1124
1125 mv_pcib_hw_cfgwrite(sc, bus, slot, func, reg, val, bytes);
1126 }
1127
1128 static int
1129 mv_pcib_route_interrupt(device_t bus, device_t dev, int pin)
1130 {
1131 struct mv_pcib_softc *sc;
1132 struct ofw_pci_register reg;
1133 uint32_t pintr, mintr[4];
1134 int icells;
1135 phandle_t iparent;
1136
1137 sc = device_get_softc(bus);
1138 pintr = pin;
1139
1140 /* Fabricate imap information in case this isn't an OFW device */
1141 bzero(®, sizeof(reg));
1142 reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) |
1143 (pci_get_slot(dev) << OFW_PCI_PHYS_HI_DEVICESHIFT) |
1144 (pci_get_function(dev) << OFW_PCI_PHYS_HI_FUNCTIONSHIFT);
1145
1146 icells = ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->sc_pci_iinfo,
1147 ®, sizeof(reg), &pintr, sizeof(pintr), mintr, sizeof(mintr),
1148 &iparent);
1149 if (icells > 0)
1150 return (ofw_bus_map_intr(dev, iparent, icells, mintr));
1151
1152 /* Maybe it's a real interrupt, not an intpin */
1153 if (pin > 4)
1154 return (pin);
1155
1156 device_printf(bus, "could not route pin %d for device %d.%d\n",
1157 pin, pci_get_slot(dev), pci_get_function(dev));
1158 return (PCI_INVALID_IRQ);
1159 }
1160
1161 static int
1162 mv_pcib_decode_win(phandle_t node, struct mv_pcib_softc *sc)
1163 {
1164 struct mv_pci_range io_space, mem_space;
1165 device_t dev;
1166 int error;
1167
1168 dev = sc->sc_dev;
1169
1170 if ((error = mv_pci_ranges(node, &io_space, &mem_space)) != 0) {
1171 device_printf(dev, "could not retrieve 'ranges' data\n");
1172 return (error);
1173 }
1174
1175 /* Configure CPU decoding windows */
1176 error = decode_win_cpu_set(sc->sc_win_target,
1177 sc->sc_io_win_attr, io_space.base_parent, io_space.len, ~0);
1178 if (error < 0) {
1179 device_printf(dev, "could not set up CPU decode "
1180 "window for PCI IO\n");
1181 return (ENXIO);
1182 }
1183 error = decode_win_cpu_set(sc->sc_win_target,
1184 sc->sc_mem_win_attr, mem_space.base_parent, mem_space.len,
1185 mem_space.base_parent);
1186 if (error < 0) {
1187 device_printf(dev, "could not set up CPU decode "
1188 "windows for PCI MEM\n");
1189 return (ENXIO);
1190 }
1191
1192 sc->sc_io_base = io_space.base_parent;
1193 sc->sc_io_size = io_space.len;
1194
1195 sc->sc_mem_base = mem_space.base_parent;
1196 sc->sc_mem_size = mem_space.len;
1197
1198 return (0);
1199 }
1200
1201 static int
1202 mv_pcib_map_msi(device_t dev, device_t child, int irq, uint64_t *addr,
1203 uint32_t *data)
1204 {
1205 struct mv_pcib_softc *sc;
1206
1207 sc = device_get_softc(dev);
1208 if (!sc->sc_msi_supported)
1209 return (ENOTSUP);
1210
1211 irq = irq - MSI_IRQ;
1212
1213 /* validate parameters */
1214 if (isclr(&sc->sc_msi_bitmap, irq)) {
1215 device_printf(dev, "invalid MSI 0x%x\n", irq);
1216 return (EINVAL);
1217 }
1218
1219 mv_msi_data(irq, addr, data);
1220
1221 debugf("%s: irq: %d addr: %jx data: %x\n",
1222 __func__, irq, *addr, *data);
1223
1224 return (0);
1225 }
1226
1227 static int
1228 mv_pcib_alloc_msi(device_t dev, device_t child, int count,
1229 int maxcount __unused, int *irqs)
1230 {
1231 struct mv_pcib_softc *sc;
1232 u_int start = 0, i;
1233
1234 sc = device_get_softc(dev);
1235 if (!sc->sc_msi_supported)
1236 return (ENOTSUP);
1237
1238 if (powerof2(count) == 0 || count > MSI_IRQ_NUM)
1239 return (EINVAL);
1240
1241 mtx_lock(&sc->sc_msi_mtx);
1242
1243 for (start = 0; (start + count) < MSI_IRQ_NUM; start++) {
1244 for (i = start; i < start + count; i++) {
1245 if (isset(&sc->sc_msi_bitmap, i))
1246 break;
1247 }
1248 if (i == start + count)
1249 break;
1250 }
1251
1252 if ((start + count) == MSI_IRQ_NUM) {
1253 mtx_unlock(&sc->sc_msi_mtx);
1254 return (ENXIO);
1255 }
1256
1257 for (i = start; i < start + count; i++) {
1258 setbit(&sc->sc_msi_bitmap, i);
1259 *irqs++ = MSI_IRQ + i;
1260 }
1261 debugf("%s: start: %x count: %x\n", __func__, start, count);
1262
1263 mtx_unlock(&sc->sc_msi_mtx);
1264 return (0);
1265 }
1266
1267 static int
1268 mv_pcib_release_msi(device_t dev, device_t child, int count, int *irqs)
1269 {
1270 struct mv_pcib_softc *sc;
1271 u_int i;
1272
1273 sc = device_get_softc(dev);
1274 if(!sc->sc_msi_supported)
1275 return (ENOTSUP);
1276
1277 mtx_lock(&sc->sc_msi_mtx);
1278
1279 for (i = 0; i < count; i++)
1280 clrbit(&sc->sc_msi_bitmap, irqs[i] - MSI_IRQ);
1281
1282 mtx_unlock(&sc->sc_msi_mtx);
1283 return (0);
1284 }
Cache object: d6b3acccce626277d9329ed644769118
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